CN103631303A - Soft starting circuit for voltage-stabilized power supply chip - Google Patents

Abstract

The invention discloses a soft-start circuit for a stabilized power supply chip, which mainly solves the problems that the existing soft-start circuit occupies a large chip area and increases power consumption. It includes a PMOS transistor M1 and two NMOS transistors M2 and M3; the source of the PMOS transistor M1 is connected to the power supply VDD, the gate is connected to the control signal ONX, and the drain is connected to the drain of the first NMOS transistor M2 and the second NMOS transistor M3 The gate of the first NMOS transistor M2 is grounded, the gate is connected to the reference voltage V _REF ; the source of the second NMOS transistor M3 is grounded, and the drain is connected to the reference voltage V _REF . The high-level control signal ONX turns off the PMOS transistor M1, causing its drain voltage to decrease slowly, weakening the conduction capability of the second NMOS transistor M3, thereby weakening its short-circuit effect on the reference voltage V _REF , and realizing the reference voltage V _REF from Zero slowly ramps up to the preset value. The invention prolongs the establishment time of the reference voltage V _REF so that it is established synchronously with the output voltage V _OUT of the stabilized power supply chip, effectively suppressing the surge current during the start-up process of the stabilized voltage power supply chip.

Description

Soft start circuit for regulated power chip

technical field

The invention belongs to the technical field of electronic circuits, in particular to a soft start circuit, which can be used for linear regulators and switching power supplies of analog integrated circuits.

Background technique

In the field of power management, the reference voltage signal and the conduction state of the feedback voltage rate tube or switch tube are used. In the steady-state working mode, the reference voltage signal is basically equal to the feedback voltage signal. However, during the power-on process of the switching power supply chip, the internal reference voltage is established prior to the output voltage, that is, when the internal reference voltage reaches the steady-state value When , the output voltage remains zero, and the feedback voltage signal of the output voltage remains zero. The control voltage output by the error operational amplifier EA causes the switching regulator power supply to output current in the form of surge current. Usually the peak value of this current is much larger than the normal steady-state output current value, which will consume or even directly damage the voltage regulator chip.

At present, there are two main schemes for weakening or even eliminating surge current circuits:

The first solution is to use gradual output current limit threshold to clamp the maximum output current, but this solution increases the power consumption of the chip, damages its low static power consumption and increases the complexity of the overall circuit.

The second solution is to use a variable voltage to replace the reference voltage at the positive input of the error operational amplifier EA. The variable voltage is usually implemented by using a current source to charge a large capacitor or using a complex digital circuit. Figure 1 shows a typical linear regulator application topology, which includes linear soft-start circuit, error operational amplifier EA, power transistor M4, output voltage feedback resistors R1, R2, output capacitor C2, parasitic resistor R3, output resistor R4 . The signals shown are the power supply VDD, the linear voltage V _line increasing from zero, the reference voltage V _REF , the output voltage V _DR of the error operational amplifier EA, the output voltage V _OUT of the linear regulator and the feedback voltage V _FB of this voltage . Among them, the linear soft-start circuit charges the capacitor C1 through the current source I1 during the power-on process, and forms a linear voltage V _line increasing from zero on the capacitor C1, and uses this linear voltage V _line to replace the reference voltage V _REF and the output Feedback voltage V _FB is compared, so that the output voltage rises slowly to achieve the purpose of limiting the inrush current. However, since the capacitance area to be used in this kind of soft-start circuit can reach the sum of all other capacitance areas inside the power supply chip, the chip area is greatly increased, and even because the capacitance area is too large, it is necessary to use an external connection of the voltage stabilization chip. In this way, the integration characteristics of the chip are damaged.

Contents of the invention

The object of the present invention is to address the above-mentioned shortcomings of the existing soft-start circuit, to provide a soft-start circuit with a simple structure, a small chip area, and no static loss, so as to suppress the surge current of the stabilized power supply chip.

The technical idea of realizing the purpose of the present invention: obtain a slowly changing control voltage by using the conduction characteristic of the CMOS device itself, and use the control voltage to change the conduction characteristic of the MOS transistor, so that the short-circuit effect of the MOS transistor on the reference voltage V _REF is gradually weakened , finally disappear, so as to realize the reference voltage V _REF slowly increasing from zero to the preset value.

The soft start circuit of the present invention is characterized in that it comprises a PMOS transistor M1 and two NMOS transistors M2, M3;

The source of the PMOS transistor M1 is connected to the power supply VDD, its gate is connected to the external control signal ONX, and its drain is respectively connected to the drain of the first NMOS transistor M2 and the gate of the second NMOS transistor M3;

The source of the first NMOS transistor M2 is grounded, and its gate is connected to the reference voltage V _REF ;

The source of the second NMOS transistor M3 is grounded, and the drain is connected to the reference voltage V _REF .

Preferably, the PMOS transistor M1 and the two NMOS transistors M2 and M3 are all low-voltage transistors with a source-to-drain withstand voltage less than or equal to 5V.

As a preferable connection between the drain of the second NMOS transistor M3 and the reference voltage V _REF , an adjustment resistor R1 is used to adjust the soft-start time and surge current value. The parameters of the adjustment resistor R1 are based on the soft-start time and the allowable surge The current value is selected.

Compared with the prior art, the present invention has the following advantages:

(1) The soft-start circuit of the present invention only uses three MOS transistors. Compared with the existing linear structure using capacitance or digital structure using multiple D flip-flops, the structure is simple and the chip area is reduced.

(2) The soft-start circuit of the present invention does not need to increase the soft-start current during the soft-start process, and does not generate logic gate flipping glitch current, and after the soft-start is completed, each branch is in the cut-off state, and there is no power loss. Compared with the existing linear structure using capacitance or using multiple D flip-flop digital structures, the power loss of the chip is reduced.

Description of drawings

Figure 1 is a schematic diagram of a traditional linear soft-start circuit;

Fig. 2 is the schematic circuit diagram of the first embodiment of the present invention;

Fig. 3 is the schematic circuit diagram of the second embodiment of the present invention;

FIG. 4 is an application example diagram of the first embodiment of the present invention;

Fig. 5 is an application example diagram of the second embodiment of the present invention;

Detailed ways

The present invention will be further described below in conjunction with accompanying drawings and embodiments thereof.

Example 1

Referring to Fig. 2, the soft start circuit of the present invention includes: a low-voltage PMOS transistor M1 with a withstand voltage between the source and the drain less than or equal to 5V, and two low-voltage NMOS transistors with a withstand voltage between the source and the drain less than or equal to 5V M2, M3;

The power supply VDD is connected to the source of the low-voltage PMOS transistor M1, the control signal ONX is connected to the gate of the low-voltage PMOS transistor M1, and the reference voltage V _REF is respectively connected to the gate of the first low-voltage NMOS transistor M2 and the drain of the second low-voltage NMOS transistor M3. The drain of the low-voltage PMOS transistor M1 is respectively connected to the drain of the first low-voltage NMOS transistor M2 and the gate of the second low-voltage NMOS transistor M3, and the source of the first low-voltage NMOS transistor M2 and the source of the second low-voltage NMOS transistor M3 are grounded. .

Figure 4 shows a typical linear regulator application topology, which includes the soft-start circuit shown in box 2, error operational amplifier EA, power transistor M4, output voltage feedback resistors R1, R2, output capacitor C2, and parasitic resistor R3 , the output resistor R4. The signals shown are the power supply VDD, the control signal ONX, the reference voltage V _REF , the output voltage V _DR of the error operational amplifier EA, the output voltage V _OUT of the linear regulator and the feedback voltage V _FB of the voltage.

Referring to Figure 4, the working principle of this example is as follows:

When the linear voltage regulator is not enabled, the linear voltage regulator does not work, the reference voltage V _REF is not established, its voltage value is zero, and the linear voltage regulator has no output current. The control signal ONX maintains a low level, the low-voltage PMOS transistor M1 is linearly turned on, the first low-voltage NMOS transistor M2 is turned off, and the drain voltage of the low-voltage PMOS transistor M1 is at a high level VDD, which makes the second low-voltage NMOS transistor M3 linearly turned on , maintaining the voltage value of the reference voltage V _REF as zero.

After the linear regulator is enabled, the control signal ONX turns from low level to high level, and the soft start circuit works, that is, the control signal ONX turns off the low-voltage PMOS transistor M1. At this time, the voltage value of the reference voltage V _REF is zero, and the first The low-voltage NMOS transistor M2 is turned off, so that the drain of the low-voltage PMOS transistor M1 is in an equivalent floating state. Due to the drain-substrate leakage current of the first low-voltage NMOS transistor M2, the voltage at the drain of the low-voltage PMOS transistor M1 slowly decreases, and this voltage directly controls the conduction state of the second low-voltage NMOS transistor M3. As the low-voltage PMOS transistor M1 As the drain terminal voltage decreases, the conduction capability of the second low-voltage NMOS transistor M3 gradually decreases, and its short-circuit effect gradually weakens, so that the reference voltage V _REF slowly rises from zero, and finally reaches the preset value. The reference voltage V _REF and the output feedback voltage V _FB slowly rising from zero are differentially amplified by the error operational amplifier EA to output the voltage V _DR , which controls the power transistor M4 of the linear regulator to realize the output feedback voltage V _FB and the reference voltage V _REF changes synchronously. Since the output voltage V _OUT is divided by the feedback resistors R1 and R2 to obtain the output feedback voltage V _FB , the output feedback voltage V _FB changes synchronously with the reference voltage V _REF , ensuring that the output voltage V _OUT changes synchronously with the reference voltage V _REF . It can be seen that the establishment time of the reference voltage V _REF can be extended through the soft start circuit of the present invention, and the reference voltage V _REF can be established synchronously with the output voltage V _OUT of the linear regulator. It avoids the extreme minimum value of the output voltage V _DR of the operational amplifier EA caused by the excessive difference between the reference voltage V _REF and the feedback voltage V _FB , and realizes the function of suppressing the surge current.

When the voltage at the drain end of the low voltage PMOS transistor M1 drops below the turn-on threshold voltage of the second low voltage NMOS transistor M3, the second low voltage NMOS transistor M3 is completely turned off, and the soft start process ends. At this time, the low-voltage PMOS transistor M1 maintains an off state, the first low-voltage NMOS transistor M2 maintains a linear conduction state, and the second low-voltage NMOS transistor M3 maintains an off state. The second low-voltage NMOS transistor M3 is turned off, and it no longer affects the reference voltage V _REF , the soft-start function completely disappears, and no longer affects the output voltage and current of the linear regulator.

Example 2

Referring to Figure 3, on the basis of the soft-start circuit shown in Figure 2, a low-voltage adjustment resistor R5 is added and connected between the drain of the second NMOS transistor M3 and the reference voltage V _REF . The adjustment resistor R5 is used to adjust the soft-start time and wave Inrush current value, the parameters of the adjustment resistor R1 are selected according to the soft-start time and the allowable inrush current value, for example, R5 is equal to 60kΩ, the required start-up time is 1.5ms, and the maximum inrush current is equal to 0.6A; R5 is equal to 180kΩ, the required The startup time is 500us, and the maximum surge current is equal to 1.2A.

Figure 5 shows a typical linear regulator application topology, which includes the soft-start circuit shown in box 3, error operational amplifier EA, power transistor M4, output voltage feedback resistors R1, R2, output capacitor C2, and parasitic resistor R3 , the output resistor R4. The signals shown are the power supply VDD, the control signal ONX, the reference voltage V _REF , the output voltage V _DR of the error operational amplifier EA, the output voltage V _OUT of the linear regulator and the feedback voltage V _FB of the voltage.

Referring to Figure 5, the working principle of this example is as follows:

When the linear voltage regulator is not enabled, the linear voltage regulator does not work, the reference voltage V _REF is not established, its voltage value is zero, and the linear voltage regulator has no output current. The control signal ONX maintains a low level, the low-voltage PMOS transistor M1 is linearly turned on, the first low-voltage NMOS transistor M2 is turned off, and the drain voltage of the low-voltage PMOS transistor M1 is at a high level VDD, which makes the second low-voltage NMOS transistor M3 linearly turned on , maintaining the voltage value of the reference voltage V _REF as zero.

After the linear regulator is enabled, the control signal ONX turns from low level to high level, and the soft start circuit works, that is, the control signal ONX turns off the low-voltage PMOS transistor M1. At this time, the voltage value of the reference voltage V _REF is zero, and the first The low-voltage NMOS transistor M2 is turned off, so that the drain of the low-voltage PMOS transistor M1 is in an equivalent floating state. Due to the drain-substrate leakage current of the first low-voltage NMOS transistor M2, the voltage at the drain of the low-voltage PMOS transistor M1 decreases slowly. Ability gradually declines. The decline of the conduction capability of the transistor will gradually weaken the short-circuit function of the series branch of the second low-voltage NMOS transistor M3 and the low-voltage resistor R5. As the short-circuit effect of the series branch of the second low-voltage NMOS transistor M3 and the low-voltage resistor R5 weakens, the reference voltage V _REF rises slowly from zero, and finally reaches a preset value. The time for the reference V _REF to rise from zero to a preset value can be adjusted by changing the resistance of the low-voltage resistor R5. Changing the resistance value of the low-voltage resistor R1 means changing the equivalent impedance value of the series branch of the second low-voltage NMOS transistor M3 and the low-voltage resistor R5. The short-circuit effect of the road will affect the soft-start time. The reference voltage V _REF and the output feedback voltage V _FB slowly rising from zero are differentially amplified by the error operational amplifier EA, and the output voltage V _DR , which controls the power transistor M4 of the linear regulator to realize the output feedback voltage V _FB and the reference voltage V _REF changes synchronously. Since the output voltage V _OUT is divided by the feedback resistors R2 and R3 to obtain the output feedback voltage V _FB , the output feedback voltage V _FB changes synchronously with the reference voltage V _REF , ensuring that the output voltage V _OUT changes synchronously with the reference voltage V _REF . It can be seen that the establishment time of the reference voltage V _REF can be extended and adjusted through the soft start circuit of the present invention, so that the reference voltage V _REF can be established synchronously with the output voltage V _OUT of the linear regulator. It avoids the extreme minimum value of the output voltage V _DR of the operational amplifier EA caused by the excessive difference between the reference voltage V _REF and the feedback voltage V _FB , and realizes the function of suppressing the surge current.

When the voltage at the drain end of the low voltage PMOS transistor M1 drops below the turn-on threshold voltage of the second low voltage NMOS transistor M3, the second low voltage NMOS transistor M3 is completely turned off, and the soft start process ends. At this time, the low-voltage PMOS transistor M1 maintains an off state, the first low-voltage NMOS transistor M2 maintains a linear conduction state, and the second low-voltage NMOS transistor M3 maintains an off state. The second low-voltage NMOS transistor M3 is turned off, and it no longer affects the reference voltage V _REF , the soft-start function completely disappears, and no longer affects the output voltage and current of the linear regulator.

The above descriptions are only two specific examples of the present invention, and do not constitute any limitation to the present invention. Obviously, for those skilled in the art, after understanding the content and principles of the present invention, it is possible to make various modifications and changes in form and details without departing from the principles and structures of the present invention, but these are based on the present invention. The modification and change of the inventive concept are still within the protection scope of the claims of the present invention.

Claims (4)

1. be applied to a soft starting circuit for stabilized voltage supply chip, it is characterized in that comprising a PMOS pipe M1 and two NMOS pipes M2, M3;

Described PMOS pipe M1, its source electrode meets power vd D, and its grid meets external control signal ONX, and the drain electrode of a NMOS pipe M2 and the grid of the 2nd NMOS pipe M3 are received respectively in its drain electrode;

A described NMOS pipe M2, its source ground, its grid connects reference voltage V _rEF;

Described the 2nd NMOS pipe M3, its source ground, its drain electrode connects reference voltage V _rEF.

2. according to the soft starting circuit described in claim, it is characterized in that described PMOS pipe M1 and two NMOS pipes M2, M3, all adopt withstand voltage between source, drain electrode to be less than or equal to the low-voltage tube of 5V.

3. soft starting circuit according to claim 1, is characterized in that the 2nd NMOS manages drain electrode and the reference voltage V of M3 _rEFbetween be connected with regulating resistance R1, for regulating soft-start time and surge current value.

4. soft starting circuit according to claim 3, is characterized in that the parameter of regulating resistance R1 is selected according to the surge current value of soft-start time and permission.

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