CN103618553A - Improved complete-accurate triangle integral modulator - Google Patents
Improved complete-accurate triangle integral modulator Download PDFInfo
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- CN103618553A CN103618553A CN201310608871.7A CN201310608871A CN103618553A CN 103618553 A CN103618553 A CN 103618553A CN 201310608871 A CN201310608871 A CN 201310608871A CN 103618553 A CN103618553 A CN 103618553A
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Abstract
The invention relates to an improved complete-accurate triangle integral modulator, and provides a method and device for improving the complete-accuracy of an oversampling digital-analog converter. Specifically, an improved switched capacitor substractor/integrator circuit describes the operation that needed capacitance is effectively provided by using N+M capacitors with totally different units, and each capacitor samples one input signal at first preset times and samples one or more reference signals at second preset times, wherein the ideal capacitance ratio of the first preset times and the second preset times is N/M.
Description
Technical field:
The present invention relates to a hits weighted-voltage D/A converter.More particularly, the method and apparatus the present invention relates to is used for improving the complete accuracy of a hits weighted-voltage D/A converter triangular integration modulator.
Background technology:
Make a continuous analog signal be converted to a discrete digital signal, conventionally need to eliminate sawtooth filtering, sampling and quantification.A reverse sawtooth filter guarantees that the limited broadband of analog input signal is correctly sampled.A sampler is caught the sample of the input signal of filtration at discrete time interval, conventionally T=1/F
s, F wherein
sit is sample frequency.Sample frequency F
sconventionally elect the bandwidth of the analog input signal of second order filtration as.Finally, a digital quantizer is the discrete set of value by sample conversion.Traditional digital-to-analogue (A/D) transducer conventionally samples and quantizes, and independent discrete elements or integrated circuit are carried out elimination sawtooth.
Over-sampling A/D converter, by contrast, at ratio DF
sthe analog input signal of sampling, this ratio is the twice of analog input signal bandwidth.An over-sampled converter generally includes one and eliminates sawtooth filter, a sampler and a ratio DF who is operated in raising
son modulator (quantizer), an and digital filter.Digital filter, is commonly referred to a withdrawal device, provides low-pass filtering to suppress to surpass F
s/ 2 signal, sample frequency drops to required frequency F
s.
Due to higher input sampling rate, over-sampled converter has lower strict elimination sawtooth filter demand than traditional transducer.In addition, over-sampled converter allows lower quantization noise power, therefore than traditional transducer, has better signal to noise ratio.
A/D converter moves at the minimum and maximum input reference signal of an appointment conventionally.Maximum input signal is commonly called the comprehensive input value of transducer.Under desirable condition, if one is comprehensively inputted and is applied on transducer, transducer provides a comprehensively output.But in fact, the actual output of transducer is different from desired result, actual output is comprehensive error with the difference of desirable output.A comprehensively accurate transducer does not have mistake.
A comprehensively accurate over-sampled converter has significant practical significance in the field as data acquisition, test and sensing device instrument, Industry Control, because transducer provides direct current transformation result accurately, refuse unexpected undesirable signal and the requirement of simple elimination sawtooth.
A common realization with reference to 1, one trigonometric integral over-sampled converter of figure is described.Transducer 10 comprises subtraction circuit 12, integrator 14 and 18, output adder 20, comparator 22, clock generator 24 and digital filter 26.
Based on clock signal clk A and digital signal Y state, subtraction circuit 12 is from analog input signal V
inputdeduct analog V
ref.Integrator 14 in each cycle of clock signal clk B to synthetic differential signal integration and produce output signal IE1.Integrator 16 in each cycle of clock signal clk C to IE1 integration and produce output signal IE2.Integrator 18 in each cycle of clock signal clk D to IE2 integration and produce output signal IE3.Output adder 20 produces the algebraical sum of output signal IE1, IE2 and IE3, to create three rank comprehensively and feedforward compensation error signal IE.
Comparator 22 is compared with differential signal IE, has an internal reference (not showing), and produces digital output signal Y in each cycle of clock signal clk E.Numeral output Y only has two kinds of possible states, therefore can with binary form, represent by position.
The clock signal clk A that clock generator 24 produces from internal clock signal CLK, CLKB, CLKC, CLKD and CLKE are used suitable phase relation in the specific realization of modulator.
Digital stream Y comprises one at input signal V
inputwith reference signal V
refbetween the numeral of ratio R.Output Y can be extracted and further transform by digital processing in filter 26.The output D of digital filter 26 is transformation results.
As full-scale signal V
fsibe applied to transducer input V
inputtime, the full-scale output of transducer 10 equals the output D of transducer
fsi.Under desirable condition, the input signal V of full-scale
fsiand V
refratio be:
Generally, k is non-zero proportionality constant, and its value depends on the working range of transducer.
Due to the variation of component tolerances and operating condition, yet, V worked as
fsiwhile being applied to the input of transducer, the actual output of transducer is not equal to D
fsi.On the contrary, as input signal V
fsawhile being applied to the input of transducer, the actual output of transducer equals D
fsi.V
fsawith reference signal V
refratio to provide:
Error is defined as relatively comprehensively:
In the ideal case, R
fs=k, E
fs=0.
In prior art, with digital calibration, to make up comprehensive mistake little for over-sampling A/D converter, at an inner signal V that generates
fsiwhile being applied to transducer input, carry out a special-purpose comprehensive self calibration conversion.Ideally, transducer output is DD
fsi.Actual output D
fsawith required output D
fsicompare, a digital computer determines error E
fswith a suitable correction factor K
c.Subsequently, digital computer is by K
cbe applied on all transducer result D.Need complicated circuit to improve size, power consumption and the inner noise producing of transducer.Further, the change under environmental condition makes calculation correction COEFFICIENT K in the past
cinvalid, and need a new comprehensive calibration cycle.Because the digital calibration cycle is reduced the throughput of transducer, frequency digital calibration causes the equivalent transformation rate of a reduction.
Comprehensive accuracy that accurately depends primarily on input subtraction circuit 12 of transducer 10.In typical circuit is realized, subtraction circuit 12 sum-product intergrators 14 are combined in a single switched-capacitor circuit, and the accuracy of subtraction function depends on the ratio of two input sample electric capacity.Prior art circuit attempts to control with well-known topology that this is critical.Although these topologies have been eliminated the inferior position of digital calibration, circuit layout does not reach the precision of expection level.
Therefore it need to provide a trigonometric integral digital to analog converter, not need digital calibration to reduce comprehensive mistake.
It also need to provide a trigonometric integral digital to analog converter, not rely on crucial electric capacity and recently reduce comprehensive mistake.
Summary of the invention:
Therefore, an object of the present invention is to provide a trigonometric integral digital to analog converter, do not need digital calibration to reduce comprehensive mistake.
Another object of the present invention is to provide a trigonometric integral digital to analog converter, does not rely on crucial electric capacity and recently reduces comprehensive mistake.
Technical solution of the present invention:
The object of these and other according to the present invention, provides a subtracter/integrator circuit effectively, has sampling capacitance C
inand C
ref, their ratio can be expressed as a rational N/M, and wherein N is relative with M is prime number.Circuit, under the control of state motor, is used different units capacitor C
u1, C
u2... C
u (M+N)this ratio is provided.State motor makes each cell capacitance C
u1, C
u2... C
u (M+N)in the second pre-determined number one or more reference signal of sampling, effectively to build an equivalent reference capacitance C
ref.The ratio of the first pre-determined number and the second pre-determined number equals expectation and compares N/M.Therefore, effective capacitance C
inand C
refratio only depend on the state of state motor, almost infinitely controlled.
Contrast patent documentation: CN101247126A bandwidth tunable sigma-delta adc modulator 200710159866.7, CN101674088A be take low pass filter as basic triangular integration modulator 200910205383.5
Accompanying drawing explanation:
Above-mentioned purpose of the present invention and feature can the clearer understandings in conjunction with drawing below, and wherein identical reference number represents identical structural detail:
Fig. 1 is the theory diagram of the trigonometric integral digital to analog converter of a previously known;
Fig. 2 A is the theory diagram of the subtracter/integrator of a previously known, and Fig. 2 B is the chronogram of Fig. 2 A circuit;
Fig. 3 A is the illustrative block diagram of prior art integrated-circuit capacitor, and Fig. 3 B is the block diagram from two electric capacity in Fig. 3 A IC capacitor;
Fig. 4 is the schematic diagram of state machine of the present invention and subtracter/integrator;
Fig. 5 is the chronogram of Fig. 4 circuit;
Fig. 6 is state machine of the present invention and the adder/integrator schematic diagram embodying directly perceived;
Fig. 7 is the chronogram of Fig. 6 circuit.
Embodiment:
In order to be the invention provides background, first this written description has proposed the subtracter/integrator circuit of a previously known, and has described the circuit element that affects comprehensive error.Then, described these previously knowns subtracter/integrator circuit modification and alternative embodiment is disclosed.
A. prior art subtracter/integrator circuit
According to Fig. 2, the circuit of a previously known combines the function of Fig. 1 subtracter 12 sum-product intergrators 14.Circuit 30 comprises amplifier 32, and it has anti-phase input V
in, noninverting input V
ipwith output V
out.Integrated capacitance C
fbe coupling in V
inand V
outbetween.Capacitor C
refby switch S 1 and S2, be coupling in reference node-V
refand V
inbetween, and be coupling in bias node V by switch S 3 and S4
bias.Capacitor C
inby switch S 7 and S8, be coupling in input signal node V
refand V
inbetween, by switch S 5 and S6 and V
biascoupling.Switch S 1 is by clock signal Φ
1control.Switch S 4, S6 and S7 are by clock signal Φ
2control, switch S 2, S3, S5 and S8 are by clock signal Φ
3 control.State motor 34 receives as input CLKA and the Y of Fig. 1, and clocking Φ
1, Φ
2and Φ
3.Fig. 2 B has shown CLKA, Y, Φ
1, Φ
2and Φ
3between time relationship.Y only changes in CLKA rising edge.
For circuit 30, precision depends primarily on C comprehensively
refand C
inratio accuracy.Particularly, when clock signal Phi
4and Φ
2while being all high, one and reference signal-V
ref(Q
ref=-C
ref* V
ref) proportional charge Q
refbe stored in capacitor C
refupper, one and input signal-V
input(Q
in=C
in* V
input) proportional charge Q
inbe stored in capacitor C
inon.Φ
3next pulse (for example, work as Φ
2step-down, Φ
3high) time, charge Q
inand Q
refbe transferred to integrated capacitance C
fon.Amplifier 32 promotes electric charge to shift.Be used for promoting that the whole bag of tricks of amplifier 32 is commonly known.A complete cycle of state machine 34 is defined as a complete cycle of CLKA, comprising clock Φ
2and Φ
3a complete cycle.Last at a complete cycle of CLKA, when Y is while being high, total electrical charge Q
tot(height) transfers to integrated capacitance C
fupper, and be stored in C
refand C
inelectric charge summation equate, in the cycle: Q
tot(height)=C
in* V
input-C
ref* V
ref(4) last at a complete cycle of CLKA, when Y is while being low, total electrical charge Q
tot(low) transfers to integrated capacitance C
fupper, and be stored in C
ref(without electric charge) and C
inon total electrical charge equate, in the cycle: Q
tot(low)=C
in* V
input(5) Q
tot(low) and Q
totthe ratio of (height) depends on C
inand C
refratio and V
inputwith reference signal V
refrelative voltage ratio.Therefore, comprehensive accuracy of modulator depends on C
inand C
refratio.
In integrated circuit technique, capacitance and electric capacity top board and baseplate zone are in direct ratio, the thickness of medium between inverse ratio and two plates.Suppose that the dielectric thickness of electric capacity is consistent in integrated circuit, the ratio of two electric capacity only depends on their Area Ratio.Therefore, prior art integrated circuit technique seeks to improve C by controlling the accuracy of two capacity area ratios conventionally
inand C
refthe accuracy of ratio.
In order to improve the accuracy of Area Ratio, the common You“ unit of IC capacitor " capacitance group composition, they are connected so that specific capacitance to be provided.Fig. 3 has shown and has been used for building capacitor C
inand C
refa typical precedent of prior art, its ratio is 1:2.Fig. 3 A has shown specific capacitance 40, and it has top board 42, and base plate 44, by connecting 50 conductors 46 that are connected to base plate 44, by connecting 52 conductors 48 that are connected to top board 42.
Fig. 3 B has shown the capacitor C that forms specific capacitance 40
inand C
ref.Particularly, C
refby C
intwo specific capacitances form, and comprise the top board 66 that adds conductor 60, and base plate 62.By a single specific capacitance device, built, and formed by top board 68 and base plate 64.Artistic layout technology has although it is so improved ratio precision, and technology itself does not allow low-down comprehensive error in over-sampling trigonometric integral digital to analog converter.
B. subtracter/integrator of inventing
According to principle of the present invention, for over-sampling trigonometric integral digital to analog converter provides a subtracter/integrator circuit, it is the input sample capacitor C of rational N/M that ratio is effectively provided
inand C
ref, wherein N is relative with M is prime number.Circuit, under the control of state motor, is used N+M different units capacitor C
u1, C
u2... C
u(M+N) provide this ratio.
Particularly, how state machine controls each different cell capaciator C
u1, C
u2... C
u(M+N) be used to sampled signal V
inputand V
ref.Within one of new state machine complete cycle (for example, in Fig. 1, CLKA one-period), each specific capacitance C
u1, C
u2... C
u(M+N) at the first pre-determined number sampling V
input, effectively to build an equivalent input capacitance C
in.Equally, in a complete cycle of a new state machine, depend on that Y is low or high, each specific capacitance C
u1, C
u2... C
u(M+N) at second scheduled time sampling-V
ref(or+V
ref), effectively to build an equivalent reference capacitance C
ref.
The first pre-determined number equals C (M+N-1, N-1), and wherein C (i, j) is famous binomial coefficient: C
(6) second pre-determined numbers equal C (M+N1, M-1).
State machine cycle is corresponding to the one-period of CLKA (Fig. 1).Yet state machine is at frequency CLKA operation C(M+N, N) inferior.The result in state machine cycle equals input capacitance C
in=N*C (M+N, N) * C
unitan and equivalent reference capacitance C
ref=M*C (M+N, N) * C
unit, C wherein
unitit is specific capacitance value.Each specific capacitance C
u1, C
u2... C
u(M+N) be used to build equivalent C
incapacitor C
(M+N-1, N-1)number of times and equivalent C
refcapacitor C (M+N-1, N-1) number of times.Therefore, equivalent capacity C
inand C
refratio be N/M, be independent of the different specific capacitance C of M+N
u1, C
u2... C
u(M+N) actual value.
According to Fig. 4, the imbody of a subtracter/integrator of the present invention has been described N=1 and M=2.Subtracter/integrator circuit 70 comprises amplifier 72, and it has anti-phase input V
in, noninverting input V
ipwith output V
out.Integrated capacitance C
fbe coupling in V
inand V
outbetween.C from Fig. 2 A
refand C
inbe divided into three capacitor C
u1, C
u2and C
u3.Capacitor C
u1by switch S, 11-S13 is coupling in reference node-V
refand V
inputand V
inbetween, by switch S 20 and S21, be coupling in bias node V
biason.Capacitor C
u2by switch S, 14-S16 is coupling in reference node-V
refand V
inputand V
inbetween, by switch S 22 and S23, be coupling in bias node V
bias.Capacitor C U3 is coupling in reference node V by switch S 17-S19
refand V
inputand V
inbetween, and be coupling in bias node V by switch S 24 and S25
biason.
Switch S 11, S13, S14, S16, S17 and S19 are by clock signal Φ
3a, Φ
3b, Φ
3cand Φ
3dcontrol respectively.Switch S 12, S15, S18, S20, S22 and S24 are by clock signal Φ
4acontrol, switch S 21, S23 and S25 are by clock control signal Φ
5a control.State machine 74 receives signal CLKA ' and Y, and clocking Φ
3a, Φ
3b, Φ
3c, Φ
3d, Φ
3e, Φ
3f, Φ
4aand Φ
5a.Fig. 5 has shown CLKA, Y, CLKA ', Φ
3a, Φ
3b, Φ
3c, Φ
3d, Φ
3e, Φ
3f, Φ
4aand Φ
5abetween relation.Y only changes in CLKA rising edge.
The frequency of clock signal clk A ' is three times of (for example, C of CLKA frequency
(M+N, N)).Therefore, three of CLKA ' cycles occur in the single cycle of CLKA.If Y is high at the one-period of CLKA, 70 operations of subtracter/integrator are as follows.In the period 1 of CLKA ', when clock signal Phi
3a, Φ
3b, Φ
3fand Φ
5aall high, with reference signal-V
ref(Q
1=-C
u1* V
ref) proportional charge Q
1be stored in capacitor C
u1in, with reference signal-V
ref(Q
2=-C
u2* V
ref) proportional charge Q
2be stored in capacitor C
u2in, with input signal V
input(Q
3=C
u3* V
input) proportional charge Q
3be stored in capacitor C
u3in.At Φ
4anext pulse (for example, work as Φ
5astep-down and Φ
4auprise), charge Q
1, Q
2and Q
3be transferred to integrated capacitance C
fon.
In the second round of CLKA ', when clock signal Phi
3b, Φ
3c, Φ
3d, and Φ
5awhile being high, with input signal V
input(Q
1=-C
u1* V
input) proportional charge Q
1be stored in capacitor C
u1in, with reference signal-V
ref(Q
2=-C
u2* V
tef) proportional charge Q
2be stored in capacitor C
u2in, with reference signal-V
ref(Q
3=-C
u3* V
ref) proportional charge Q
3be stored in capacitor C
u3in.At Φ
4anext pulse (for example, work as Φ
5astep-down and Φ
4auprise), charge Q
1q
2q
3be transferred to integrated capacitance C
fon.
In the period 3 of CLKA ', when clock signal Phi
3a, Φ
3c, Φ
3eand Φ
5awhile being high, with reference signal-V
ref(Q
1=-C
u1* V
ref) proportional charge Q
1be stored in capacitor C
u1in, with input signal V
input(Q
2=C
u2* V
input) proportional charge Q
2be stored in capacitor C
u2in, with reference signal-V
ref(Q
3=-C
u3* V
ref) proportional electric charge Φ
3be stored in capacitor C
u3in.At Φ
4anext pulse (for example, work as Φ
5astep-down and Φ
4auprise), charge Q
1q
2q
3be transferred to integrated capacitance C
fon.
Therefore, when Y is one of CLKA complete cycle while being high, total electrical charge Q
tot(height) transfers to integrated capacitance C
f, its be stored in C
u1, C
u2and C
u3electric charge sum equate, in the cycle: Q
tot(height)=(C
u1+ C
u2+ C
u3) * V
input-2 (C
u1+ C
u2+ C
u3) * V
ref(7)
If C
u1+ C
u2+ C
u3=C
x, formula (7) can be write as: Q
tot(height)=C
x* V
input-2*C
x* V
ref(8) formula (8) and formula (4) are identical equation, wherein C
x=C
inand C
ref=2*C
in.
If Y is low at the one-period of CLKA, 70 operations of subtracter/integrator are as follows.In the period 1 of CLKA ', when clock signal Phi
3a, Φ
5aall high, with input signal V
input(Q
3=C
u3* V
input) proportional charge Q
3be stored in capacitor C
u3in.At Φ
4anext pulse (for example, work as Φ
5astep-down and Φ
4auprise), charge Q
3transfer to integrated capacitance C
fon.
In the second round of CLKA ', when clock signal Phi
3a, Φ
5aall high, with input signal V
input(Q
1=C
u1* V
input) proportional charge Q
1be stored in capacitor C
u1in.At Φ
4anext pulse (for example, work as Φ
5astep-down and Φ
4auprise), charge Q
1transfer to integrated capacitance C
fon.
In the period 3 of CLKA ', when clock signal Phi
3e, Φ
5aall high, with input signal V
input(Q
2-C
u2* V
input) proportional charge Q
2be stored in capacitor C
u2in.At Φ
4anext pulse (for example, work as Φ
5astep-down and Φ
4auprise), charge Q
2transfer to integrated capacitance C
fon.
Therefore, when Y is one of CLKA complete cycle while being low, total electrical charge Q
tot(low) transfers to integrated capacitance C
f, its be stored in C
u1, C
u2and C
u3electric charge sum equate, in the cycle: Q
tot(low)=(C
u1+ C
u2+ C
u3) * V
input(9) if C
u1+ C
u2+ C
u3c
x, formula (9) can be write as: Q
tot(low)=C
x* V
input(10) formula (10) and formula (5) are identical equation, wherein C
x=C
in.
Therefore, at last complete cycle of CLKA, each specific capacitance C
u1, C
u2and C
u3be used once (for example, the first pre-determined number C (M+N-1, N-1)), built equivalent input capacitance C
in, they are used (when Y is while being high) (for example, the first pre-determined number C (M+N-1, M-1)) twice, build equivalent reference capacitance C
ref.Therefore, equivalent capacity C
inand C
refbetween ratio be 1:2, be independent of specific capacitance C
u1, C
u2and C
u3actual value.
According to Fig. 6, the imbody of a subtracter/integrator of the present invention has been described N=1 and M=2, input signal V
inputthere are positive and negative two polarity.Subtracter/integrator circuit 80 comprises amplifier 82, and it has anti-phase input V
in, noninverting input V
ipwith output V
out.Integrated capacitance C
fbe coupling in V
inand V
outbetween.C from Fig. 2 A
refand C
inbe divided into three capacitor C
u1, C
u2and C
u3.Capacitor C
u1by switch S 11-S13 coupling 44, be coupling in bias node V
biason.Capacitor C
u2by switch S, 35-S38 is coupling in reference node+V
refwith-V
refand V
inputand V
inbetween, by switch S 45 and S46, be coupling in bias node V
bias.Capacitor C
u3by switch S, 39-S42 is coupling in reference node+V
ref,-V
refand V
inputand V
inbetween, and be coupling in bias node V by switch S 47 and S48
biason.
Switch S 31, S32, S33, S35, S36, S37, S39, S40 and S41 are by clock signal Φ
3ah, Φ
3a1, Φ
3d, Φ
3bh, Φ
3b1, Φ
3e, Φ
3ch, Φ
3c1and Φ
3fcontrol respectively.Switch S 34, S38, S42, S43, S45 and S47 are by clock signal Φ
4acontrol, switch S 44, S46 and S48 are by clock control signal Φ
5a control.State machine 84 receives signal CLKA ' and Y, and clocking Φ
3ah, Φ
3a1, Φ
3bh, Φ
3b1, Φ
3ch, Φ
3c1, Φ
3d, Φ
3e, Φ
3f, Φ
4aand Φ
5a.Fig. 7 has shown CLKA, Φ
3ah, Φ
3a1, Φ
3bh, Φ
3b1, Φ
3ch, Φ
3c1, Φ
3d, Φ
3e, Φ
3f, Φ
4aand Φ
5abetween relation.Y only changes in CLKA rising edge.
If Y is high at the one-period of CLKA, 80 operations of subtracter/integrator are as follows.In the period 1 of CLKA ', when clock signal Phi
3ah, Φ
3bh, Φ
3fand Φ
5aall high, with reference signal-V
ref(Q
1=-C
u1* V
ref) proportional charge Q
1be stored in capacitor C
u1in, with reference signal-V
ref(Q
2=-C
u2* V
ref) proportional charge Q
2be stored in capacitor C
u2in, with input signal V
input(Q
3=C
u3* V
input) proportional charge Q
3be stored in capacitor C
u3in.At Φ
4anext pulse (for example, work as Φ
5astep-down and Φ
4auprise), electric Q
1, Q
2and Q
3be transferred to integrated capacitance C
fon.
In the second round of CLKA ', when clock signal Phi
3bh, Φ
3ch, Φ
3dand Φ
5awhile being high, with input signal V
input(Q
1=-C
u1* V
input) proportional charge Q
1be stored in capacitor C
u1in, with reference signal-C
ref(Q
2=-C
u2* V
ref) proportional charge Q
2be stored in capacitor C
u2in, with reference signal-V
ref(Q
3=-C
u3* V
ref) proportional charge Q
3be stored in capacitor C
u3in.At Φ
4anext pulse (for example, work as Φ
5astep-down and Φ
4auprise), charge Q
1, Q
2and Q
3be transferred to integrated capacitance C
fon.
In the period 3 of CLKA ', when clock signal Phi
3ah, Φ
3ch, Φ
3eand Φ
5awhile being high, with reference signal-V
ref(Q
1=-C
u1* V
ref) proportional charge Q
1be stored in capacitor C
u1in, with input signal V
input(Q
2=C
u2* V
input) proportional charge Q
2be stored in capacitor C
u2in, with reference signal-V
ref(Q
3=-C
u3* V
ref) proportional charge Q
3be stored in capacitor C
u3in.At Φ
4anext pulse (for example, work as Φ
5astep-down and Φ
4auprise), charge Q
1, Q
2and Q
3be transferred to integrated capacitance C
fon.
Therefore, when Y is one of CLKA complete cycle while being high, total electrical charge Q
tot(height) transfers to integrated capacitance C
f, its be stored in C
u1, C
u2and C
u3electric charge sum equate, in the cycle: Q
tot(height)=(C
u1+ C
u2+ C
u3) * V
input-2 (C
u1+ C
u2+ C
u3) * V
ref(11), if Y is low at the one-period of CLKA, 80 operations of subtracter/integrator are as follows.In the period 1 of CLKA ', when clock signal Phi
3a1, Φ
3b1, Φ
3fand Φ
5aall high, with reference signal+V
ref(Q
1=+C
u1* V
ref) proportional charge Q
1be stored in capacitor C
u1in, with reference signal+V
ref(Q
2=+C
u2* V
ref) proportional charge Q
2be stored in capacitor C
u2in, with input signal V
input(Q
3=C
u3* V
input) proportional charge Q
3be stored in capacitor C
u3in.At Φ
4anext pulse (for example, work as Φ
5astep-down and Φ
4auprise), charge Q
1, Q
2and Q
3be transferred to integrated capacitance C
fon.
In the second round of CLKA ', when clock signal Phi
3bh, Φ
3ch, Φ
3dand Φ
5awhile being high, with input signal V
input(Q
1=C
u1* V
input) proportional charge Q
1be stored in capacitor C
u1in, with reference signal+V
ref(Q
2=+C
u2* V
ref) proportional charge Q
2be stored in capacitor C
u2in, with reference signal+V
ref(Q
3=+C
u3* V
ref) proportional charge Q
3be stored in capacitor C
u3in.At Φ
4anext pulse (for example, work as Φ
5astep-down and Φ
4auprise), charge Q
1, Q
2and Q
3be transferred to integrated capacitance C
fon.
In the period 3 of CLKA ', when clock signal Phi
3a1, Φ
3c, Φ
3eand Φ
5awhile being high, with reference signal+V
ref(Q
1=+C
u1* V
ref) proportional charge Q
1be stored in capacitor C
u1in, with input signal V
input(Q
2=C
u2* V
input) proportional charge Q
2be stored in capacitor C
u2in, with reference signal+V
ref(Q
3=+C
u3* V
ref) proportional charge Q
3be stored in capacitor C
u3in.At Φ
4anext pulse (for example, work as Φ
5astep-down and Φ
4auprise), charge Q
1q
2and Q
3be transferred to integrated capacitance C
fon.
Therefore, when Y is one of CLKA complete cycle while being high, total electrical charge Q
tot(height) transfers to integrated capacitance C
f, its be stored in C
u1, C
u2and C
u3electric charge sum equate, in the cycle: Q
tot(low)=(C
u1+ C
u2+ C
u3) * V
input+ 2 (C
u1+ C
u2+ C
u3) * V
ref(12) if C
u1+ C
u2+ C
u3=C
x, formula (11) and (12) can be write as: Q
tot(height)=C
x* V
input-2*C
xv
ref(13) Q
tot(low)=C
x* V
input-2*C
xv
ref(14) therefore, in last complete cycle of CLKA, when Y is while being high or low, each specific capacitance C
u1, C
u2and C
u3be used once (for example, the first pre-determined number C (M+N-1, N-1)), built equivalent input capacitance C
in, they are used (when Y is while being high) (for example, the first pre-determined number C (M+N-1, M-1)) twice, build equivalent reference capacitance C
ref.Therefore, equivalent capacity C
inand C
refbetween ratio be 1:2, be independent of specific capacitance C
u1, C
u2and C
u3actual value.
People's masterful technique will recognize that, circuit of the present invention will be realized except the Circnit Layout of above description and displaying by using.For example, Fig. 4 and 6 is fully differential circuit.Modification in the scope of the invention is only limited by the claims.
Claims (9)
1. the completely accurate triangular integration modulator through improvement, it is characterized in that: a subtracter/integrator circuit produces an output signal at output node, itself and input signal and a reference signal sum that is multiplied by predetermined scale factor N/M are proportional, subtracter/integrator circuit comprises the input signal node that an input signal is employed, a reference signal node that reference signal is employed, a deviation signal node that deviation signal is employed, an output circuit that is coupling in deviation signal node, this output circuit has the output being coupled with output node, N+M switched-capacitor circuit and input signal node, reference signal node, deviation signal node and output circuit coupling, control circuit and the coupling of N+M switched-capacitor circuit, control circuit causes that each N+M switched-capacitor circuit is at the first pre-determined number sampling input signal and in the second pre-determined number sampling reference signal, wherein the first pre-determined number and the second pre-determined number equal scale factor N/M.
2. a kind of completely accurate triangular integration modulator through improvement according to claim 1, it is characterized in that: wherein N+M switched-capacitor circuit each there is an electric capacity, wherein each electric capacity comprises a top board and a base plate, output circuit comprises an amplifier, the anti-phase input node of amplifier and the coupling of N+M switched-capacitor circuit, noninverting input node and the coupling of deviation signal node, output signal node and output node coupling, subtracter/integrator circuit also comprises a feedback capacity being coupling between anti-phase input node and output node.
3. a kind of completely accurate triangular integration modulator through improvement according to claim 2, it is characterized in that: wherein N+M switched-capacitor circuit each also comprise the first and second inputs, the first and second outputs, the first input and the coupling of reference signal node, the second input and the coupling of input signal node, the first output and the coupling of anti-phase input node, the second output and noninverting input node coupling, be coupling in the first switch between reference signal node and electric capacity top board, be coupling in the second switch between capacitor bottom plate and anti-phase input node, be coupling in the 3rd switch between input signal node and electric capacity top board, be coupling in the 4th switch between electric capacity top board and noninverting input node, be coupling in the 5th switch between capacitor bottom plate and noninverting input node.
4. a kind of completely accurate triangular integration modulator through improvement according to claim 3, it is characterized in that: control circuit produces a plurality of control signals in a plurality of output, each also comprises N+M switched-capacitor circuit and first of a plurality of control signal couplings, second, the third and fourth control inputs, a plurality of control signals cause that each N+M switched-capacitor circuit is at the first pre-determined number sampling input signal and in the second pre-determined number sampling reference signal, wherein N+M switched-capacitor circuit each also comprise the first switch being coupling between reference signal node and electric capacity top board, the first switch comprises a switch control inputs being coupled with the first control inputs, be coupling in the second switch between capacitor bottom plate and anti-phase input node, second switch comprises a switch control inputs being coupled with the second control inputs, be coupling in the 3rd switch between electric capacity top board and input signal node, the 3rd switch comprises a switch control inputs being coupled with the 3rd control inputs, be coupling in the 4th switch between electric capacity top board and noninverting input node, the 4th switch comprises a switch control inputs being coupled with the second control inputs, be coupling in the 5th switch between capacitor bottom plate and noninverting input node, the 5th switch comprises a switch control inputs being coupled with the 4th control inputs.
5. a kind of completely accurate triangular integration modulator through improvement according to claim 4, it is characterized in that: N=1 and M=2, N+M=3 switched-capacitor circuit comprises first, the second and the 3rd switched-capacitor circuit, first, each second control inputs of the second and the 3rd switched-capacitor circuit is coupled, their the 4th control inputs is also coupled, a subtracter/integrator circuit produces an output signal at output node, itself and input signal and a first or second reference signal sum that is multiplied by predetermined scale factor N/M are proportional, subtracter/integrator circuit comprises: an input signal node that input signal is employed, the first reference signal node that the first reference signal is employed, the second reference signal node that the second reference signal is employed, a deviation signal node that deviation signal is employed, an output circuit that is coupling in deviation signal node, this output circuit has the output being coupled with output node, N+M switched-capacitor circuit and input signal node, the first reference signal node, the second reference signal node, deviation signal node and output circuit coupling, control circuit and the coupling of N+M switched-capacitor circuit, control circuit causes that each N+M switched-capacitor circuit is at the first pre-determined number sampling input signal and in second pre-determined number sampling the first or second reference signal, wherein the first pre-determined number and the second pre-determined number equal scale factor N/M.
6. a kind of completely accurate triangular integration modulator through improvement according to claim 5, it is characterized in that: each comprises an electric capacity N+M switched-capacitor circuit, each electric capacity comprises a top board and a base plate, output circuit comprises an amplifier, the anti-phase input node of amplifier and the coupling of N+M switched-capacitor circuit, noninverting input node and the coupling of deviation signal node, output signal node and output node coupling, subtracter/integrator circuit also comprises a feedback capacity being coupling between anti-phase input node and output node, each also comprises first N+M switched-capacitor circuit, the second and the 3rd input, the first and second outputs, the first input and the first reference signal node coupling, the second input and the second reference signal node coupling, the 3rd input and the coupling of input signal node, the first output and the coupling of anti-phase input node, the second output and noninverting input node coupling, wherein N+M switched-capacitor circuit each also comprise the first switch being coupling between the first reference signal node and electric capacity top board, be coupling in the second switch between capacitor bottom plate and anti-phase input node, be coupling in the 3rd switch between the second reference signal node and electric capacity top board, be coupling in the 4th switch between electric capacity top board and noninverting input node, be coupling in the 5th switch between capacitor bottom plate and noninverting input node, be coupling in the 6th switch between input signal node and electric capacity top board.
7. a kind of completely accurate triangular integration modulator through improvement according to claim 6, it is characterized in that: control circuit produces a plurality of control signals in a plurality of output, each also comprises N+M switched-capacitor circuit and first of a plurality of control signal couplings, second, the 3rd, the the 4th and the 5th control inputs, a plurality of control signals cause that each N+M switched-capacitor circuit is at the first pre-determined number sampling input signal and in second pre-determined number sampling the first or second reference signal, wherein N+M switched-capacitor circuit each also comprise: be coupling in the first switch between the first reference signal node and electric capacity top board, the first switch comprises a switch control inputs being coupled with the first control inputs, be coupling in the second switch between capacitor bottom plate and anti-phase input node, second switch comprises a switch control inputs being coupled with the second control inputs, be coupling in the 3rd switch between the second reference signal node and electric capacity top board, the 3rd switch comprises a switch control inputs being coupled with the 3rd control inputs, be coupling in the 4th switch between electric capacity top board and noninverting input node, the 4th switch comprises a switch control inputs being coupled with the second control inputs, be coupling in the 5th switch between capacitor bottom plate and noninverting input node, the 5th switch comprises a switch control inputs being coupled with the 4th control inputs, be coupling in the 6th switch between input signal node and electric capacity top board, the 6th switch comprises a switch control inputs being coupled with the 5th control inputs.
8. a kind of completely accurate triangular integration modulator through improvement according to claim 7, it is characterized in that: N=1 and M=2, N+M=3 switched-capacitor circuit comprises first, second, and third switched-capacitor circuit, each second control inputs of first, second, and third switched-capacitor circuit is coupled, and their the 4th control inputs is also coupled.
9. a kind of completely accurate triangular integration modulator through improvement according to claim 8, it is characterized in that: be used for producing and be multiplied by the input signal of predetermined scale factor N/M to one and the method for a proportional output signal of reference signal sum comprises: store one at the first pre-determined number and proportional the first electric charge of N+M electric capacity input signal, store one at the second pre-determined number and proportional the second electric charge of each N+M electric capacity reference signal, wherein the first pre-determined number and the second pre-determined number equal scale factor N/M, the first and second electric charges are transferred in an integrated capacitance, wherein the voltage by integrated capacitance comprises output signal, be used for producing and be multiplied by the input signal of predetermined scale factor N/M to one and the method for the proportional output signal of the first or second reference signal sum comprises: store one at the first pre-determined number and proportional the first electric charge of N+M electric capacity input signal, store one at the second pre-determined number and each N+M electric capacity first or proportional the second electric charge of the second reference signal, wherein the first pre-determined number and the second pre-determined number equal scale factor N/M, the first and second electric charges are transferred in an integrated capacitance, wherein the voltage by integrated capacitance comprises output signal.
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| CN201310608871.7A CN103618553A (en) | 2013-11-26 | 2013-11-26 | Improved complete-accurate triangle integral modulator |
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| CN201310608871.7A CN103618553A (en) | 2013-11-26 | 2013-11-26 | Improved complete-accurate triangle integral modulator |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105024681A (en) * | 2015-06-25 | 2015-11-04 | 深圳市芯海科技有限公司 | Touch detection circuit capable of adjusting sensitivity and range |
| CN113162623A (en) * | 2021-04-21 | 2021-07-23 | 北京大学 | Conversion circuit and digital-to-analog converter based on resistance voltage division and capacitance integration |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0981205A2 (en) * | 1998-08-17 | 2000-02-23 | Linear Technology Corporation | Delta-sigma modulator with improved full-scale accuracy |
-
2013
- 2013-11-26 CN CN201310608871.7A patent/CN103618553A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0981205A2 (en) * | 1998-08-17 | 2000-02-23 | Linear Technology Corporation | Delta-sigma modulator with improved full-scale accuracy |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105024681A (en) * | 2015-06-25 | 2015-11-04 | 深圳市芯海科技有限公司 | Touch detection circuit capable of adjusting sensitivity and range |
| CN113162623A (en) * | 2021-04-21 | 2021-07-23 | 北京大学 | Conversion circuit and digital-to-analog converter based on resistance voltage division and capacitance integration |
| CN113162623B (en) * | 2021-04-21 | 2023-10-20 | 北京大学 | Conversion circuit and digital-to-analog converter based on resistor voltage division and capacitor integration |
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