CN103618541A - Input/output buffering device with configurable interfaces and power source - Google Patents
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Abstract
The invention discloses an input/output buffering device with configurable interfaces and a power source. The input/output buffering device comprises a bi-directional node, an output stage, an input stage and a control circuit. The output stage is provided with a first N channel transistor, and the first N channel transistor is coupled between the bi-directional node and a power source node to pull the bi-directional node upwards; the output stage is also provided with a first P channel transistor and a second P channel transistor, and the first P channel transistor and the second P channel transistor are coupled between the bi-directional node and the power source node to pull the bi-directional node upwards. The input stage is provided with a first inverter pole, and the first inverter pole is coupled between the bi-directional node and a first intermediate node; the input stage is also provided with a second inverter pole, and the second inverter pole is coupled between the bi-directional node and a second intermediate node.
Description
Technical field:
The present invention relates to I/O (I/O) buffer, more specifically, relate to the configurable input/output (i/o) buffer of power supply and interface.
Background technology:
Input and/or output buffer are generally used for connecting the external equipment of integrated circuit (IC) chip internal and chip.Particularly, an output buffer, for transmitting the inner signal producing to the packaging pin of described IC chip, makes this signal can be transferred to an external equipment.Input buffer is used for the signal that transmit outer equipment produces, and is received by the IC chip package pin using in inside.Identical node is used in the input and output of buffer, and a mono-packaging pin of IC is for example commonly referred to as an I/O (I/O) buffer (or briefly, an I/O).
An application of I/O is for connecting external memory storage and dram controller.In this application, the technology that is combined with high speed, low overshoot/undershoot, stationary noise tolerance limit is the design specification of target.Generally, with respect to the output of an I/O, in the totem output design of a standard, the shortcoming that can cause overshoot and undershoot to increase with the increase of the transmission rate at high to Low edge from low to high.In the I/O design with two different power level, for example supply voltage is 5V and 3.3V, and supply voltage is reduced to 3.3V from 5V can produce other bad phenomenon.Particularly, the TTL(transistor-transistor logic of input buffer) trigger point, the reduction due to supply voltage in the input structure of standard is drifted about downwards, and the transmission speed of output buffer is degenerated.
Therefore, the characteristic that makes an I/O framework have high speed, low overshoot/undershoot and a stable minimized noise margin is necessary, and will overcome above-mentioned shortcoming.
Summary of the invention:
The invention provides a buffer circuits, this circuit comprises an output node, be coupling in an above N channel transistor that draws output node between output node and power junctions, be coupling between output node and power junctions above draw the first p channel transistor of output node and be coupling in output node and power junctions between above the second p channel transistor that draws output node.When there is first power supply in power junctions, the first and second described p channel transistors of control circuit forbidding, and enable a N channel transistor.When power junctions exists a second source, control circuit enables the first and second p channel transistors.
The present invention also provides a buffer circuit, and this circuit comprises a primary input node and the first and second intermediate nodes.The input node of the first inverter stage is coupled to primary input node, and output node is coupled to the first intermediate node.The one N channel transistor is coupling between the first intermediate node and grounding node.The input node of the second inverter stage is coupled to primary input node, and output node is coupled to the second intermediate node.The 2nd N channel transistor is coupling between the second intermediate node and grounding node.Control circuit is coupled to described the first and second inverter stage and the first and second N channel transistors.Described control circuit enables the second inverter stage under first mode, and turn-offs the 2nd N channel transistor; Under the second pattern, enable the first inverter stage, and turn-off a N channel transistor.
Technical solution of the present invention:
For understanding better the features and advantages of the present invention, can, with reference to the detailed description and the accompanying drawings below, wherein illustrate an illustrative example utilizing the principle of the invention.
Contrast patent documentation: CN202872354U current buffer 201220577655.1
Accompanying drawing explanation:
Fig. 1 is a block diagram that an I/O buffer of principle according to the present invention is shown.
Fig. 2 is an operation truth table that I/O buffer is as shown in Figure 1 shown.
Fig. 3 is a principle schematic that the output buffer of Fig. 1 is shown.
Fig. 4 is a principle schematic that the input buffer of Fig. 1 is shown.
Embodiment:
With reference to Fig. 1, it shows an I/O buffer 20 of the principle according to the present invention.I/O buffer 20 is integrated in IC chip 22 inside, and uses DIN/OUT pin that the input and output of data are provided.I/O buffer 20 comprises an output buffer 24 and an input buffer 26.Yet, should be understood that, can use output buffer 24 and input buffer 26, to form two-way I/O buffer 20; Or use respectively output buffer 24 and input buffer 26, to form unidirectional output and input buffer.
In order to overcome above-mentioned shortcoming, the drive characteristic of the output buffer 24 in I/O buffer 20 is configurable.In addition, the size of the device in input buffer 26 (for example, transistor) is also configurable, for adjusting the variation of the working power voltage in AC-battery power source design.
With reference to Fig. 2, I/O buffer 20 is configured to output mode, by enable signal EN is set, is " 1 " (that is, logic high); Input pattern is " 0 " (that is, logic low) by enable signal EN is set.Under input pattern, open input buffer 26, and forbid output buffer 24.Data are received by the pin DIN/OUT on IC chip 22.Pin DIN/OUT is coupled to the input DIN of input buffer 26.Input buffer 26 sends to data by pin DIN2 the remainder of IC chip 22.Under output mode, enable output buffer 24, and input buffer 26 keeps enabling, but on the impact of operation nothing.Particularly, the transfer of data being produced by the inside of IC chip 22 is to DOUT1.Output buffer 24 sends to data by DOUT2 the DIN/OUT of packaging pin.Meanwhile, the data on DOUT2 also will send to DIN2 by input buffer 26, but on not impact of operation, this is because use pin DIN/OUT as output at IC chip 22.
I/O buffer 20 can be configured to be operated in 5V Transistor-Transistor Logic level, and it is " 0 " (that is, logic low) by THREE signal is set, and DRVCON signal completes for " 0 ".When being operated in Transistor-Transistor Logic level, output buffer 24 will draw DOUT2 on not understanding be high level.I/O buffer 20 can be configured to be operated in 5V CMOS level, by THREE signal is set, is " 0 " (that is, logic low), and DRVCON signal is that " 1 " (that is, logic is high) completes simultaneously.When being operated in CMOS level, on output buffer 24, drawing DOUT2 is high level.I/O buffer 20 can be configured to be operated in 3.3V CMOS level, by THREE signal is set, for " 1 ", completes.When being operated in 3.3 volts, DRVCON signal is on operating without any impact.This mode of operation also can be for 3.3V TTL.
With reference to Fig. 3, it shows the detailed schematic diagram of output buffer 24.N channel pull-up transistor M1 of output buffer 24 use is operated in the TTL5V level of standard.Transistor M1 is by a Voltagre regulator 28(or slew rate control circuit 28) control, and pressurizer and control circuit full conducting in delay chain.For the state that is operated in 3.3V, two p channel transistor M2 and M3 are same uses the mode of drawing.First transistor M2 conducting, then after the delays that produced by inverter 30,32 and 34, transistor M3 conducting.Transistor M2 and M3 also can be used in the operating state of 5V, to meet CMOS level.But the method (that is, using the M1 that pulls up transistor) that obtains 5VTTL has advantage aspect speed and restriction overshoot and power supply saltus step.
For the mode of operation of 3.3V and 5V, can use identical pulldown method.Particularly, a N channel transistor M4 opens immediately, thereby then another N channel transistor M5 is by feedback conducting.Should be understood that, yet, there are many different pulldown method to can be used for the present invention, and use transistor M4 and M5, be one of them example.
With reference to Fig. 4, it shows the detailed schematic diagram of input buffer 26.Data receive at DIN1, and export at DIN2.The afterbody of input buffer 26 is NOR doors 30.The first order in input buffer 26 can select to be operated in 5V or 3.3V.Particularly, when THREE signal is " 1 ", this Circnit Layout is for being operated in 3.3V, p channel transistor M7 conducting while being low that p channel transistor M6 allows DIN1.N channel transistor M13 turn-offs.In addition, p channel transistor M9 turn-offs, and take and prevents DIN1 p channel transistor M10 On current when low.N channel transistor M12 conducting.N channel transistor M8 and M11 will open, and be that bleedout is very low at present for height at DIN1.Therefore, transistor M7 and the M8 of an input of NOR door 30 in totem-pote circuit drives, and another input of NOR door 30 is drop-down by the transistor M12 of open-drain structure.For the transistor M7 that above draws and the size of M8, be set to a trigger point, for the operating state of desirable 3.3V.
On the other hand, when THREE signal is " 0 ", this Circnit Layout is for being operated in 5V, transistor M7 will be not can conduction current, and transistor M13 conducting, transistor M10 opens, transistor M12 closes.Therefore, an input of NOR door 30 is driven by transistor M10 and the M11 of totem-pote circuit, and another input of NOR door 30 is driven by the transistor M13 of open-drain structure.For the transistor M10 that above draws and the size of M11, be set to a trigger point, for the operating state of desirable 5V.
By way of example, following transistor channel size can be used in input buffer 26, and the size of raceway groove is listed (unit: micron): M6=24/2 in the mode of width/height; M7=24/2; M8=18/2; M9=22/2; M10=22/2; M11=54/2; M12=5/1; M13=5/1; M14=18/1; M15=18/1; M16=18/1; M17=18/1; M18=36/1 and M19=36/1.Equally, following transistorized channel dimensions can be used for output buffer 24:M1=450/1; M2=240/1; M3=300/1; M4=180/1; M5=260/1; M20=15/1; M21=30/1; M22=8/2.5; M23=10/1; M24=10/1; M25=44/1; M26=5.6/2.6; M27=16.3/2.6; M28=25/1.Yet, should be understood that, transistorized channel dimensions given here only as an example, can be used according to the invention other raceway groove large scale.
Example of the present invention as described herein has been embodied in an integrated circuit, some extra functions have wherein been comprised, in the patent application below of these functions, describe, its disclosure is hereby incorporated herein by reference: United States Patent (USP) Ser.No.08/451,319, be entitled as " can access the display controller for the external memory storage of gray modulation data " (attorney docket is NSC1-62700); United States Patent (USP) Ser.No.08/451,965, be entitled as " serial line interface that is operated in two kinds of different serial data transmission patterns " (attorney docket is NSC1-62800); United States Patent (USP) Ser.No.08/453,076, be entitled as " the multi-functional direct memory access of high-performance (DMA) controller " (attorney docket is NSC162900); United States Patent (USP) Ser.No.08/452,001, be entitled as " the Lou multi-source clock generator of opening with minimum pulse width " (agent's record of a case volume is NSC1-63000); United States Patent (USP) Ser.No.08/451,503, be entitled as " according to the integrated circuit of the multi-functional shared internal signal bus of distributed bus access control " (attorney docket is NSC1-63100); United States Patent (USP) Ser.No.08/451,924, be entitled as " the performance element framework of supporting * 86 instruction set and segment addressing in * 86 minutes " (attorney docket is NSC1-63300); United States Patent (USP) Ser.No.08/451,444, be entitled as " barrel shifter " (attorney docket is NSC1-63400); United States Patent (USP) Ser.No.08/451,204, be entitled as " using 8 of 32 bit datapath search, 16 or 32 positional operands " (attorney docket is NSC1-63500); United States Patent (USP) Ser.No.08/451,295, be entitled as " using double precision (64) shifting function of 32 bit data passages " (attorney docket is NSC1-63600); United States Patent (USP) Ser.No.08/451,571, be entitled as " method that execution has symbol division " (attorney docket is NSC1-63700); United States Patent (USP) Ser.No.08/452,162, be entitled as " using 32 barrel shift register sum counters to carry out the method for circulation " (attorney docket is NSC1-63800); United States Patent (USP) Ser.No.08/451,434, be entitled as " region and time is the on-the-spot circuit that extracts effectively " (attorney docket is NSC1-63900); United States Patent (USP) Ser.No.08/451,535, be entitled as " the usability status indicating circuit of non-arithmetic circular buffering unit " (attorney docket is NSC1-64000); United States Patent (USP) Ser.No.08/445,513, be entitled as " label of variable-length instruction set is looked ahead and the method for operation of Instruction decoding " (attorney docket is NSC1-64100); United States Patent (USP) Ser.No.08/450,153, be entitled as " decoding circuit of low power consumption operation " (attorney docket is NSC1-64200); United States Patent (USP) Ser.No.08/451,495, be entitled as " using processor decodes device to be used to specify the circuit of instruction pointer " (attorney docket is NSC1-64300); United States Patent (USP) Ser.No.08/451,219, be entitled as " circuit that produces need-based gated clock " (attorney docket is NSC1-64500); United States Patent (USP) Ser.No.08/451,214, be entitled as " adder/subtracter " (attorney docket is NSC1-64700); United States Patent (USP) Ser.No.08/451,150, be entitled as " microprocessor in the internal memory path of request exterior storage " (attorney docket is NSC1-64800); United States Patent (USP) Ser.No.08/451,198, be entitled as " code breakpoint decoder " (attorney docket is NSC1-64900); United States Patent (USP) Ser.No.08/445,569, be entitled as " two-layer buffer structure and the method for looking ahead of using bypass " (attorney docket is NSC1-65000); United States Patent (USP) Ser.No.08/445,564, be entitled as " microprocessor is surveyed instruction restriction and checked " (attorney docket is NSC1-65100); United States Patent (USP) Ser.No.08/452,306, be entitled as " microprocessor of the storage of controlling at same clock cycle request cache and external memory storage " (attorney docket is NSC1-65200); United States Patent (USP) Ser.No.08/452,080, be entitled as " compatible 486
tMthe apparatus and method of microprocessor POP instruction " (attorney docket is NSC1-65700); United States Patent (USP) Ser.No.08/450,154, be entitled as " apparatus and method of the memory address that specified data storage does not line up " (attorney docket is NSC1-65800); United States Patent (USP) Ser.No.08/451,742, be entitled as and " implement quick 486
tMthe method of the string operation instruction of microprocessor compatibility " (attorney docket is NSC1-65900); United States Patent (USP) Ser.No.08/452,659, be entitled as " microprocessor that prevents from reading high-speed cache when cache contents is invalid " (attorney docket is NSC166000); United States Patent (USP) Ser.No.08/451,507, be entitled as " dram controller that can reduce memory request process required time " (attorney docket is NSC1-66300); United States Patent (USP) Ser.No.08/451,420, be entitled as " integrated elementary bus and secondary bus controller/minimizing pin number " (attorney docket is NSC1-66400); United States Patent (USP) Ser.No.08/452,365, be entitled as " the configurable input/output (i/o) buffer of power supply and interface " (attorney docket is NSC1-66500); United States Patent (USP) Ser.No.08/452,365, be entitled as " clock generation circuit with the display controller of accurate, tunable frame rate " (attorney docket is NSC1-66600); United States Patent (USP) Ser.No.08/452,365, be entitled as " Managed Solution of power configuration " (attorney docket is NSC1-66700); United States Patent (USP) Ser.No.08/452,350, be entitled as " two-way simultaneous signaling interface " (attorney docket is NSC1-67000); United States Patent (USP) Ser.No.08/452,350, be entitled as " liquid crystal display (LCD) protective circuit " (attorney docket is NSC1-67100); United States Patent (USP) Ser.No.08/452,094, be entitled as " circuit emulator condition indication circuit " (attorney docket is NSC1-67400); United States Patent (USP) Ser.No.08/452,094, be entitled as " can from the display controller of the access of graphics data of shared system internal memory " (attorney docket be NSC1-67500); United States Patent (USP) Ser.No.08/450,726, be entitled as " with the integrated circuit of test signal bus and test control circuit " (attorney docket is NSC1-67600); United States Patent (USP) Ser.No.08/445,468, be entitled as " method of testing of decoding module and device " (attorney docket is NSC1-68000).
Should be understood that, realizing when of the present invention, described example is optional.Claim below limits scope of the present invention, and structure and method.
Claims (2)
1. the configurable inputoutput buffer of power supply and interface, is characterized in that: an inputoutput buffer comprises: a two-way node; An output stage, it has a N channel transistor and is coupling between two-way node and power junctions the above two-way node that draws; And have the first and second p channel transistors, it draws two-way node more than being coupled between two-way node and power junctions; An input stage, it has, and a first inverter utmost point is coupling between two-way node and the first intermediate node, a second inverter utmost point is coupling between two-way node and the second intermediate node, and input stage also has a 2nd N channel transistor and is coupled between the first intermediate node and grounding node and the 3rd N channel transistor is coupled between the second intermediate node and grounding node; A control circuit, it is coupled to output stage and input stage, at output mode, enable output stage, and forbid output stage at input pattern, and control circuit has first node, this node is forbidden the first and second p channel transistors and is enabled a N channel transistor when power junctions exists first voltage source, and enables the stage of the second inverter and turn-off the 3rd N channel transistor.
2. a kind of power supply according to claim 1 and the configurable inputoutput buffer of interface, it is characterized in that: buffer circuits also comprises: a Voltagre regulator, it is coupled to grid and the control circuit of a N channel transistor, for opening a N channel transistor; A delay circuit, it is coupled to grid and the control circuit of the second p channel transistor, for open the second p channel transistor after a delay time of the first p channel transistor conducting; A NOR door, one of them input is coupled to the first intermediate node, and another input is coupled to the second intermediate node.
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| CN201310616477.8A CN103618541A (en) | 2013-11-28 | 2013-11-28 | Input/output buffering device with configurable interfaces and power source |
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| CN201310616477.8A CN103618541A (en) | 2013-11-28 | 2013-11-28 | Input/output buffering device with configurable interfaces and power source |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105281711A (en) * | 2015-10-26 | 2016-01-27 | 宁波大学 | CNFET (Carbon Nanotube Field Effect Transistor)-based single-edge pulse signal generator |
| WO2016176836A1 (en) * | 2015-05-06 | 2016-11-10 | 京微雅格（北京）科技有限公司 | Buffer circuit and electronic device utilizing same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5612637A (en) * | 1995-05-26 | 1997-03-18 | National Semiconductor Corporation | Supply and interface configurable input/output buffer |
| CN101174829A (en) * | 2006-11-03 | 2008-05-07 | 联发科技股份有限公司 | Output buffer and circuit with controllable rotation rate |
-
2013
- 2013-11-28 CN CN201310616477.8A patent/CN103618541A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5612637A (en) * | 1995-05-26 | 1997-03-18 | National Semiconductor Corporation | Supply and interface configurable input/output buffer |
| CN101174829A (en) * | 2006-11-03 | 2008-05-07 | 联发科技股份有限公司 | Output buffer and circuit with controllable rotation rate |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016176836A1 (en) * | 2015-05-06 | 2016-11-10 | 京微雅格（北京）科技有限公司 | Buffer circuit and electronic device utilizing same |
| CN105281711A (en) * | 2015-10-26 | 2016-01-27 | 宁波大学 | CNFET (Carbon Nanotube Field Effect Transistor)-based single-edge pulse signal generator |
| CN105281711B (en) * | 2015-10-26 | 2017-11-10 | 宁波大学 | It is a kind of unilateral along pulse signal generator based on CNFET |
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Application publication date: 20140305 |