CN103617995A - Power source voltage load dump protective circuit - Google Patents
Power source voltage load dump protective circuit Download PDFInfo
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Abstract
The invention discloses a power source voltage load dump protective circuit so as to ensure that a supply voltage is applied to a low-current logic circuit and prevent the supply voltage from exceeding a preset voltage and damaging the logic circuit. Similarly, the voltage also appears at the output of the logic circuit so as to protect three circuit areas.
Description
Technical field
The present invention be directed to the protection on circuit chip, prevent power supply transient load dump, the structure of operative installations in such circuit, and for the manufacture of the method for these structures.
Background technology
Integrated circuit (IC)-components is especially easily damaged when power supply transient, unless protective circuit is provided.Can be protected in the situation that of a kind of worst being called as " load dump automatically ".This situation can describe with the curve chart providing in Fig. 1.
As everyone knows, in the autoelectrinic system of a basic configuration, battery and alternating current generator are connected in the input power pad of the various low current logical circuits in system in parallel.Alternative electric generation function produces large electric current battery is charged, and other automobile loads are provided.When " load dump " event occurs, the load of generator disconnects, for example, when battery contact is loosening or in more not serious example, as the headlight when automobile is closed.Because the electric current of alternating current generator flows through its intrinsic inductance, set up the vertiginous magnetic field of output current that prevents alternating current generator.When the load of alternating current generator reduces suddenly, charges, thereby be based upon operating circuit
v dD the voltage of power pad is still connected to the output of alternating current generator.
As shown in Figure 1, voltage increases suddenly, or " load dump transition ", is provided to
v dD power pad is in t=0 o'clock.The time that this is of short duration, can be expressed as
millisecond.In typical automotive system, voltage is to approach very much battery, and along with the distance with battery increases and successively decreases.For example, in enging cabin, transient voltage may reach 80V, and fire compartment wall is 60V, at passenger carriage, is 40V.
Clearly, the logical circuit in system must remain on its normal mode of operation and arrive 16V's
v dD supply voltage.But, if supply voltage
v dD rise to higher than 16V, as load dump transient affair, the normal running that destroys circuit allows, still can not cause the permanent damage of internal circuit, by it output it can not transmit the voltage that is greater than 20V to other circuit in system.When as shown in Figure 1, supply voltage
v dD return and be less than 16V, As time goes on, this circuit must turn back to normal operation.
The conventional method of the transition load dump of dealing with problems is just to provide an external passive components, is arranged between the power supply weld pad of power supply and operating circuit.This needs outside resistance-capacitance network as a filter conventionally, prevents that voltage from increasing sharply.In addition, an external inductance is connected and is inserted into operating circuit with operating circuit, resists the transient current that instantaneous variation causes.These solutions need extra element, thereby increase cost and consume valuable internal system space.
Summary of the invention
Therefore, a main purpose of the present invention is to provide integrated protection, prevents power supply transient load dump.
Another object of the present invention is to utilize the unique application of traditional process technology, and integrated protective circuit is provided.
Another object of the present invention is to provide the power supply transient to inner executive circuit, and provides integrated protection to the transient state of the output voltage by internal circuit.
Load dump protective circuit these and other object of the present invention, advantage and feature will be better understood, by the detailed description in conjunction with the preferred embodiments of the present invention below and by reference to the accompanying drawings.
Technical solution of the present invention:
According to the present invention, protective circuit is integrated is operated in the logical circuit of low current, and like this, operating circuit can be experienced
v dD power supply transient, recovers, and then turns back to normal operation and avoids permanent damage.In addition, protective circuit guarantees that transient voltage can not travel through operating circuit to system data bus by its output line.It provides one to have
v dD the interface of the external logic signal level of 16V level and 16V, for level shifting circuit on integrated regulator and monolithic provides further protection.
In protective circuit of the present invention, adopt knot Isolation CMOS device technology.The equipment that has thickness to be about 1000 dust gate oxides is to be used to provide 9-16V automobile power line and signal wire interface.Utilization has the equipment of thickness approximately 400 dust gate oxides that 5V logic and treatment circuit are provided, and these devices all adopt integrated 5V pressurizer.Voltage reduces device and is connected to
v dD between power pad and computing circuit, and the remainder of computing circuit is used for the voltage and current of restricted passage computing circuit.
Therefore, just as described above, three integrated circuit regions have obtained the protection of transition load dump.First, the logical circuit of the low current of integrated 16V will be by will
v dD power pad is connected to the polysilicon resistance of the higher value of the power supply terminal that is connected in series to these circuit, and it is protected.Secondly, the circuit of the output signal of the integrated high electric current of 16V is by directly connecting
v dD power pad is to the source electrode of the P channel MOS output driver of output circuit, and the drain electrode of driver is connected to the pad of output signal, and it is protected.The 3rd, integrated 5V voltage-stabilized power supply circuit passes through
v dD power pad is connected to the polysilicon resistance of the p channel MOS output driver source electrode that is connected on voltage stabilizing circuit, and the drain electrode of output driver is connected to 5V stabilized voltage power supply pad, and it is protected.
The grid of each p channel MOS driver transistor is connected to an integrated voltage detection circuit, when supply level being detected, is greater than 16V, with regard to short gate, is driven into its source electrode to be closed.Each grid of these equipment is also passed a series of high value N trap diffusion resistance and is connected to by the control logic of normal operation.
The unique design of all above-mentioned transistors and resistance can be born the transient state of maximum load dump voltage and current, also in the normal processing procedure of manufacturing.
The mobile unit power-supply system 201220024900.6 of mono-kind of patent documentation: CN202424291U of contrast based on energy acquisition chip.
Accompanying drawing explanation:
Fig. 1 is a curve chart, time dependent voltage between the power source loads bust transient period illustrating.
Fig. 2 is the rough schematic view that an integrated load dump protective circuit is in accordance with a preferred embodiment of the present invention shown.
Fig. 3 be one for the cutaway view of the p-channel device structure of exploded view 2 load dump protective circuits.
Fig. 4 be one for the cutaway view of the further fine structure of p-channel device of exploded view 2 load dump protective circuits.
Fig. 5 be one according to of the present invention, close the schematic diagram of integrated load dump detection latches of the output driver of logical circuit.
Fig. 6 is the schematic diagram of analysis of the grid voltage of a P channel MOS driver transistor when load dump.
Fig. 7 be one according to the schematic diagram of the integrated load dump protective circuit for power regulator of the present invention.
Fig. 8 be one for the analysis schematic diagram of the load dump electric current of analysis chart 7 power regulators.
Embodiment:
Fig. 2 has shown the load 12 of automobile, as automobile batteries, by switch S 1, is connected to
v dD the integrated circuit 10 of power pad 13.The power supply 16 of alternating current generator is also connected to power pad 13.The opening of switch S 1 represents the appearance that work is disturbed, and this is by the generation causing in the power source loads bust transient state of Fig. 1 shown type.
Be connected to V
dDbetween power pad 13 and a low current logical circuit 14 is the polysilicon resistance 18 of 2K Ω.Although polysilicon resistance 18 is shown in Figure 2, should be appreciated that they can be connected in parallel by a plurality of resistance as resistance, each such resistance is connected to an independent logical circuit.
In automobile application, the normal cell voltage of voltage at the logical circuit 14 of low current from 0V to about maximum 16V, fluctuate.Voltage drop at resistance 18 two ends of normal work period will be little, because logical circuit 14 needs low-down electric current to work under normal operation.Yet when as shown in Figure 1, at one of short duration in the situation that, resistance 18 declines most of transient voltages while carrying out the equipment in protective circuit 14, with supply voltage V
dDrise to about 60V.
Therefore, in the present invention, first aspect, polysilicon resistance film 18 is according to being connected on
v dD the logical circuit 14 of power supply to low current protected and provided to power pad 13.As described above, when power supply transient, resistance 18 plays the source current of circumscription logic circuit 14.Under normal operation, each polysilicon resistance 18 is understood by being less than the electric current of 50 microamperes, and falls the voltage less than 100 millivolts.Resistance 18 will be made enough large, with unburned bad power supply between load dump transient period.Because the thickness that their manufactured peroxidating layers have is 6-12K dust, so resistance 18 can be isolated for the remainder of logical circuit 14 voltage of about 60-120V.The size of shown resistance 18, easily realizes in 2 μ * 200 micron.
The output inverter that drives the o pads 15 of logical circuit 14, has proposed a more difficult design problem, because it must be the driving of low-resistance.For example
or
the impedance of ohm.Wherein
v oH equal the output voltage at pad 15,
equal the output current at pad 15.
Use the supply voltage on above-described polysilicon resistance and each output driver
v dD series connection, this is unpractical, this is that these large scale polysilicon resistance output driver equipment can take very large chip area, cause the expansion of chip area because logical circuit 14 has a lot of output conventionally.
Therefore, according to a second aspect of the invention, provide a kind of load dump protective circuit, it detects the transient voltage of power supply, and stops it to arrive the o pads 15 of integrated circuit 10.
When a power supply generation load transient, when switch S 1 is opened,
v dD supply voltage rises (as shown in fig. 1) immediately.When normal open switch S3 detects transient state, it can be closed, and therefore, the grid of short circuit driver 20 and source electrode, carry out Down Drive 20.If switch S 3 is not for existing, load dump voltage can open output equipment 20 and the full load bust electric current of p channel-type will be by device 20.This electric current is by output device 20 and n-raceway groove output device 22 even as big as destroying.It is also by the element destroying potentially on data/address bus, and when being greater than 20V, the electric current on data/address bus passes through low-resistance data/address bus under these conditions,
milliampere.
As described above, and as will be described in more detail below, the invention provides a kind of testing circuit, this circuit is closed output driver 20, and protects all parasitic bipolar device when load dump transition, wherein 20V≤
v dD ≤ 60V, then returns to output driver 20 to normal operation, supply voltage
v dD turn back to lower than 17V.
In the normal work period of integrated circuit 10, the data/address bus relevant to circuit 10 need to be pulled to full cell voltage.Accomplish this point, in normal working conditions, the rated voltage of output driver 20 is 20V.Yet as described in more detail below, driver 20 also can bear the high voltage producing during power supply transient condition.
As described above, according to a third aspect of the invention we, output driver 20 is constructed such that it can bear its grid when drain electrode is closed and the puncture voltage 40V between its source electrode, its source electrode and ground connection
v sS puncture voltage 60V between silicon substrate.This can be by providing a unique p channel-type, and the design of N trap MOS device is to realize for dragging down output pin 15.A traditional N-channel MOS device 22 is for dragging down the output of pin 15.These two devices 20 and 22, manufacture the gate oxide thickness with approximately 1000 dusts, the puncture voltage providing
bV dSS approximate 20V.In addition, will illustrate in greater detail below, the puncture voltage of p-channel device 20 can arrive about 42V, because hot electron is injected near leakage-body avalanche breakdown region of gate oxide.
As shown in Figure 3, it is a well-known phenomenon to reference figure, and hot electron " e " can charge to the gate oxide of field-effect transistor, and reduces the electric field strength in depletion layer, thereby permission puncture voltage
bV dSS increase.Due to this effect, at output driver 20, the special-purpose load dump protective circuit when closing switch S3 representative, will make drain/source pole tension
v dS about 42V, makes output voltage like this
v oUT be less than or equal to 60V-42V=18V.
More specifically, as shown in Figure 3, when the source electrode of device 20 and the voltage difference increase in drain electrode, the depletion layer that does not comprise any free carrier region according to definition becomes larger, and ever-increasing voltage is slowed down.Electric field is created such result, because free carrier is stripped from out, has left ion doping atom.Therefore, P+district has " h " as free carrier, is stripped from, and has left negative boron ion.On the contrary, in N-region, electronics is peeled off by high source/drain electrode potential, has left positive phosphonium ion.This will create positive charge N-district, and negative electrical charge is in P+district, and produce a large electric field across intersection between the two.Due to
v dD supply voltage while increasing, it is stronger that electric field becomes, the physical silicon main material of electronics " e " tears off.At this moment, electronics moves freely under electric field action.Owing to installing 20 polysilicon gate, be to be connected to together positive potential, electronics has attracted to positive potential, and free electron " e " floats to polysilicon gate rapidly.Therefore, free electron is crossed over potential barrier and is entered gate oxide, and the gate oxide of a negative electrical charge is provided.The intersection avalanche breakdown voltage that this negative electrical charge increases
bV dSS .
In addition, utilize the parasitic bipolar device of MOS manufacturing process structure circuit, its can bear from
v dD node (P+and N-) arrive
v sS the reverse bias of the 60V of node (P-), as shown in diagram 4.
In traditional design, p raceway groove output driver has a N+guard ring that is manufactured on the surrounding of equipment, high-tension to prevent that reversion from producing while forming
pin.According to a forth aspect of the invention, as shown in Figure 4, the output driver 20 of p channel-type channel has a field plate 25 of manufacturing around it.This field plate 25 is connected to the maximum potential of output buffer (being N trap), therefore, can not form inversion channel district at N-.In addition, as described later, under the existence of field plate 25, the avalanche breakdown voltage of the N of increase trap/P substrate knot is greater than 60V.
Field plate phenomenon in Fig. 4 makes N trap/P substrate tie plane seemingly, and in fact, it is crooked.Because electric field is strong bending area, the curvature of intersection has reduced puncture voltage.Therefore, positive charge is placed on to outside, exceeds PN junction, and extend to negative potential, in effect, increased the radius of curvature of intersection.
Therefore, according to the present invention, rather than injected carrier as shown in Figure 3, there is the field plate 25 of identical positive potential with N trap, extend to physically knot, increase avalanche breakdown voltage.On the contrary, place negative electrical charge at field plate 25, that is, making the electromotive force of its substrate is negative potential, and making intersection seems that physical bend is returned.Like this, if it is to be connected to diffusion N well area, the electric field strength of field plate 25 can reduce; If field plate is connected to substrate, electric field strength can increase.
Therefore, in the design of output driver 20, three conditions are met, and to maintain between N trap and P-substrate, are isolated under 60V bias voltage.First, parasitic bipolar transistor keeps closing in the situation that there is no base drive.Secondly, in vertical and horizontal direction, N-spreads abundant overlapping P+diffusion region simultaneously, punctures preventing.The 3rd, substrate doping is enough few, and the abundant overlapping PN junction of field plate 25, is enough to prevent avalanche breakdown.In general, according to the present invention, the concept of field plate is under any time of utilizing in logical circuit and protective circuit, the resistance of a N-type trap or a P raceway groove, and the equipment of N-type trap is easy to apply the voltage of 60V to it.
According under load dump transient condition, the action of field plate 25 as shown in Figure 4.Overlapping N-trap field plate is " a+b ".
electromotive force across the distance on silicon face, be the place of " a " at present.On silicon face, the electromotive force in " b " region is
.When overlapping reducing, the distance in the region of " b " becomes 0.Then, region " a " reduces.When region, " a " reduces, and PN puncture voltage will reduce.In order to obtain maximum PN puncture voltage, a=c, the N-type trap of the below of " c " is wherein diffused into the depletion layer of P substrate.The electric field E field plate that is come from polysilicon field plate as a+b>c is captured, and because they are to be kept apart by oxidation and depletion layer and current source, so do not flow, at this moment, 25 times formation free electrons of field plate.
The circuit of an embodiment that detects load dump transient state and close the output driver 20 of p channel-type is shown in Fig. 5.In Fig. 5, in p-channel device 20, switching transistor 33(is determined to be in the switch S 3 in Fig. 2) and 40K Ω resistance 24 corresponding to similar element in Fig. 2.
As mentioned above, in order to close p-raceway groove output driver 20, need closing switch 33.In the circuit shown in Fig. 5, this means detector circuit, comprise resistor 32, transistor 28, resistor 30 and transistor 26, the necessary node V that produces the grid of an activator switch transistor 33
2voltage.Therefore, parts 26,28,30 and 32 be configured to form one simple, by supply voltage
v dD the latch of controlling.When
v dD when supply voltage uprises, transistor 26 and 28 is opened.When
v dD supply voltage declines and falls back to the level of a safety, and lower than 17V, transistor 26 and 28 is closed.
Latch can be regarded two inverters as, a PMOS inverter and a NMOS inverter, and in a circulation, the output of n channel-type inverter is provided to the grid of switching transistor 33.
As shown in Figure 5, work as supply voltage
v dD rise to higher than transistor 26 (
be accompanied by the avalanche breakdown voltage of the oxidation grid of 1000 dusts, long length of effective channel, transistor 26 has not according to it
i d with
v dSS curve recover), then, node V
2be clamped at
.If supply voltage
v dD higher than
, transistor 28 and switch 33 can be opened so.When switching transistor 33 conducting, output driver 20 is closed and is prevented with excessive load dump voltage on o pads 15.If output voltage V
oUTbe allowed to surpass 18V, the output driving arrangement of n channel-type (device 22 in Fig. 2) and may damaging at the outer member of data/address bus.
The size that is shown in the equipment in the load dump detection latches in Fig. 5 is like this, when
v dD voltage is less than or equal to 18V, and latch transistor 26 and 28 will be closed, and does not produce quiescent current, and switching transistor 33 will be closed.This is essential, works as like this supply voltage
v dD during lower than 18V, driver 20 can normal operation.Accomplish this point,
be designed to be less than or equal to
v t26 , when
v dD be less than 18V, transistor 26 will be closed, node V2=
v dD .This is by resistance 32=40K Ω, transistor 28
also have
realize.In addition,, in conjunction with Fig. 4, by using N-type trap and field plate, resistance 24,32 and 30 is all designed to bear 60V voltage.
Under transient condition, transistor 26 avalanche breakdowns.That is to say, when being applied to the supply voltage of transistor 26
v dD while becoming too high, electric current starts to flow through resistance 30.This will open transistor 28.Conversely, transistor 28 allows current flowing resistance 32, makes transistor 26 conductings.All these start the avalanche breakdown by transistor 26.Resistor 30 Limited Currents, are not destroyed transistor 26, but cause latch to be opened and cause switching transistor 33 conductings.On the contrary, when
v dD supply voltage returns to normal value, is less than 17V, and the voltage at resistance 32 two ends becomes low level, and transistor 26 is closed, and this latch resets, and closing switch transistor 33.
Utilize transistor 28 and resistance 32, structure load dump detection latches, rather than delete their advantage, when the grid of transistor 28 is by transistor 26
bV dSS clamper is at 18V, and supply voltage
v dD rise to over transistor 26 with the source electrode of transistor 28
bV dSS , add 18V, so node
v 2 will be latched device and be arranged on 0V.This will occur in load dump transition and be greater than the rising edge of 36V.Latch will keep node
v 2 at 0V until at the supply voltage of load dump
v dD be less than 18V.Because latch, transistor 20 is closed, in the whole time course of load dump that is more than or equal to 36V (time t=0),
i oUT be approximately 0 and
v oUT be less than 20V.
When the amplitude of load dump is less than 36V(time t=0) latch can not start, but node V
2can remain on transistor 26
bV dSS equal 18V.Switch 33 will be opened, and can make
v 3 be greater than
, so just make output driver 20 close, as described in Figure 6.
Fig. 6 provide for output transistor 20 provide test model value load dump protective circuit equipment 33 work and
the schematic diagram of ratio.Circuit working can be calculated, by use equation below (wherein
v dS ,
v gS with
v tO all negative value) result all provides in table 1.
?
Wherein
When
time, transistor 20 can be closed.
Table 1
As shown in Figure 7, the present invention also provides the load dump protection of the power supply of single-chip power supply voltage stabilizing.Power supply stabilization circuit depends on for output driver 20 identical load dump detection latches and switching circuit, as mentioned above.
The object of monolithic voltage stabilizing is to reduce voltage V
dDpower supply level, this is to lie prostrate from the about 9-16 by battery, to the 5V of integrated 5V logic load supply.
Except load dump detector and latch (being element 26,30,28 and 32), polyresistor 39 series connection of switching transistor S2 and 34, one 100 Ω of isolation resistor are added on the output driver 36 of pressurizer.Resistor 39 is essential, because output voltage V
rEGdo not allow to surpass 10V, because the low-voltage at circuit is partly used the avalanche breakdown voltage of gate oxidation equipment of 400 dusts lower.Therefore, provided the demand of the pressurizer of maximum 10V, and restriction p channel device 36V
dS=40V, the extra 10V of the transient state of the processing 60V of resistance 39, as shown in Figure 8.
Refer again to Fig. 7,
resistance 38 provides a little electric current by Zener diode 40, at the grid maintenance 5V of N channel device 42 reference voltage.N channel device 42 and 44, in conjunction with P- channel device 46 and 48, as a comparator circuit, keeps voltage V
rEGwith the voltage on the grid of equipment 42 in identical rank.Because the grid of N channel device 44 is connected to voltage V
rEG, two N channel devices 42 and 44 grid all remain on 5V.Therefore, if voltage V
rEGuprise, the grid that stabilizer output voltage is applied to P-channel device 36 will make device 36 close.
The load dump analysis of the electric current in pressurizer as shown in Figure 8.Load dump electric current
.From t=0 to t=29 millisecond.
milliampere is to 0 milliampere.
Standard low-voltage process technique is for manufacturing high-tension apparatus, as output driver 20, as mentioned above.Therefore, P substrate, N-type trap and field oxide region are to define according to the step of conventional MOS technique.So, the gate oxide of thick 700 dusts is layered on the region that zoneofoxidation has been eliminated.Then the thick oxide layer in selected region shields and etching.Then the oxide layer that one deck is very thin is layered on these regions, defines 400 dust thin gate oxides, and 1000 dust gate oxides are not removed oxide and the field oxide region of 700 dusts in these regions.Then, use standard MOS to process, to complete this equipment.
Those skilled in the art also will appreciate that, the present invention can be different from above-mentioned example, and described example only for illustrative purposes, rather than restrictive, and the present invention is only defined by the claims scope.
Claims (5)
1. a supply voltage load dump protection circuit, is characterized in that: comprise an o pads, a supply voltage pad, is connected in series in power supply and for receive the computing circuit of supply voltage from power supply, a MOS output pulls up transistor, it is formed in Semiconductor substrate, and comprise source electrode, drain and gate, it is characterized in that, described source electrode is connected to power pad, drain electrode is connected to o pads, grid is connected from computing circuit and receives output signal, output pulls up transistor and is configured to bear the puncture voltage between the source electrode between the previously selected source electrode at it and described Semiconductor substrate and drain electrode, and checkout gear is connected between the grid that power pad and output pulls up transistor, for detection of the supply voltage that surpasses predetermined voltage, and closing described output pulls up transistor, described checkout gear comprises that output pulls up transistor, the switch connecting between source electrode and gate electrode, with a load dump detection latches, it has an input that is connected to power pad, an output that is connected to switch, voltage when power pad place surpasses preset value like this, and the output of latch will make switch close, wherein switch comprises a MOS switching transistor, its source electrode is connected to power supply weld pad, and its drain electrode is connected to the grid that MOS output pulls up transistor, and its grid receives the output of latch, make when latch output surpasses the voltage of preliminary election switching transistor conducting.
2. according to a kind of supply voltage load dump protection circuit described in claim 1, it is characterized in that: also comprise an o pads, a supply voltage pad, is connected in series in power supply and for receive the computing circuit of supply voltage from power supply, a MOS output pulls up transistor, it is formed in Semiconductor substrate, and comprise source electrode, drain and gate, it is characterized in that, described source electrode is connected to power pad, drain electrode is connected to o pads, grid is connected from computing circuit and receives output signal, output pulls up transistor and is configured to bear the puncture voltage between the source electrode between the previously selected source electrode at it and described Semiconductor substrate and drain electrode, and checkout gear is connected between the grid that power pad and output pulls up transistor, for detection of the supply voltage that surpasses predetermined voltage, and closing described output pulls up transistor, described checkout gear comprises the switch connecting between the source electrode that pulls up transistor of output and grid, with a load dump detection latches, it has an input that is connected to power pad, an output that is connected to switch, voltage when power pad place surpasses preset value like this, and the output of latch will make switch close, middle switch comprises a MOS switching transistor, and its source electrode is connected to power supply weld pad, and its drain electrode is connected to the grid that MOS output pulls up transistor, and its grid receives the output of latch, makes when latch output surpasses the voltage of preliminary election switching transistor conducting, load dump detection latches comprises first resistance device being connected between power pad and first node, and the grid that is connected to the first switching transistor provides one to latch output, a the one MOS latch transistor, its drain electrode is connected to first node, and source electrode is connected to earth potential, and grid is connected to Section Point, a the 2nd MOS latch transistor, its source electrode is connected to power pad, and drain electrode is connected to Section Point, and grid is connected to first node, also has second resistance device being connected between Section Point and earth potential, further comprise the 3rd resistance device being connected between switching transistor and earth potential, further comprise a MOS output pull-down transistor, its drain electrode is connected to o pads, and source electrode is connected to earth potential, and grid is accepted the output signal of computing circuit.
3. according to a kind of supply voltage load dump protection circuit described in claim 1, it is characterized in that: comprise an o pads, a supply voltage pad, is connected in series in power supply and for receive the computing circuit of supply voltage from power supply, a MOS output pulls up transistor, it is formed in Semiconductor substrate, and comprise source electrode, drain and gate, it is characterized in that, described source electrode is connected to power pad, drain electrode is connected to o pads, grid is connected from computing circuit and receives output signal, output pulls up transistor and is configured to bear the puncture voltage between the source electrode between the previously selected source electrode at it and described Semiconductor substrate and drain electrode, and checkout gear is connected between the grid that power pad and output pulls up transistor, for detection of the supply voltage that surpasses predetermined voltage, and closing described output pulls up transistor, wherein further comprise a polysilicon resistance being connected between power pad and voltage stabilizing output driving transistors, wherein the value of polysilicon resistance is about 100 ohm, wherein voltage stabilizing output driving transistors is formed in Semiconductor substrate, and comprises source electrode, drain electrode, grid, and wherein source electrode is used for from power pad receiver voltage signal, and drain electrode is connected to voltage stabilizing o pads, and grid is used for receiving output signal from checkout gear, voltage stabilizing output driving transistors is configured to bear the puncture voltage between the source electrode between the previously selected source electrode at it and described Semiconductor substrate and drain electrode, wherein checkout gear comprises: a switch being connected between power pad and the grid of voltage stabilizing output driving transistors, a load dump detection latches, it has an input that is connected to power pad, an output that is connected to switch, the voltage when power pad place surpasses preset value like this, and the output of latch will make switch close, comprising a MOS switching transistor, its source electrode is connected to power supply weld pad, and its drain electrode is connected to the grid that MOS output pulls up transistor, and its grid receives the output of latch, makes when latch output surpasses the voltage of preliminary election switching transistor conducting.
4. according to a kind of supply voltage load dump protection circuit described in claim 1, it is characterized in that: comprising: (a) resistance device, is connected between power pad and the remainder of computing circuit, to limit the source current of the remainder of computing circuit; (b) for preventing that excessive supply voltage from appearing at the device of the output of computing circuit, described protector comprises: (i) a MOS output pulls up transistor, it has source electrode, drain electrode, grid, source electrode is connected to power pad, grid comes to receive output signal from computing circuit, and drain electrode is connected to o pads; (ii) load dump checkout gear is connected between the source electrode and grid of output driving transistors, in response, to excessive supply voltage, just closes output driving transistors; (iii) one is connected to the grid that pulls up transistor of output and the resistance between computing circuit, and load dump checkout gear is connected between one end of resistance and grid that MOS output pulls up transistor; (iv) such output pull-down transistor, has source electrode, drain electrode, grid, and drain electrode comes to receive output signal from computing circuit, and source electrode is connected to earth potential, and grid is connected between second end and computing circuit of resistance.
5. according to a kind of supply voltage load dump protection circuit described in claim 1, it is characterized in that: also comprise a supply voltage pad; A voltage stabilizing o pads; When voltage stabilizing output transistor is connected between power pad and voltage stabilizing o pads, the voltage that is used for controlling voltage stabilizing o pads is at a preset value; A device that is used for producing the reference voltage that equals preset value; Comparator device, is connected between reference voltages means and voltage stabilizing o pads, keeps the voltage of preliminary election at the level of reference voltage; Checkout gear, is connected between power pad and voltage stabilizing output driving transistors, detects supply voltage, when surpassing preset value, closes voltage stabilizing output transistor; Wherein voltage stabilizing output transistor comprises source electrode, drain electrode, grid, its source electrode is used for from power pad receiver voltage signal, drain electrode is connected to voltage stabilizing o pads, grid comes to receive output signal from checkout gear, and voltage stabilizing output driving transistors is configured to bear the puncture voltage between the source electrode between the previously selected source electrode at it and described Semiconductor substrate and drain electrode; Described checkout gear comprises the switch connecting between the source electrode that pulls up transistor of output and grid, with a load dump detection latches, it has an input that is connected to power pad, an output that is connected to switch, voltage when power pad place surpasses preset value like this, and the output of latch will make switch close; Middle switch comprises a MOS switching transistor, and its source electrode is connected to power supply weld pad, and its drain electrode is connected to the grid that MOS output pulls up transistor, and its grid receives the output of latch, makes when latch output surpasses the voltage of preliminary election switching transistor conducting; Load dump detection latches comprises first resistance device being connected between power pad and first node, and the grid that is connected to the first switching transistor provides one to latch output; A the one MOS latch transistor, its drain electrode is connected to first node, and source electrode is connected to earth potential, and grid is connected to Section Point; A the 2nd MOS latch transistor, its source electrode is connected to power pad, and drain electrode is connected to Section Point, and grid is connected to first node; Also has second resistance device being connected between Section Point and earth potential.
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| CN201310599291.6A CN103617995A (en) | 2013-11-25 | 2013-11-25 | Power source voltage load dump protective circuit |
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| US4835416A (en) * | 1987-08-31 | 1989-05-30 | National Semiconductor Corporation | VDD load dump protection circuit |
| CN101800467A (en) * | 2010-03-11 | 2010-08-11 | Bcd半导体制造有限公司 | A kind of protective circuit of Switching Power Supply |
| CN202026077U (en) * | 2010-12-10 | 2011-11-02 | 上海新进半导体制造有限公司 | Short circuit protection circuit for switch power supply, controller for switch power supply, and switch power supply |
| CN203983279U (en) * | 2013-11-25 | 2014-12-03 | 苏州贝克微电子有限公司 | A kind of supply voltage load dump protection circuit |
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2013
- 2013-11-25 CN CN201310599291.6A patent/CN103617995A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4835416A (en) * | 1987-08-31 | 1989-05-30 | National Semiconductor Corporation | VDD load dump protection circuit |
| CN101800467A (en) * | 2010-03-11 | 2010-08-11 | Bcd半导体制造有限公司 | A kind of protective circuit of Switching Power Supply |
| CN202026077U (en) * | 2010-12-10 | 2011-11-02 | 上海新进半导体制造有限公司 | Short circuit protection circuit for switch power supply, controller for switch power supply, and switch power supply |
| CN203983279U (en) * | 2013-11-25 | 2014-12-03 | 苏州贝克微电子有限公司 | A kind of supply voltage load dump protection circuit |
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Application publication date: 20140305 |