CN103617952B - Diode wet etching method - Google Patents

Abstract

The invention discloses a diode wet etching method. The diode wet etching method comprises the following steps: a. etching the conductive layer and the barrier layer to form a plurality of etched units; b. etching an adhesion layer formed between the plurality of etched units; c. and etching the edge portions of the conductive layers and the edge portions of the barrier layers of the plurality of etched units to expose the edges of the adhesion layers of the etched units from under the conductive layers and the barrier layers. Compared with the existing wet etching, the method provided by the invention adds a step of secondarily etching the conductive layer and the barrier layer. Thus, the obtained adhesion layer is exposed out of one side more than the barrier layer and the conductive layer on the adhesion layer, and the occurrence of undercutting of the adhesion layer is effectively reduced. And when the under-mirror inspection is carried out, judging whether the bottom metal layer adhesion layer undercuts or not according to the existence of the edge. The existence of the edge indicates that undercutting does not occur, and the existence of the edge does not influence the use of the product.

Description

Diode wet etching method

technical field

The invention relates to a diode manufacturing method, in particular to a Schottky barrier diode wet etching method.

Background technique

The front of the Schottky barrier diode (SBD) adopts a multi-layer metal structure, and in this structure, from the silicon substrate 4 upwards are the adhesion layer 1, the barrier layer 2 (filter layer) and the conductive layer 3 in sequence.

In the manufacturing process of Schottky barrier diodes, there are many wet etching methods for etching multilayer metal layers on silicon substrates. For example:

Method 1, using layer-by-layer etching, first corroding the conductive layer, then corroding the barrier layer, and finally corroding the adhesion layer. This method has high requirements on the process, and it is difficult to achieve the ideal effect as shown in Figure 1. It is easy to cause over-corrosion of the adhesion layer of the underlying metal layer (undercutting as shown in Figure 2 as shown in 10), or cause metal cracking. Process issues such as delamination, uneven metal edges, etc.

In method 2, the barrier layer and the conductive layer are corroded together, and then the adhesion layer is corroded. It is more common to use method 2 to etch multi-layer metals. This method is simpler than method 1, but the disadvantage is that the underlying metal layer is easy to undercut, resulting in the problem shown as 10 in Figure 2, that is, the underlying metal layer adhesion layer is undercut. Since the inspection under the microscope is from the top down, only the surface of the conductive layer can be seen. Even if the underlying metal is corroded, the corroded adhesion layer below it cannot be inspected, so the undercutting is not easy to be detected. . Once the undercutting problem occurs, it will affect the reliability of the device, and if the undercutting is serious, it will cause the metal layer to fall off and other problems.

However, such problems are generally considered to be inherent to the process and have not attracted attention and motivation for improvement.

Contents of the invention

The object of the present invention is to provide a diode wet etching method, which can overcome one or more of the above-mentioned defects in the prior art.

According to one aspect of the present invention, a diode wet etching method is provided, comprising the following steps: a, corroding the conductive layer and the barrier layer to form a plurality of etched units; b, corroding the adhesion between the plurality of etched units layer; c, corroding the edge portion of the conductive layer and the edge portion of the barrier layer of the plurality of etched units, so that the edge of the adhesion layer of the etched unit is exposed from under the conductive layer and the barrier layer.

Compared with the existing wet etching, the invention adds a second step of corroding the conductive layer and barrier layer. In this way, the adhesion layer exposes one side more than the upper barrier layer and the conductive layer, effectively reducing the occurrence of undercutting of the adhesion layer. When inspected under a microscope, the presence or absence of this edge is used to determine whether the underlying metal layer adhesion layer is undercut. The existence of this edge indicates that undercutting does not occur, and the existence of this edge will not affect the use of the product.

In some embodiments, step a includes, applying a mask on the silicon wafer with multi-layer metal to be etched; placing the masked silicon wafer into the conductive layer etchant, and conducting a conductive layer in the mask window once Etching: put the silicon wafer whose conductive layer has been etched away into the barrier layer etchant, and etch the barrier layer in the mask window once.

In some embodiments, step c includes: placing the silicon wafer obtained in step b into the conductive layer etching solution, and performing secondary etching on the conductive layer in the mask window; In the barrier layer etching solution, secondary etching is performed on the barrier layer in the mask window.

In some embodiments, step a includes: applying a mask on the silicon wafer with multi-layer metal to be etched, and the mask window is the cutting edge of the single crystal; the masked silicon wafer is placed into a silicon wafer that can simultaneously etch the conductive layer and the barrier In the conductive layer-barrier layer etchant of the first layer, the conductive layer and the barrier layer in the mask window are etched once. As a result, corrosion steps are reduced, the process is simplified, and phenomena such as layer delamination and uneven metal edges are reduced.

In some embodiments, step c includes: putting the silicon wafer obtained in step b into the etching solution for conducting layer-barrier layer corrosion again, and performing secondary etching on the conducting layer and the barrier layer. Therefore, the corrosion steps are reduced, the process is simplified, and the phenomenon of metal delamination and uneven metal edges is reduced.

In some embodiments, the etching time in step c is shorter than the etching time in step a. The adhesive layer exposes one side more than the barrier layer and the conductive layer above, and at the same time, the barrier layer and the conductive layer will not be corroded excessively.

In some embodiments, in step b, an adhesion layer etching solution is used to etch the adhesion layer between the plurality of etched units.

In some embodiments, the etched silicon wafer is flushed with water after each etching. Remove residual corrosive liquid, prevent excessive corrosion of conductive layer and barrier layer, and eliminate the impact on the next processing step.

In some embodiments, step d is also included after step c: inspecting the silicon wafer processed in step c, it can be seen that the edge of the adhesive layer is exposed from under the conductive layer and the barrier layer, and it is judged that undercutting does not occur . From this, it can be judged whether the diode is qualified or not.

The invention overcomes the problem that undercutting is easy to occur when multilayer metals on the silicon chip are corroded. At the same time, it solves the problem that the underlying metal undercutting is not easy to be found.

Description of drawings

Fig. 1 is the structure schematic diagram after the multilayer metal corrosion of diode under the ideal state;

Fig. 2 is the schematic diagram of undercutting produced by the existing wet etching method;

FIG. 3 is a schematic diagram of the etched structure of the diode by the wet etching method of the present invention.

detailed description

The etching method of the present invention will be further described in detail below.

As shown in FIG. 1 , the multilayer metal structure on the front side of the silicon substrate 4 of the Schottky barrier diode is an adhesion layer 1 , a barrier layer 2 and a conductive layer 3 in sequence. The layer structure of the silicon wafer used to make the Schottky barrier diode is the same as that of the Schottky barrier diode.

Example 1

Step a:

Using a mask etching method, a mask is applied in a conventional manner on the silicon wafer with multilayer metal to be etched, and the position of the mask window is the cutting edge of a plurality of etched units;

Putting the masked silicon wafer into a conductive layer etchant capable of corroding the conductive layer 3, and once etching the conductive layer 3 in the mask window to form a plurality of etched units;

Flush the silicon wafer that has corroded the conductive layer with water;

Putting the flushed silicon wafer into the barrier layer etching solution capable of corroding the barrier layer 2, performing one corrosion on the barrier layer 2 in the mask window, and corroding the barrier layer 2 between multiple corroded units;

The silicon wafer from which the barrier layer 2 has been etched away is rinsed with water.

Step b:

Corroding the adhesion layer 1 between the plurality of corroded units with an adhesion layer corrosion solution capable of corroding the adhesion layer 1, so that the plurality of corroded units are completely separated;

Flush the silicon wafer that has corroded the adhesion layer 1 with water to remove the residual adhesion layer etching solution, prevent excessive corrosion of the adhesion layer 1 and eliminate the influence of the remaining adhesion layer etching solution on the next processing step.

stepc:

Put the silicon wafer obtained in step b into the conductive layer etching solution, and perform secondary etching on the conductive layer 3 in the mask window. In this step, the conductive layer etching solution is the same as the conductive layer etching solution in step a, and the etching time is shorter than the primary corrosion time of the conductive layer in step a; 3 The sum of the etching time of the secondary etching is equal to or greater than the etching time of the conductive layer 3 in the traditional method. According to the metal thickness of the conductive layer, determine the ratio of the two corrosion times. For example, when the metal thickness is large, the ratio of the first and second corrosion times can be selected as 8:2; when the metal thickness is small, the time ratio can be selected as 7: 3 etc.

Flush the silicon wafer that has undergone secondary corrosion of the conductive layer;

Place the silicon chip through the secondary corrosion of the conductive layer into the barrier layer etching solution, and carry out secondary corrosion to the barrier layer 2 in the mask window, so that the edge of the adhesion layer 1 of the etched unit is separated from the conductive layer 3 and the barrier layer. 2 exposed. The barrier layer etching solution in this step is the same as the barrier layer etching solution in step a, and the etching time is shorter than the primary corrosion time of the barrier layer in step a.

The sum of the etching time for the primary etching of the barrier layer 2 in step a and the etching time for the secondary etching of the barrier layer 2 in step c is equal to or greater than the etching time for the barrier layer 2 in the traditional method.

The silicon wafer that has been etched twice by the barrier layer is rinsed with water and shaken to dry.

Step d: Check the silicon wafer processed in step c under a microscope. As shown in FIG. 3 , if the edge 11 of the adhesive layer 1 is exposed from under the conductive layer and the barrier layer, it is judged that there is no undercutting. Under a microscope, the presence or absence of the edge 11 is used to determine whether the adhesive layer is undercut. The existence of the edge 11 indicates that undercutting does not occur, and the existence of the edge 11 will not affect the use of the product.

Example 2

Step a:

Using a mask etching method, a mask is applied on the silicon wafer with multi-layer metal to be etched, and the position of the mask window is the cutting edge of a plurality of etched units;

Put the masked silicon wafer into the conductive layer-barrier layer etching solution that can corrode the conductive layer 3 and the barrier layer 2 at the same time, and etch the conductive layer 3 and the barrier layer 2 in the mask window once to form multiple corroded layers. unit;

The silicon wafer which has been corroded once by the conductive layer and the barrier layer is flushed with water.

Step b:

The adhesion layer 1 between the multiple corroded units is etched with an adhesive layer etching solution capable of corroding the adhesive layer 1, so that the multiple corroded units are completely separated. The silicon wafer with the adhesion layer 1 etched off is rinsed with water.

Step c: Place the silicon wafer obtained in step b into the conductive layer-barrier layer etchant again, conduct secondary corrosion to the conductive layer 3 and the barrier layer 2, and make the edge of the adhesion layer 1 separate from the conductive layer 3 and the barrier layer 2, the diode shown in FIG. 3 is obtained, that is, the adhesive layer 1 exposes one more edge 11 than the upper conductive layer 3 and barrier layer 2. In this step, the conductive layer-barrier layer etching solution is the same as the conductive layer-barrier layer etching solution in step a, and the etching time is shorter than the etching time in step a, so that the edge of the adhesive layer 1 can be separated from the conductive layer 3 and the etching time in step a. The bottom of the barrier layer 2 is exposed, which is convenient for checking whether the product is qualified, and does not corrode the conductive layer 3 and the barrier layer 2 too much. Then rinse and shake dry.

Step d: Check the silicon wafer processed in step c under a microscope, and it can be seen that the edge 11 of the adhesive layer 1 is exposed from under the conductive layer 3 and the barrier layer 2, and it is judged that undercutting does not occur. Under a microscope, the presence or absence of the edge 11 is used to determine whether the adhesive layer is undercut. The existence of the edge 11 indicates that undercutting does not occur, and the existence of the edge 11 will not affect the use of the product.

In the above embodiments of the present invention, the total etching time combined with the secondary etching process needs to be designed as described above. The etching time of the first step is also different from that of the conventional etching method. For example: the conventional method is used for 7 minutes of etching; and after the method of the embodiment of the present invention is used, the first etching takes 5 minutes and the second etching takes 2 minutes. In the manufacturing process of Schottky barrier diodes in the prior art, there is no such simple secondary corrosion process in which the corroded edge exposes the underlying metal (referred to as metal back-floating in the present invention).

The most commonly used multilayer metal structure of Schottky barrier diodes is: the adhesion layer 1 is a Ti metal layer, the barrier layer 2 is a Ni metal layer, and the conductive layer 3 is an Ag metal layer. There are also some other commonly used metal structures, such as: Ti/Ni/AL, V/Ni/Ag, V/Ni/AL, etc.

Take the diode with Ti/Ni/Ag=2000/3000/30000 Angstroms as an example, the etching steps are the same as above, where:

The etching solution used in step a is a Ni-Ag etching solution, and the Ni-Ag etching solution is nitric acid and glacial acetic acid with a volume ratio of 1:2. Wherein, the corrosion time is 10 minutes. The volume ratio of nitric acid and glacial acetic acid in the Ni-Ag etching solution can be set between 1:2 and 1:3. The etching time can also be other values between 5 and 10 minutes.

The etching solution used in step b is a Ti etching solution, and the Ti etching solution is water and hydrofluoric acid with a volume ratio of 50:1. Corrosion time is 30 seconds. The etching time can also be a value between 30 and 60 seconds, which also depends on the thickness of the metal layer.

In step c, the same etching solution as in step a is used, and the etching time is 2 minutes. The etch time is shorter than the etch time in step a, and the edge of the Ni metal layer and the Ag metal layer can be corroded so that the edge of the Ti metal layer is exposed from the bottom of the Ni metal layer and the Ag metal layer without causing damage to the Ni metal layer and the Ag metal layer. Excessive corrosion of the metal layer. The etching time in this step can also be other values between 1 and 3 minutes.

The sum of the corrosion time of the primary corrosion of the conductive layer 3 and the barrier layer 2 in step a and the corrosion time of the secondary corrosion of the conductive layer 3 and the barrier layer 2 in the step c is equal to or greater than that of the conductive layer 3 and the barrier layer 2 in the traditional method corrosion time.

The flushing time in step a1, step b1 and step c1 is all 10 minutes.

When the multilayer metal on the diode is Ti/Ni/Al, V/Ni/Ag, V/Ni/Al and other structures, the corresponding corrosion solution can be used and the corrosion time can be set according to the thickness of each metal layer. Obtain the product of the structure shown in Figure 3.

What have been described above are only some embodiments of the present invention. For those skilled in the art, without departing from the inventive concept of the present invention, several modifications and improvements can be made, and these all belong to the protection scope of the present invention.

Claims (8)

1. Diode wet etching method, wherein, comprises the following steps: a. Corrosion of the conductive layer and the barrier layer to form multiple corroded units; b. corroding the adhesion layer between a plurality of corroded units; c, corroding the edge portion of the conductive layer and the edge portion of the barrier layer of the etched unit, so that the edge of the adhesion layer of the etched unit is exposed from under the conductive layer and the barrier layer; and d. Check the silicon wafer processed in step c. If it can be seen that the edge of the adhesive layer is exposed from under the conductive layer and the barrier layer, it is judged that there is no undercutting. 2. The diode wet etching method according to claim 1, wherein said step a comprises, Applying a mask on the silicon wafer with multiple layers of metal to be etched; Put the masked silicon wafer into the conductive layer etching solution to etch the conductive layer in the mask window once; Putting the silicon wafer from which the conductive layer has been etched away into the barrier layer etchant, and etching the barrier layer in the mask window once. 3. The diode wet etching method according to claim 2, wherein said step c comprises: placing the silicon wafer obtained in step b into the conductive layer etching solution, and performing secondary etching on the conductive layer in the mask window; Putting the silicon wafer which has undergone secondary etching of the conductive layer into the barrier layer etchant, and performing secondary etching on the barrier layer in the mask window. 4. The diode wet etching method according to claim 1, wherein step a comprises Applying a mask on the silicon wafer with multiple layers of metal to be etched; Putting the masked silicon wafer into the conductive layer-barrier layer etchant which can corrode the conductive layer and the barrier layer at the same time, the conductive layer and the barrier layer in the mask window are etched once. 5. The diode wet etching method according to claim 4, wherein step c comprises: placing the silicon wafer obtained in step b into the conductive layer-barrier layer etchant again, and performing two steps on the conductive layer and the barrier layer secondary corrosion. 6. The diode wet etching method according to claim 5, wherein the etching time in step c is shorter than the etching time in step a. 7. The diode wet etching method according to any one of claims 1-6, wherein, in the step b, an adhesion layer etching solution is used to etch the adhesion layer between the plurality of etched units. 8. The diode wet etching method according to claim 7, wherein after each etching, the etched silicon wafer is flushed with water.