CN103616814A - Synchronous sampling clock closed loop correcting method and system based on FPGA - Google Patents

Info

Publication number

CN103616814A

CN103616814A CN201310661429.0A CN201310661429A CN103616814A CN 103616814 A CN103616814 A CN 103616814A CN 201310661429 A CN201310661429 A CN 201310661429A CN 103616814 A CN103616814 A CN 103616814A

Authority

CN

China

Prior art keywords

pulse signal

pps

error

baund

heavily

Prior art date

2013-12-09

Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Granted

Links

• Espacenet
• Global Dossier
• Discuss

• 230000001360 synchronised effect Effects 0.000 title claims abstract description 50
• 238000005070 sampling Methods 0.000 title claims abstract description 31
• 238000000034 method Methods 0.000 title claims abstract description 28
• 239000013078 crystal Substances 0.000 claims abstract description 38
• 238000012937 correction Methods 0.000 claims abstract description 34
• 238000004364 calculation method Methods 0.000 claims abstract 3
• 238000013139 quantization Methods 0.000 claims description 9
• 230000000630 rising effect Effects 0.000 claims description 9
• 238000012545 processing Methods 0.000 claims description 5
• 230000001186 cumulative effect Effects 0.000 claims description 3
• 230000001915 proofreading effect Effects 0.000 claims description 2
• 230000032683 aging Effects 0.000 abstract description 2
• 238000010586 diagram Methods 0.000 description 6
• 230000004224 protection Effects 0.000 description 6
• 238000009825 accumulation Methods 0.000 description 3
• 238000013461 design Methods 0.000 description 3
• 238000005516 engineering process Methods 0.000 description 3
• 238000012986 modification Methods 0.000 description 3
• 230000004048 modification Effects 0.000 description 3
• 238000012360 testing method Methods 0.000 description 3
• 238000005259 measurement Methods 0.000 description 2
• 238000012544 monitoring process Methods 0.000 description 2
• 230000008569 process Effects 0.000 description 2
• 239000010453 quartz Substances 0.000 description 2
• VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
• 230000002159 abnormal effect Effects 0.000 description 1
• 238000004458 analytical method Methods 0.000 description 1
• 230000009286 beneficial effect Effects 0.000 description 1
• 238000004891 communication Methods 0.000 description 1
• 239000012141 concentrate Substances 0.000 description 1
• 230000007812 deficiency Effects 0.000 description 1
• 238000001514 detection method Methods 0.000 description 1
• 230000002045 lasting effect Effects 0.000 description 1
• 230000007774 longterm Effects 0.000 description 1
• 238000004519 manufacturing process Methods 0.000 description 1
• 230000006855 networking Effects 0.000 description 1
• 230000010355 oscillation Effects 0.000 description 1
• 238000004088 simulation Methods 0.000 description 1
• 230000009466 transformation Effects 0.000 description 1
• 230000007704 transition Effects 0.000 description 1

Abstract

本发明公开了一种基于FPGA的同步采样时钟闭环校正方法和系统。该方法首先采用了对PPS脉冲信号脉冲持续时间与相邻脉冲触发周期分别进行判断，来检测其脉冲信号的正确性；然后实时接收并检测PPS判断模块发送的动作信号，以作出相应的反应；接着通过误差校正模块对本地晶振时钟的频率进行校正并根据动作信号的状态对同步重采信号的相位误差进行测量和校正；最后通过倍频计算模块生成同步重采信号，同时将输出信号反馈给误差校正模块形成了一个闭环系统，并根据校正信息校正信息对输出自动进行调整。该方法解决了在研究基于GPS采样数据同步的基础上，合并单元同步采样时钟对晶振依赖性强，以致在晶振老化、频率准确度降低的情况下，输出误差较大的问题。

The invention discloses an FPGA-based method and system for closed-loop correction of a synchronous sampling clock. The method firstly judges the pulse duration of the PPS pulse signal and the adjacent pulse trigger period to detect the correctness of the pulse signal; then receives and detects the action signal sent by the PPS judgment module in real time to make a corresponding response; Then, the frequency of the local crystal oscillator clock is corrected by the error correction module, and the phase error of the synchronous reacquisition signal is measured and corrected according to the state of the action signal; finally, the synchronous reacquisition signal is generated by the frequency multiplication calculation module, and the output signal is fed back to the The error correction module forms a closed-loop system, and automatically adjusts the output according to the correction information. This method solves the problem that the synchronous sampling clock of the merging unit has a strong dependence on the crystal oscillator on the basis of the research on the synchronization of the sampling data based on GPS, so that the output error is relatively large when the crystal oscillator is aging and the frequency accuracy is reduced.

Description

A kind of closed-loop corrected method and system of synchronized sampling clock based on FPGA

Technical field

The invention belongs to electrical technology field, be specifically related to a kind of closed-loop corrected method of synchronized sampling clock based on FPGA.

Background technology

Intelligent substation is standardized as basic demand with the information digitalization of entirely standing, communications platform networking, information sharing; realize the functions such as information acquisition, measurement, control, protection, monitoring and metering; and station domain information real-time synchronization acquisition technique is the basis of realizing the various application functions of intelligent substation; it requires electronic mutual inductor to reach per second thousands of time to the data sampling of power network current and voltage, and in sampling just can be by a plurality of intelligent substations, each intelligent electronic device (IED) is shared.But no matter control, protect, or the computing of monitoring, measuring all requires sampled data at the same time, to gather, in order to avoid phase place and amplitude produce error.

For protections such as overcurrent protections, because the short-term stability of the local crystal oscillator clock of merging unit of electronic transformer is very high, can not impact the operation precision of protection.But for differential protection and metering; because the local crystal oscillator clock of merge cells is very inaccurate; through long error accumulation, can cause across the different phase errors of merge cells of compartment and the expansion gradually of amplitude error, cause the gross error of misoperation and the metering of differential protection.

Therefore, invent that a kind of performance is more superior, range of application more widely the closed-loop corrected new method of synchronized sampling clock become the problem of needing solution badly.

Summary of the invention

For the problems referred to above, the present invention proposes the design of synchronized sampling clock in a kind of merging unit of electronic transformer, be devoted to solve merge cells synchronized sampling clock strong to crystal oscillator dependence, aging at crystal oscillator, in the situation that frequency accuracy reduces, the deficiency that output error is larger.

For achieving the above object, the technical scheme that the present invention takes is:

In merging unit of electronic transformer, a design for synchronized sampling clock, comprises the steps:

1) by PPS judge module, PPS pulse signal duration of pulse and the adjacent pulse cycle of triggering are judged respectively, detect the correctness of its pulse signal;

2) by wrong processing module, receive in real time and detect the actuating signal that PPS judge module sends, to make corresponding reaction;

3) by error correction module, the frequency of local crystal oscillator clock is proofreaied and correct and heavily frequency error and the phase error of the number of accepting and believing are measured and proofreaied and correct to synchronous according to the state of actuating signal;

4) by frequency multiplication computing module, generate the synchronously heavily number of accepting and believing of 80 points/cycle, output signal is fed back to error correction module simultaneously and formed a closed-loop system, the control information of sending according to error correction module is adjusted exporting automatically.

In step 1, adopt PPS judge module to judge respectively PPS pulse signal duration of pulse and the adjacent pulse cycle of triggering, detect the correctness of pulse signal, after merge cells system starts, FPGA just starts constantly circulation and reads PPS pulse signal input pin signal, until detect, after pulse signal rising edge arrives, trigger two counters simultaneously and start counting, by local clock source, PPS pulse signal is detected.Then the judgement of carrying out two counter values judges the validity of pulse signal.

In step 3, adopt cumulative method to measure 4000 interval T of synchronously heavily adopting pulse signal _c, and guarantee T by frequency multiplication computing module _c=T _peven to have avoided in the maximized situation of Crystal Oscillator Errors, its two subsynchronous heavy number of accepting and believing interval error also only has 0.25Hz, be difficult to detected problem.

In step 4, adopted a kind of frequency-doubling method of realizing by totalizer, the reg that can define a bit wide W in FPGA deposits type totalizer Baund_acc and accumulated value variable Baund_inc.Totalizer Baund_acc capacity 2 ^wthe digital quantization value that represents synchronously heavily to adopt the signal period, accumulated value Baund_inc represents the digital quantization value in crystal oscillator cycle.Therefore have:

F _cry/F _res=2 ^w/Baund_inc

Consider

f _res=4000Hz, can try to achieve

$\mathrm{Baund}\_\mathrm{inc}=4000\·2^w/\stackrel{\‾}{M}$

When each arrives in crystal oscillator cycle, totalizer Baund_acc can add Baund_inc, carries out one-accumulate calculating, and to be dutycycle be 50% the synchronously heavily number of accepting and believing to the output of the most significant digit of totalizer.Zero moment output error that the method is the synchronous heavily number of accepting and believing of realization is proofreaied and correct and is needed maximum duration to be

t _s=F _cry/(500·F _res)=25s

After the access of PPS pulse signal, add the PPS judgement time of 3s, need at most 28s, can be completely achieved the synchronous output of the heavily number of accepting and believing.The method has overcome when local oscillator frequency deviation is larger, the error of the synchronous heavily number of accepting and believing is larger, can not realize the synchronous heavily uniformly-spaced output of the number of accepting and believing, the accuracy class of crystal oscillator is had relatively high expectations, and be unfavorable for zero problem that output error is proofreaied and correct constantly to the synchronous heavily number of accepting and believing.

With respect to prior art, beneficial effect of the present invention mainly contains: the method, when improving output accuracy, has reduced the impact of crystal oscillation frequency error on synchronized sampling clock, has saved production cost, has guaranteed the long-term stability operation of synchronized sampling clock.The method also can be applicable to the realization of synchronous clock in other IED equipment simultaneously, realizes the collection of information real-time synchronization lay a good foundation for intelligent substation.

Accompanying drawing explanation

Fig. 1 FB(flow block) of the present invention;

Fig. 2 PPS pulse input oscillogram;

Fig. 3 PPS pulse detection process flow diagram;

Fig. 4 error correction schematic diagram;

Fig. 5 frequency multiplication computing module operational flow diagram;

Fig. 6 synchronized sampling clock sequential analogous diagram;

Fig. 7 (a) experimental error angular difference test pattern;

Fig. 7 (b) experimental error ratio test pattern.

Embodiment

Below in conjunction with drawings and Examples, the invention will be further described.

As shown in Figure 1, in a kind of merging unit of electronic transformer, the design of synchronized sampling clock, comprises the steps:

1) PPS judgement.PPS pulse signal trigger characteristic as shown in Figure 2, when light intensity rise reach amplitude 50% time trigger constantly and arrive, its duration of pulse t _h>10 μ s, interpulse period t _i>500ms, adjacent pulse triggers period T _p=1s.Therefore can be by its duration of pulse and the adjacent pulse cycle of triggering be judged respectively, detect the correctness of PPS pulse signal, PPS judge module overhaul flow chart is as shown in Figure 3.

After merge cells system starts, FPGA just starts constantly circulation and reads PPS pulse signal input pin signal, until detect, after pulse signal rising edge arrives, trigger two counters simultaneously and start counting, by local clock source, PPS pulse signal is detected.Select herein precision be the common quartz crystal oscillator of 50MHz of 20ppm as local clock source, the actual vps of crystal oscillator is 5 * 10 ⁷between ± 1000.Start counter 1, local crystal oscillator vibration number in PPS pulse signal high level lasting time is carried out to accumulation calculating, as the count value N of negative edge arrival hour counter 1 ₁be latched, then carry out judgement 1, judgement N ₁whether be greater than 500, i.e. t _h>10 μ s.If but N ₁count down to 25 * 10 ⁶also at counting, i.e. t _h>500ms, stops counting automatically, carries out judgement 1 and makes mistakes.Start counter 2, local crystal oscillator vibration number in the PPS pulse signal adjacent pulse triggering cycle is carried out to accumulation calculating, the count value N of counter 2 after the arrival of next pulse signal rising edge being detected ₂be latched, then carry out judgement 2, judgement N ₂whether be greater than 4.9999 * 10 ⁷, i.e. T _p≈ 1s.If but N2 count down to 5.0001 * 10 ⁷also at counting, i.e. T _p>1s, stops counting automatically, carries out judgement 2 and makes mistakes.When judgement 1 or judge that 2 when make mistakes, automatically enter error handler, by all register zero clearings of PPS judge module, get back to the original state of waiting for PPS pulse signal rising edge.If judge, 1 can meet simultaneously and enter judgement 3 with judgement 2, need to think that PPS pulse signal is effective through continuous three correct judgments, output synchronous mark signal syn=1, and the while, no matter whether correct judgment was by the value zero clearing of counter 1 sum counter 2.

2) mistake is processed.Mistake processing module receives and detects the syn signal that PPS judge module sends in real time, if its value is 0, outwards send synchronous abnormal bright light alarm signal, synchronized sampling clock carries out asynchronous punctual output, until PPS pulse signal correctly accesses again and judgement in continuous three seconds is effective, syn signal value is 1, and wrong processing module is reset.

3) error correction.Error correction schematic diagram as shown in Figure 4.IEC61850-9-2LE standard-required merge cells sampling rate is 80 points/cycle or 256 points/cycle (50Hz), and the 80 points/cycle often using of take is herein example, requires synchronously the heavily number of accepting and believing output speed to be fixed as for 4000 point/seconds.Because the adjacent synchronous heavily time interval between the number of accepting and believing is very short, even therefore in the maximized situation of Crystal Oscillator Errors, its two subsynchronous heavy number of accepting and believing interval error also only has 0.25Hz, is difficult to detect.So can adopt accumulative, measure 4000 interval T of synchronously heavily adopting pulse signal _c, and guarantee T by frequency multiplication computing module _c=T _p.When error correction module detects syn signal value and is 1, after judging that in PPS judge module 2 conditions meet, to first three count value N in counter 2 ₂carry out mean value computation and obtain mean value

and the actual vibration frequency using it as crystal oscillator sends to frequency multiplication computing module to proofread and correct processing.When error correction module detects syn signal value and is 0, by losing, calculate before synchronous

value sends to frequency multiplication computing module, enters asynchronous punctual state.

When PPS pulse signal arrives, when rising edge triggers, error correction module starts timing.First of after this or this moment times frequency module output of definition simultaneously synchronously heavily the number of accepting and believing be No. 0, when No. 0 heavily the number of accepting and believing arrive after error correction module stop timing, measure PPS pulse signal and synchronize the heavily mistiming t between the number of accepting and believing with No. 0 ₀, i.e. t ₀crystal oscillator vibration number K in time, and send to frequency multiplication computing module to carry out correcting process K, the output that guarantees the synchronous heavily number of accepting and believing with this is without phase deviation.When error correction module detects syn signal value and is 0, by the zero clearing of K value, enter asynchronous punctual state.

4) frequency multiplication is calculated.Frequency multiplication computing module operational flow diagram as shown in Figure 5.

Because reg in FPGA deposits type variable, can freely define bit wide, the reg that therefore can define a bit wide W deposits type totalizer Baund_acc and accumulated value variable Baund_inc.Totalizer Baund_acc capacity 2 ^wthe digital quantization value that represents synchronously heavily to adopt the signal period, accumulated value Baund_inc represents the digital quantization value in crystal oscillator cycle.Therefore have

F _cry/F _res=2 ^w/Baund_inc （3）

Consider f _res=4000Hz, can try to achieve

$\mathrm{Baund}\_\mathrm{inc}=4000\·2^w/\stackrel{\‾}{M}---\left(4\right)$

When frequency multiplication computing module receives the crystal oscillator frequency corrected value that error correction module sends

after, can through type (4) round downwards and calculate accumulated value Baund_inc.Because totalizer Baund_acc is unsigned int, therefore can ignore it and overflow, constantly do cycle accumulor.When each arrives in crystal oscillator cycle, totalizer Baund_acc can add Baund_inc, carries out one-accumulate calculating, and to be dutycycle be 50% the synchronously heavily number of accepting and believing to the output of the most significant digit of totalizer.

Because Baund_inc rounds downwards when calculating, cause interior accumulator count value of a period of time less than normal, can in proofreading and correct, to count value, revise in zero moment output error to the synchronous heavily number of accepting and believing.When frequency multiplication computing module receive that error correction module sends zero constantly during output error value K, now the most significant digit of totalizer Baund_acc has just completed by 0 to 1 transformation, generates No. 0 heavily number of accepting and believing.Baund_inc is multiplied by K and obtains t _odigital quantization value Baund_err.Due to the attach most importance to time value of the number of accepting and believing lag output of Baund_err, therefore can be by accumulator count value Baund_acc be added to Baund_err carries out compensation of delay.Consider that the synchronous heavily adjustment of the number of accepting and believing need to realize a smooth transition, for preventing adjacent two heavy interval too small between the number of accepting and believing, cause program run-time error, need to be limited Baund_err, when K is greater than 500, Baund_err is 500Baund_inc.The zero output error correction constantly that realizes the synchronous heavily number of accepting and believing needs maximum duration to be

t _s=F _cry/(500·F _res)=25s （5）

After the access of PPS pulse signal, add the PPS judgement time of 3s, need at most 28s, can be completely achieved the synchronous output of the heavily number of accepting and believing.

Embodiment:

The error analysis of synchronized sampling clock:

While calculating due to Baund_inc in this synchronized sampling clock, round operation, can n synchronously heavily the number of accepting and believing locate to produce error:

${\mathrm{\ξ}}_2=|\frac{n}{F_{\mathrm{res}}}-\frac{n\·2^W}{\mathrm{Baund}\_\mathrm{inc}}\·\frac{1}{F_{\mathrm{cry}}}|---\left(6\right)$

When synchronous, the error correction of the counterweight per second number of accepting and believing once, so get maximal value 4000 and Baund_inc round-off error is 1 to the maximum as n, i.e. n=4000,

time, ξ ₂there is maximal value to be

${\mathrm{\ξ}}_{2\max }=\frac{\stackrel{\‾}{M}}{4000\·2^W-\stackrel{\‾}{M}}---\left(7\right)$

The synchronously heavy number of the accepting and believing output error ξ that is different from traditional frequency-doubling method in formula (2) ₁only be subject to the impact of crystal oscillator precision, from formula (7), maximum error ξ is exported in synchronously heavily accepting and believing of realizing by this paper method _2maxbe subject to the impact of crystal oscillator precision and totalizer bit wide W simultaneously.Therefore can be not high in crystal oscillator precision, crystal oscillator actual vibration frequency

when larger, strengthen bit wide W, reduce ξ _2max.For further studying and exist

get maximal value 5.0001 * 10 ⁷time, the different values of bit wide W are to ξ _2maxthe situation that affects, Baund_inc calculated value and round-off error number percent δ thereof are observed simultaneously, as shown in table 1.

Impact (M=5.0001 * 10 of table 1 bit wide W different value on error amount ⁷)

W	Baund_inc	δ(%)	ξ 2max(μs)
				32	343590	1.48977×10 -4	2.91045
40	87959171	4.39513×10 -8	1.1369×10 -2
				41	175918342	4.39513×10 -8	5.6845×10 -3
48	2.25175×10 10	3.98250×10 -9	4.4410×10 -5
				64	1.47571×10 15	1.34631×10 -14	6.7764×10 -10

By table 1, can find out, when bit wide W is larger, the calculated value that Baund_inc is corresponding is also larger, and the round-off error number percent δ that ignores fraction part generation when it calculates is also corresponding less, the ξ therefore causing corresponding to round-off error _2maxalso less.

The experimental study of synchronized sampling clock:

Utilize Quartus II to carry out programming simulation to synchronized sampling clock, as shown in Figure 6, wherein clk is local crystal oscillator clock input in its sequential emulation, and PPS_clk is the input of PPS pulse signal, resample_clk is the synchronously heavily number of accepting and believing output, and syn and K are internal register variable.When PPS judge module detects PPS pulse signal when effective, synchronous regime syn becomes 1, represents synchronous.Error correction module is heavily adopted pulse signal to No. 0 and is proofreaied and correct subsequently, obtains its output error value K, records the heavily number of accepting and believing lag output PPS pulse signal 17.12 μ s with timebar instrument simultaneously.Because K is 856, be greater than 500, so only compensated 500 when compensating for the first time, after next PPS pulse signal arrives, being again corrected to the output error of heavily adopting pulse signal is 356, and compensates.Finally synchronously heavily the number of accepting and believing is carved triggering at the same time with PPS pulse signal, and its output phase error value K is 0.

This synchronized sampling clock is downloaded in electronic current mutual inductor merge cells, adopt Jiangsu to insult wound NT702 electronic mutual inductor steady state check system and carried out operation test.Crystal oscillator is the common quartz crystal oscillator of 20ppm, and specified measurement electric current is 5A, and the synchronously sampled data error of the merge cells under different strength of current as shown in Figure 7.The ratio that can find out synchronously sampled data distributes and comparatively evenly to concentrate, and at electric current hour, because the burr of white noise disturbs, angular difference fluctuation is larger, but can meet generally the accuracy requirement of IEEE60044 standard 0.2S level, reflects good synchronism.

Those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.

Claims (8)

1. the closed-loop corrected method of synchronized sampling clock based on FPGA, is characterized in that: comprise the steps:

1) PPS determining step, judged respectively PPS pulse signal duration of pulse and the adjacent pulse cycle of triggering, and detected the correctness of its pulse signal;

2) mistake treatment step, receives and detects the actuating signal that PPS judge module sends, in real time to make corresponding reaction;

3) error correction step, proofreaies and correct and heavily frequency error and the phase error of the number of accepting and believing are measured and proofreaied and correct to synchronous according to the state of actuating signal the frequency of local crystal oscillator clock;

4) frequency multiplication calculation procedure, generates the synchronously heavily number of accepting and believing of 80 points/cycle, output signal is fed back to error correction step simultaneously and forms closed loop, according to the frequency error in error correction step and phase error, to exporting automatically, adjusts.

2. the closed-loop corrected method of synchronized sampling clock according to claim 1, it is characterized in that: in PPS determining step, adopt PPS judge module to judge respectively PPS pulse signal duration of pulse and the adjacent pulse cycle of triggering, detect the correctness of pulse signal, after merge cells system starts, FPGA just starts constantly circulation and reads PPS pulse signal input pin signal, until pulse signal rising edge detected, arrive, just trigger two counters simultaneously and start counting, by local clock source, PPS pulse signal is detected, then by the numerical value of two counters, judge the validity of pulse signal.

3. the closed-loop corrected method of synchronized sampling clock according to claim 1, is characterized in that: in error correction step, adopt cumulative method to measure a plurality of interval T of synchronously heavily adopting pulse signal _c, and guarantee T by frequency multiplication computing module _c=T _p, after thereby judge module is set up, try to achieve first three count value N in counter 2 ₂carry out mean value computation and obtain mean value in the hope of frequency error; PPS pulse signal arrives, when rising edge triggers, error correction module starts timing, first of after this or this moment times frequency module output synchronously heavily the number of accepting and believing arrive after error correction module stop timing, measure PPS pulse signal and synchronize the heavily mistiming t between the number of accepting and believing with No. 0 ₀, obtain t ₀in time, crystal oscillator vibration number K, to obtain phase error, carries out error correction by frequency error and phase error.

4. the closed-loop corrected method of synchronized sampling clock according to claim 1, it is characterized in that: in frequency multiplication calculation procedure, by totalizer, realize frequency multiplication, the reg that can define a bit wide W in FPGA deposits type totalizer Baund_acc and accumulated value variable Baund_inc, totalizer Baund_acc capacity 2w represents synchronously heavily to adopt the digital quantization value of signal period, accumulated value Baund_inc represents the digital quantization value in crystal oscillator cycle, so

F _cry/F _res=2 ^w/Baund_inc

When each arrives in crystal oscillator cycle, totalizer Baund_acc can add Baund_inc, carries out one-accumulate calculating, and to be dutycycle be 50% the synchronously heavily number of accepting and believing to the output of the most significant digit of totalizer.

5. the closed-loop corrected system of synchronized sampling clock based on FPGA, is characterized in that: comprise as lower module:

1) PPS judge module, for PPS pulse signal duration of pulse and the adjacent pulse cycle of triggering are judged respectively, detects the correctness of its pulse signal;

2) mistake processing module, the actuating signal sending for receiving in real time and detect PPS judge module, to make corresponding reaction;

3) error correction module, for proofreading and correct the frequency of local crystal oscillator clock and heavily frequency error and the phase error of the number of accepting and believing are measured and proofreaied and correct to synchronous according to the state of actuating signal;

4) frequency multiplication computing module, for generating the synchronously heavily number of accepting and believing of 80 points/cycle, feeds back to output signal error correction module simultaneously and forms closed-loop system, and the frequency error and the phase error that according to error correction module, send are adjusted exporting automatically.

6. the closed-loop corrected system of synchronized sampling clock according to claim 1, it is characterized in that: PPS judge module, be used for adopting PPS judge module to judge respectively PPS pulse signal duration of pulse and the adjacent pulse cycle of triggering, detect the correctness of pulse signal, after merge cells system starts, FPGA just starts constantly circulation and reads PPS pulse signal input pin signal, until pulse signal rising edge detected, arrive, just trigger two counters simultaneously and start counting, by local clock source, PPS pulse signal is detected, then by the numerical value of two counters, judge the validity of pulse signal.

7. the closed-loop corrected method of synchronized sampling clock according to claim 1, is characterized in that: error correction module, and for adopting cumulative method to measure a plurality of interval T of synchronously heavily adopting pulse signal _c, and guarantee T by frequency multiplication computing module _c=T _p, after thereby judge module is set up, try to achieve first three count value N in counter 2 ₂carry out mean value computation and obtain mean value

in the hope of frequency error; PPS pulse signal arrives, when rising edge triggers, error correction module starts timing, first of after this or this moment times frequency module output synchronously heavily the number of accepting and believing arrive after error correction module stop timing, measure PPS pulse signal and synchronize the heavily mistiming t between the number of accepting and believing with No. 0 ₀, obtain t ₀in time, crystal oscillator vibration number K, to obtain phase error, carries out error correction by frequency error and phase error.

8. the closed-loop corrected method of synchronized sampling clock according to claim 1, it is characterized in that: frequency multiplication computing module, for realizing frequency multiplication by totalizer, the reg that can define a bit wide W in FPGA deposits type totalizer Baund_acc and accumulated value variable Baund_inc, totalizer Baund_acc capacity 2 ^wthe digital quantization value that represents synchronously heavily to adopt the signal period, accumulated value Baund_inc represents the digital quantization value in crystal oscillator cycle, so

F _cry/F _res=2 ^w/Baund_inc

When each arrives in crystal oscillator cycle, totalizer Baund_acc can add Baund_inc, carries out one-accumulate calculating, and to be dutycycle be 50% the synchronously heavily number of accepting and believing to the output of the most significant digit of totalizer.

Cited By (40)