CN103607546A - Asynchronous CMOS pixel circuit with light adaptive threshold voltage adjustment mechanism - Google Patents
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Abstract
The invention relates to a digital-analog hybrid integrated circuit design field and provides an asynchronous CMOS pixel circuit with a light adaptive threshold voltage adjustment mechanism. The objectives of the invention are to maintain the advantages of high dynamic range and low fixed-model noise of a circuit, and compress time for measuring light intensity in a relatively small range, and improve the response speed of the circuit. In order to achieve the above objectives, the following technical schemes are adopted: the asynchronous CMOS pixel circuit with the light adaptive threshold voltage adjustment mechanism is composed of a light intensity change detection unit (CD), an exposure measurement unit (EM) using a PWM mode and a VrefL reference voltage switching unit; and output signals Rst of the output end R of the change detection unit are connected with the input end Reset of the exposure measurement unit and the input end T1 of the VrefL reference voltage switching unit and are respectively used for controlling signals of measurement initiating of the exposure measurement unit and controlling the evaluation of light intensity. The asynchronous CMOS pixel circuit with the light adaptive threshold voltage adjustment mechanism of the invention is mainly applied to the digital-analog hybrid integrated circuit design.
Description
Technical field
The present invention relates to hybrid digital-analog integrated circuit design field, particularly there is the asynchronous cmos pixel circuit of light adaptive threshold voltage-regulation mechanism.
Technical background
Asynchronous cmos image sensor is a kind of brand-new imageing sensor, it has abandoned the concept based on frame in conventional image sensor, the substitute is and utilize AER(address events to represent) communication mode, realization changes and produces event, by event, represent optical information, thereby realize asynchronous autonomous pixel, can overcome so the many shortcoming and defect under frame pattern.
In asynchronous cmos image sensor, mostly adopted to be different from and based on voltage, represented the mode of light intensity in conventional image sensor, but adopted the mode based on time representation light intensity, from pixel resets, not to fix its discharge time to survey end voltage, but set the time that reference voltage measurement reaches set threshold voltage, its major advantage is the detectable dynamic range of raising pixel that can be larger.In order to eliminate fixed pattern noise, people have proposed a kind of twice comparison with reference voltage of carrying out in a discharge cycle, represent light intensity with this time difference of two, and the basic structure of its pixel is as shown in figure mono-.
Yet being applied to by this way have another problem in asynchronous cmos pixel is exactly the reference voltage for two fixing comparators of setting, under different light intensity conditions, the time that measurement needs has very large difference.Because asynchronous pixel is to adopt the sign that changes and measure for starting, if two reference voltage differences that arrange are larger, so, under the condition of low light level photograph, the time that there will be Measuring Time to be longer than to change, just there will be and cannot measure current intensity signal; If two reference voltage differences that arrange are less, so, under the condition of intense light irradiation, there will be Measuring Time very short, thereby affected the precision of digital quantization intensity signal.A kind of method addressing this problem is that larger reference voltage difference is set, and under weak illumination condition, only gets the time that reaches first threshold value to represent light intensity, and the cost of doing is like this to have introduced larger fixed pattern noise.
Summary of the invention
For overcoming the deficiencies in the prior art, the present invention is intended to realize holding circuit high dynamic range, the advantage of low fixed pattern noise, the time of measuring light intensity is compressed in some relatively little intervals simultaneously, improve the response speed of circuit, for achieving the above object, the technical solution used in the present invention is, the asynchronous cmos pixel circuit with light adaptive threshold voltage-regulation mechanism, by light intensity change detection unit (CD), adopt exposure measuring unit (EM) and a VrefL reference voltage switch unit of PWM pattern to form, the output signal Rst of the output R of change detection unit is connected to the exposure input Reset of measuring unit and the input T1 of VrefL reference voltage switch unit, being used separately as control exposure measuring unit starts the signal of measuring and controls evaluation intensity of illumination, the VrefL reference voltage VL1 of two inputs setting and input VrefL1 and the VrefL2 that VL2 is connected respectively to VrefL reference voltage switch unit, VrefL reference voltage switch unit selects suitable VrefL by port Vsel output VL signal according to the relation of T1 and T2 signal, and output port Vsel is connected with the input VrefL of exposure measuring unit, the output signal S of the output Sign of VrefL switch unit outputs to pixel outside, as the sign bit of the low reference voltage of current selection, externally exports, the high reference voltage VH setting is connected to the input VrefH of exposure measuring unit, the external output of exposure measuring unit has RR, RL and RH, wherein the output signal RowReq of RR end exports outer row moderator on the one hand, be connected with the input T2 of VrefL voltage switch unit in pixel on the other hand, for switch unit, intensity of illumination evaluated, the output signal ColReqH of output RH, RL and ColReqL output to outside row moderator, the confirmation signal RowAck returning from row moderator is connected to the input RA of exposure measuring unit, and the confirmation signal ColAckH returning from row moderator and ColAckL are connected respectively to input AH and the AL of exposure measuring unit.
The structure of VrefL voltage switch unit, by the d type flip flop that postpones inverter, three general inverters, two switches and a rising edge triggering, formed, nmos type transistor M1, pmos type transistor, capacitor C 1 form and postpone inverter, postpone inverter the pulse duration of T1 signal is carried out to broadening, the width of broadening depends on size and the transistor pmos type transistor breadth length ratio of capacitor C 1, the grid of nmos type transistor connects T1 signal, the source ground of nmos type transistor, the transistorized grid of pmos type meets bias voltage V1, the transistorized source electrode of pmos type meets power vd D, the source electrode of the transistorized drain electrode of pmos type and nmos type transistor is connected together, the top crown of capacitor C 1 meets power vd D, the bottom crown of capacitor C 1 is connected on the transistorized drain electrode of pmos type, the transistorized output of pmos type connects the input of inverter 1, the output of inverter INV1 meets the input D of d type flip flop, the input end of clock of d type flip flop connects T2 signal, the RSTB port of d type flip flop connects T1 signal, when signal T1 is high level, output Q is low level, the output Q of d type flip flop connects the input of inverter INV2, the input of the output termination inverter INV3 of INV2, and the output of INV3 is flag bit Sign signal, one termination VrefL1 of cmos switch, the other end of cmos switch and one end of another switch link together, as the output port of signal Vsel, another termination VrefL2 of another switch, in the grid of the nmos pass transistor in cmos switch and another switch, the transistorized grid of PMOS connects Sign signal, in the transistorized grid of PMOS in cmos switch and another switch, the grid of nmos pass transistor connects the output port of inverter INV2, and capacitor C 1 and C2 are the effects of playing delay, T1 is reset signal, and high level is effective, T2 is control signal, and rising edge is effective.
For the common processes of 180nm, VrefL1 span is 0.4-0.8V, and optimum voltage is 0.6V; VrefL2 span is 1.1-1.5V, and optimum voltage is 1.3V.
The present invention possesses following technique effect:
The present invention by increasing the adaptively selected structure of comparative voltage in pixel, make each pixel automatically to select most suitable comparative voltage Δ V according to local light intensity, thereby make under different light intensity conditions, each pixel completes the time of exposure and automatically adjusts, to improve certainty of measurement, to shorten the response time.
Accompanying drawing explanation
The existing asynchronous dot structure of Fig. 1.
Fig. 2 increases the dot structure of VrefL voltage switch unit.
The circuit structure of Fig. 3 VrefL voltage switch unit.
Embodiment
Object of the present invention is introduced the circuit of the lower reference voltage mechanism of a kind of automatic adjusting in pixel, and can produce corresponding coded message and offer back-end processing circuit marking-threshold information, to realize the advantage that keeps primary circuit high dynamic range, low fixed pattern noise, the time of measuring light intensity is compressed in some relatively little intervals simultaneously, improves the response speed of circuit.
A kind of asynchronous cmos pixel with light adaptive threshold voltage-regulation mechanism comprises following three parts: a light intensity change detection unit (CD), exposure measuring unit (EM) and a VrefL reference voltage switch unit that adopts PWM pattern.As shown in Figure 2, in a pixel, the output signal Rst of the output R of change detection unit is connected to the exposure input Reset of measuring unit and the input T1 of VrefL reference voltage switch unit, is used separately as control exposure measuring unit and starts the signal of measuring and control evaluation intensity of illumination.The VrefL reference voltage VL1 of two inputs setting and input VrefL1 and the VrefL2 that VL2 is connected respectively to VrefL voltage switch unit; VrefL voltage switch control unit can select suitable VrefL by port Vsel output VL signal according to the relation of T1 and T2 signal, and output port Vsel is connected with the input VrefL of exposure measuring unit; The output signal S of the output Sign of VrefL switch unit outputs to pixel outside, as the sign bit of the low reference voltage of current selection, externally exports.The high reference voltage VH setting is connected to the input VrefH of exposure measuring unit; The external output of exposure measuring unit has RR, RL and RH, wherein the output signal RowReq of RR end exports outer row moderator on the one hand, be connected with the input T2 of VrefL voltage switch unit in pixel on the other hand, for switch unit, intensity of illumination evaluated; The output signal ColReqH of output RH, RL and ColReqL output to outside row moderator; The confirmation signal RowAck returning from row moderator is connected to the input RA of exposure measuring unit, and the confirmation signal ColAckH returning from row moderator and ColAckL are connected respectively to input AH and the AL of exposure measuring unit.
Figure tri-is depicted as the structure of VrefL voltage switch unit, and it has the inverter of delay feature, three general inverters, two switches and a d type flip flop that rising edge triggers by one.Nmos type transistor M1, pmos type transistor, capacitor C 1 form an inverter with delay feature, are called delay inverter.Postpone inverter major function the pulse duration of T1 signal is carried out to broadening, the width of broadening depends primarily on size and the M2 transistor breadth length ratio of C1 electric capacity.The grid of M1 connects T1 signal, the source ground of M1, and the grid of M2 meets bias voltage V1, and the source electrode of M2 meets power vd D, and the drain electrode of M2 and the source electrode of M1 are connected together, and the top crown of capacitor C 1 meets power vd D, and the bottom crown of capacitor C 1 is connected on the drain electrode of M2.The output of M2 connects the input of inverter 1, and the output of inverter INV1 meets the input D of d type flip flop.The input end of clock of d type flip flop connects T2 signal.The RSTB port of d type flip flop connects T1 signal, and when signal T1 is high level, output Q is low level.The output Q of d type flip flop connects the input of inverter INV2, the input of the output termination inverter INV3 of INV2, and the output of INV3 is flag bit Sign signal.A termination VrefL1 of cmos switch K1, the other end of cmos switch K1 and one end of K2 link together, as the output port of signal Vsel; Another termination VrefL2 of K2 switch.In the grid of the nmos pass transistor in K1 switch and K2 switch, the transistorized grid of PMOS connects Sign signal, and in the transistorized grid of PMOS in K1 switch and K2 switch, the grid of nmos pass transistor connects the output port of inverter INV2.Capacitor C 1 and C2 are the effects of playing delay.T1 is reset signal, and high level is effective; T2 is control signal, and rising edge is effective.
T1 is between high period, and the output of d type flip flop is reset to low level, and output signal Sign is low level, and Vsel equals VrefL2; When the width between T1 and T2 signal pulse is greater than the pulse duration of inverter INV1 output, during T2 rising edge, INV1 is output as low level, and output Q is low level, and Sign is low level, and Vsel equals VrefL2.When the width between T1 and T2 signal pulse is less than the pulse duration of inverter INV1 output, during T2 rising edge, T1 is high level, and output Q is high level, and Sign is high level, and Vsel equals VrefL1.
For different pixels array sizes and control circuit, the time difference between two rising edge of a pulses between T1 and T2 may be different.In order to increase the dynamic range of pixel, VrefL1 is as much as possible little, and for the common processes of 180nm, VrefL1 is generally 0.5V.VrefL2 is larger than VrefL1, and for circuit is all worked normally under the low light level and high light environment, it is proper that VrefL2 generally gets 1.0V.
Claims (3)
1. an asynchronous cmos pixel circuit with light adaptive threshold voltage-regulation mechanism, it is characterized in that, by light intensity change detection unit (CD), the exposure measuring unit (EM) that adopts PWM pattern and a VrefL reference voltage switch unit formation, the output signal Rst of the output R of change detection unit is connected to the exposure input Reset of measuring unit and the input T1 of VrefL reference voltage switch unit, is used separately as control exposure measuring unit and starts the signal of measuring and control evaluation intensity of illumination; The VrefL reference voltage VL1 of two inputs setting and input VrefL1 and the VrefL2 that VL2 is connected respectively to VrefL reference voltage switch unit; VrefL reference voltage switch unit selects suitable VrefL by port Vsel output VL signal according to the relation of T1 and T2 signal, and output port Vsel is connected with the input VrefL of exposure measuring unit; The output signal S of the output Sign of VrefL switch unit outputs to pixel outside, as the sign bit of the low reference voltage of current selection, externally exports; The high reference voltage VH setting is connected to the input VrefH of exposure measuring unit; The external output of exposure measuring unit has RR, RL and RH, wherein the output signal RowReq of RR end exports outer row moderator on the one hand, be connected with the input T2 of VrefL voltage switch unit in pixel on the other hand, for switch unit, intensity of illumination evaluated; The output signal ColReqH of output RH, RL and ColReqL output to outside row moderator; The confirmation signal RowAck returning from row moderator is connected to the input RA of exposure measuring unit, and the confirmation signal ColAckH returning from row moderator and ColAckL are connected respectively to input AH and the AL of exposure measuring unit.
2. the asynchronous cmos pixel circuit with light adaptive threshold voltage-regulation mechanism as claimed in claim 1, it is characterized in that, the structure of VrefL voltage switch unit, by the d type flip flop that postpones inverter, three general inverters, two switches and a rising edge triggering, formed, nmos type transistor M1, pmos type transistor, capacitor C 1 form and postpone inverter, postpone inverter the pulse duration of T1 signal is carried out to broadening, the width of broadening depends on size and the transistor pmos type transistor breadth length ratio of capacitor C 1, the grid of nmos type transistor connects T1 signal, the source ground of nmos type transistor, the transistorized grid of pmos type meets bias voltage V1, the transistorized source electrode of pmos type meets power vd D, the source electrode of the transistorized drain electrode of pmos type and nmos type transistor is connected together, the top crown of capacitor C 1 meets power vd D, the bottom crown of capacitor C 1 is connected on the transistorized drain electrode of pmos type, the transistorized output of pmos type connects the input of inverter 1, the output of inverter INV1 meets the input D of d type flip flop, the input end of clock of d type flip flop connects T2 signal, the RSTB port of d type flip flop connects T1 signal, when signal T1 is high level, output Q is low level, the output Q of d type flip flop connects the input of inverter INV2, the input of the output termination inverter INV3 of INV2, and the output of INV3 is flag bit Sign signal, one termination VrefL1 of cmos switch, the other end of cmos switch and one end of another switch link together, as the output port of signal Vsel, another termination VrefL2 of another switch switch, in the grid of the nmos pass transistor in cmos switch and another switch, the transistorized grid of PMOS connects Sign signal, in the transistorized grid of PMOS in cmos switch and another switch, the grid of nmos pass transistor connects the output port of inverter INV2, and capacitor C 1 and C2 are the effects of playing delay, T1 is reset signal, and high level is effective, T2 is control signal, and rising edge is effective.
3. the asynchronous cmos pixel circuit with light adaptive threshold voltage-regulation mechanism as claimed in claim 1, is characterized in that, for the common processes of 180nm, VrefL1 is 0.5V; VrefL2 gets 1.0V.
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Cited By (11)
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| CN105163048A (en) * | 2015-09-11 | 2015-12-16 | 天津大学 | Dynamic vision sensor based on amplifier multiplexing |
| CN106375685A (en) * | 2016-10-26 | 2017-02-01 | 中国科学院上海高等研究院 | A pulse width modulation pixel exposure method and pixel structure |
| CN109274375A (en) * | 2018-09-05 | 2019-01-25 | 东南大学 | Voltage-controlled delay unit and high-precision time-to-digital converter |
| CN110505417A (en) * | 2019-06-28 | 2019-11-26 | 西安理工大学 | Adaptive conversion gain system and method for CMOS image sensor |
| CN111641403A (en) * | 2020-06-15 | 2020-09-08 | 南开大学深圳研究院 | D trigger structure with asynchronous set reset and rapid output |
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