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CN103606556A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN103606556A
CN103606556A CN201310504608.3A CN201310504608A CN103606556A CN 103606556 A CN103606556 A CN 103606556A CN 201310504608 A CN201310504608 A CN 201310504608A CN 103606556 A CN103606556 A CN 103606556A
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China
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type
region
conductivity type
semiconductor device
substrate
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CN201310504608.3A
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Chinese (zh)
Inventor
丛国芳
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LIYANG DONGDA TECHNOLOGY TRANSFER CENTER Co Ltd
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LIYANG DONGDA TECHNOLOGY TRANSFER CENTER Co Ltd
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Priority to CN201310504608.3A priority Critical patent/CN103606556A/en
Publication of CN103606556A publication Critical patent/CN103606556A/en
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177Base regions of bipolar transistors, e.g. BJTs or IGBTs
    • H10D62/184Base regions of bipolar transistors, e.g. BJTs or IGBTs of lateral BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00Bipolar junction transistors [BJT]
    • H10D10/60Lateral BJTs

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Abstract

The invention discloses a semiconductor device comprising a first conductivity type substrate, a second conductivity type epitaxial layer used as a base region, a second conductivity type buried diffusion layer, a second conductivity type diffusion layer used as a base lead-out region, a first conductivity type diffusion layer used as an emitter region and a first conductivity type diffusion layer used as a collector region. The semiconductor device is characterized in that tungsten is diffused in the second conductivity type epitaxial layer used as the base region. The structure enables holes injected from an emitter and a plurality of carriers (namely, electrons) existing in the base region to be recombined by making use of high energy level of tungsten so that the current amplification rate of the semiconductor device can be improved and pollution can be reduced.

Description

Semiconductor device
Technical field
The present invention relates to a kind of semiconductor device.
Background technology
In prior art, the transistorized structure of a kind of horizontal type PNP for being formed with the N-type epi region of low concentration on P type semiconductor substrate.Across P type semiconductor substrate and N-type epi region, be formed with N-type impurity and imbed region.In epi region, be formed with the first N-type extrinsic region.The concentration of the concentration ratio N-type epi region of the first N-type extrinsic region is high 2~3 times.And, at the first N-type extrinsic region, be formed with the second N-type extrinsic region as base region, as the first p type impurity region of emitter region and as the second p type impurity region of collector region.
Another kind of common horizontal type PNP transistor arrangement for being formed with N-type epitaxial loayer on P type semiconductor substrate.Across P type semiconductor substrate and N-type epitaxial loayer, be formed with N-type and imbed diffusion layer.On N-type epitaxial loayer, be formed with n type diffused layer as base region, as the p type diffused layer of emitter region and as the p type diffused layer of collector region.And, the circular formation of surrounding as the p type diffused layer of collector region at the p type diffused layer as emitter region.
In prior art, the transistorized manufacture method of PNP comprises: prepare P type silicon monocrystalline substrate, form heat oxide film on substrate.Heat oxide film is carried out to composition, form peristome being formed with in the district of n type diffused layer.And coating contains boron (B) and as the two liquid source electrode of the platinum (Pt) of life-span inhibitor, forms diffuse source film on substrate.By in non-oxidized gas medium apply the heat treatment of 1000~1050 ℃, boron (B) and platinum (Pt) from diffuse source film to substrate spread thereafter.Owing to using platinum, the problem of existence has been to improve the resistivity value that spreads the region that has N-type impurity.
In addition, in the transistorized manufacture method of existing PNP, on N-type epitaxial loayer, as p type diffused layer circular formation around the p type diffused layer as emitter region of collector region.Utilize this structure, can effectively configure the p type diffused layer as collector region to the p type diffused layer as emitter region.That is,, by making the narrowed width of base region, can improve the transistorized current amplification degree of horizontal type PNP.On the contrary, by the N-type epitaxial loayer of low impurity concentration is used as base region, the transistorized current amplification degree of horizontal type PNP is raised too high in the situation that, can adapt to by expanding the width (spacing distance between emitter-collector region) of base region.Problem in this situation is, the transistorized device size of horizontal type PNP will become large.
Summary of the invention
The present invention forms in view of described variety of issue, a kind of semiconductor device is provided, it has Semiconductor substrate and is formed at emitter region, base region, the collector region in described Semiconductor substrate, in the semiconductor layer using as described base region, spreads tungsten.Therefore, in the present invention, can utilize the tungsten being diffused on semiconductor layer to adjust base current value, not need to increase device size and just can realize the current amplification degree of expectation.
Semiconductor device of the present invention comprises the first conduction type diffusion layer that the substrate of the first conduction type, the second conductive type epitaxial layer, the second conduction type that use as base region are imbedded diffusion layer, drawn the second conduction type diffusion layer using in region, the first conduction type diffusion layer using as emitter region, use as collector region as base stage; It is characterized in that, in described the second conductive type epitaxial layer using as base region, diffusion has tungsten.
Preferably, described substrate is single crystalline substrate; More preferably, described substrate is monocrystalline substrate.
Preferably, described transistor also comprises the insulating barrier being formed on base region; More preferably, described insulating barrier is PGS film.
Preferably, described transistor also comprises collector electrode, emitter and base stage; More preferably, described collector electrode, emitter and base stage form with aluminium alloy; Described aluminium alloy is preferably Al-Si.
In the present invention, at the base region diffusion tungsten of semiconductor device.Compare platinum or molybdenum, it is electronics combination again with the many charge carriers that are present in base region that the high level of tungsten makes from emitter injected holes, thereby can improve the transistorized current amplification degree of horizontal type PNP; Can reduce because of the metallic pollution on the production line forming semiconductor device simultaneously.
Accompanying drawing explanation
Fig. 1 is the section of structure of semiconductor device of the present invention.
Fig. 2~7 are structural representation in the manufacture method of semiconductor device of the present invention.
Embodiment
Below, the semiconductor device describing in detail as one of the present invention embodiment with reference to accompanying drawing 1, Fig. 1 is for the profile of the semiconductor device of one embodiment of the invention is described.
As shown in Figure 1, horizontal type PNP transistor 1 mainly by p type single crystal silicon substrate 3, N-type epitaxial loayer 4, the N-type as base region, used imbed diffusion layer 5, as base stage draw the n type diffused layer 6 using in region, the p type diffused layer 7 using as emitter region, the p type diffused layer 8,9 that uses as collector region forms.
N-type epitaxial loayer 4 is formed on p type single crystal silicon substrate 3.In addition, in the present embodiment, be illustrated in the situation that forms one deck epitaxial loayer 4 on substrate 3, but be not only confined to this situation.Can be also for example the situation of only having substrate, can be also the situation that is laminated with epitaxial layer on substrate.In addition, substrate can be also N-type mono-crystalline substrate.
N-type is imbedded diffusion layer 5 across on substrate 3 and epitaxial loayer 4 and form.And N-type is imbedded diffusion layer 5 and is formed across the formation region of horizontal type PNP transistor 1.
N type diffused layer 6 is formed on epitaxial loayer 4.And N-type epitaxial loayer 4 is used as base region, n type diffused layer 6 is drawn region as base stage and is used.
P type diffused layer 7 is formed on epitaxial loayer 4.And p type diffused layer 7 is used as emitter region.
P type diffused layer 8,9 is formed on epitaxial loayer 4.And p type diffused layer 8,9 is used as collector region.In addition, p type diffused layer 8,9 can be also the situation in surrounding's one ring-type formation of p type diffused layer 7.
Insulating barrier 10 is formed at above epitaxial loayer 4.Insulating barrier 10 is by formations such as PGS (Phospho SilicateGlass) films.Then, use known lithography technology, for example, by having used CHF 3+ O2 is that the dry-etching of gas forms contact hole 11,12,13,14 on insulating barrier 10.
In contact hole 11,12,13,14, optionally form for example Al-Si film of aluminium alloy, form collector electrode 15,17, emitter 16 and base stage 18.
After at length the manufacture method of semiconductor device is described, on the epitaxial loayer 4 as base region of horizontal type PNP transistor 1 and substrate 3, spread tungsten.And, in horizontal type PNP transistor 1, from the p type diffused layer 7 as emitter, be injected into and as the hole of the epitaxial loayer 4 of base region, using epitaxial loayer 4 near surfaces that base width (Wb) becomes the narrowest and flow to the p type diffused layer 8,9 as collector region as path.Now, hole is minority carrier in N-type epitaxial loayer 4, because the existence of the tungsten in epitaxial loayer 4 is easily combined with electronics again.That is, the life-span in hole reduces in conjunction with facilitation because of tungsten again, thereby the current amplification degree of horizontal type PNP transistor 1 reduces.
Particularly, the current amplification degree of horizontal type PNP transistor 1 reduces according to the diffusing capacity of epitaxial loayer 4 interior tungsten.In addition, Fig. 2 represents the mean value (X) of horizontal type PNP transistor 1 emitter current (Ie) current amplification degree when 10 (μ A).
In the situation that not making tungsten in epitaxial loayer 4 interior diffusion, the mean value of the current amplification degree of horizontal type PNP transistor 1 (X) is 273.On the other hand, in the situation that working concentration is the aqueous solution (with reference to the explanation of Fig. 7) of the tungsten of 0.1 (ppm), the mean value of the current amplification degree of horizontal type PNP transistor 1 (X) is 236.In addition, in the situation that working concentration is the aqueous solution (with reference to the explanation of Fig. 7) of the tungsten of 1.0 (ppm), the mean value of the current amplification degree of horizontal type PNP transistor 1 (X) is 201.In addition, in the situation that working concentration is the aqueous solution (with reference to the explanation of Fig. 7) of the tungsten of 10.0 (ppm), the mean value of the current amplification degree of horizontal type PNP transistor 1 (X) is 188.And in the situation that working concentration is the aqueous solution (with reference to the explanation of Fig. 7) of the tungsten of 100.0 (ppm), the mean value of the current amplification degree of horizontal type PNP transistor 1 (X) is 151.That is, the diffusing capacity of the tungsten in epitaxial loayer 4 is more, and the current amplification degree of horizontal type PNP transistor 1 is just lower.
In addition, on substrate 3, be formed with various semiconductor elements, but because tungsten does not impact the element characteristic of other semiconductor element, so the concentration of the tungsten aqueous solution can determine according to the characteristic of the current amplification degree of horizontal type PNP transistor 1.The in the situation that of particularly both having made in tungsten is diffused into substrate 3 or diffusion layer 4, can not make resistivity value increase yet, can not make the connection resistance value of horizontal type PNP transistor 1 and other semiconductor element increase.
In addition, the standard deviation rate (σ/X) of the current amplification degree of horizontal type PNP transistor 1 reduces according to the diffusing capacity of epitaxial loayer 4 interior tungsten.
As mentioned above, in horizontal type PNP transistor 1, by utilizing and the tungsten facilitation of combination again, can reduce the life-span in hole, reduce current amplification degree, obtain the current amplification degree of expecting.Use tungsten of the present invention than available technology adopting molybdenum, more easily to promote the combination of hole and electronics.Now, owing to not improving the impurity concentration of N-type epitaxial loayer 4, so can prevent the deterioration of horizontal type PNP transistor 1 voltage endurance.In addition, owing to need not expanding the base width (spacing between emitter-collector region) of horizontal type PNP transistor 1, just can reduce current amplification degree, so can prevent the increase of the device size of horizontal type PNP transistor 1.
Describe the manufacture method of the semiconductor device of one embodiment of the invention below in detail.
First, as shown in Figure 2, prepare p type single crystal silicon substrate 3.Thermal oxidation is carried out in substrate 3 surfaces, on substrate 3 surfaces, form silicon oxide film 31.The form that forms peristome to imbed in N-type on the formation region of diffusion layer 5,19 is removed silicon oxide film 31 selectively.Then, use silicon oxide film 31 as mask, with spin-coating method, will be coated in the surface of substrate 3 as the liquid source electrode 32 of antimony (Sb) containing N-type impurity.Then, make antimony (Sb) thermal diffusion, form N-type and imbed diffusion layer 5,19.Then remove silicon oxide film 31 and liquid source electrode 32.
Then, as shown in Figure 3, cvd silicon oxide film 33 on substrate 3.Then on silicon oxide film 33, form photoresist 34.And use on the photoresist 34 of well-known lithography technology on the region that is formed with P type embedding layer 35,36,37 and form peristome.Thereafter, at accelerating voltage 90~180 (keV), import volume 0.5 * 10 14~1.0 * 10 16(/cm 2) condition under from the surface ion of substrate 3, inject for example boron of p type impurity.Then, remove photoresist 34, carry out thermal diffusion, form P type and imbed diffusion layer 35,36,37.
Then, as shown in Figure 4, substrate 3 is configured on the recipient of vapor phase epitaxial growth device, on substrate 3, forms epitaxial loayer.Vapor phase epitaxial growth device mainly consists of gas supply system, reactor, gas extraction system, control system.In the present embodiment, owing to using vertical formula reactor, so can improve the film thickness uniformity of epitaxial loayer.By the heat treatment of the formation operation at this epitaxial loayer 4, N-type is imbedded to diffusion layer 5,19 and P type and imbed diffusion layer 35,36,37 and carry out thermal diffusion.
Then, cvd silicon oxide film 38 on epitaxial loayer 4.Then, on silicon oxide film 38, form photoresist 39.Then, use on the photoresist 39 of well-known lithography technology on the region that is formed with P type embedding layer 40,41,42 and form peristome.Thereafter, at accelerating voltage 90~180 (keV), import volume 0.5 * 10 14~1.0 * 10 16(/cm 2) condition under from the surface ion of epitaxial loayer 4, inject for example boron of p type impurity.And remove photoresist 39, form P type and imbed diffusion layer 40,41,42.
Then, as shown in Figure 5, on silicon oxide film 38, form photoresist 43.Then, use on the photoresist 43 of well-known lithography technology on the region that is formed with N-type embedding layer 20 and form peristome.Take photoresist 43 as mask, at accelerating voltage 90~110 (keV), import volume 1.0 * 10 13~1.0 * 10 15(/cm 2) condition under from the surface ion of epitaxial loayer 4, inject for example phosphorus (P) of N-type impurity., remove silicon oxide film 38 and photoresist 43, make phosphorus (P) thermal diffusion, form n type diffused layer 20 thereafter.
Then, as shown in Figure 6, make epitaxial loayer 4 surface heat oxidations, on epitaxial loayer 4 surfaces, form silicon oxide film 44.To form the mode of peristome in the formation district at p type diffused layer 7,8,9,21, optionally remove silicon oxide film 44.Then, by cleaning the wafer that is formed with epitaxial loayer 4, make epitaxial loayer 4 surfaces of exposing from the peristome of silicon oxide film 44 there is hydrophily.
Then the aqueous solution (having dissolved the solution of tungstic acid with ammoniacal liquor) that, contains tungsten with spin-coating method coating is 10 (ml) left and right for example.And, while make wafer rotation make its dry tack free, afterwards, with spin-coating method, by containing p type impurity, be coated in the surface of epitaxial loayer 4 as the liquid source electrode 45 of boron.And, by making the thermal diffusion simultaneously of tungsten and boron, form p type diffused layer 7,8,9,21.Now, on substrate 3 and epitaxial loayer 4 tungsten simultaneously by thermal diffusion.Remove silicon oxide film 44 and liquid source electrode 45 thereafter.In addition, as long as at least make tungsten be diffused in epitaxial loayer 4.
Then, as shown in Figure 7, use well-known lithography technology, by desired formation method, form n type diffused layer 6,22.Thereafter, on epitaxial loayer 4, deposition such as psg film etc. is done insulating barrier 10.And, use well-known lithography technology, by having used CHF3+O2, be for example that the dry ecthing of gas forms contact hole 11,12,13,14,23,24,25 on insulating barrier 10.On contact hole 11,12,13,14,23,24,25, form selectively for example Al-Si film of aluminium alloy, to form collector electrode 15,17,28 and emitter 16,26 and base stage 18,27.
It should be noted that, in the present embodiment, the public operation by with forming the operation of p type diffused layer 7,8,9,21, is illustrated the situation that makes tungsten be diffused into substrate 3 and epitaxial loayer 4, but is not only confined to this kind of situation.For example, can be also by making tungsten be diffused into the situation of substrate 3 and epitaxial loayer 4 with the public operation that forms the operation of the p type diffused layer that area of isolation uses on epitaxial loayer 4.In addition, in the present embodiment, although the situation of the aqueous solution that contains tungsten with spin-coating method coating is illustrated,, be not only confined to this kind of situation.For example, also can by ion implantation, in containing the aqueous solution of tungsten the method for impregnation process wafer, or make the liquid source electrode 45 that contains boron contain tungsten compound, and make the method for tungsten and boron co-diffused, make tungsten be diffused into the situation of substrate 3 and epitaxial loayer 4.In addition,, within not exceeding the scope of aim of the present invention, those skilled in the art can make various combinations and modification to the present invention.

Claims (8)

1.一种半导体装置,包括第一导电类型的衬底、作为基极区域使用的第二导电类型外延层、第二导电类型埋入扩散层、作为基极引出区域使用的第二导电类型扩散层、作为发射极区域使用的第一导电类型扩散层、作为集电极区域使用的第一导电类型扩散层;其特征在于,在所述作为基极区域使用的第二导电类型外延层中扩散有钨。1. A semiconductor device, comprising a substrate of the first conductivity type, a second conductivity type epitaxial layer used as a base region, a second conductivity type buried diffusion layer, and a second conductivity type diffusion layer used as a base lead-out region layer, the first conductivity type diffusion layer used as the emitter region, and the first conductivity type diffusion layer used as the collector region; it is characterized in that, in the second conductivity type epitaxial layer used as the base region, diffused tungsten. 2.如权利要求1所述的半导体装置,其特征在于,所述衬底为单晶衬底。2. The semiconductor device according to claim 1, wherein the substrate is a single crystal substrate. 3.如权利要求1或2所述的半导体装置,其特征在于,所述衬底为单晶硅衬底。3. The semiconductor device according to claim 1 or 2, wherein the substrate is a single crystal silicon substrate. 4.如权利要求1所述的半导体装置,其特征在于,所述晶体管还包括形成在基极区域上的绝缘层。4. The semiconductor device according to claim 1, wherein the transistor further comprises an insulating layer formed on the base region. 5.如权利要求4所述的半导体装置,其特征在于,所述绝缘层为PGS膜。5. The semiconductor device according to claim 4, wherein the insulating layer is a PGS film. 6.如权利要求1所述的半导体装置,其特征在于,所述晶体管还包括集电极、发射极和基极。6. The semiconductor device according to claim 1, wherein the transistor further comprises a collector, an emitter and a base. 7.如权利要求6所述的半导体装置,其特征在于,所述集电极、发射极和基极用铝合金形成。7. The semiconductor device according to claim 6, wherein the collector, emitter, and base are formed of aluminum alloy. 8.如权利要求7所述的半导体装置,其特征在于,所述集电极、发射极和基极用Al-Si形成。8. The semiconductor device according to claim 7, wherein the collector, emitter and base are formed of Al-Si.
CN201310504608.3A 2013-10-23 2013-10-23 Semiconductor device Pending CN103606556A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101114671A (en) * 2006-07-28 2008-01-30 三洋电机株式会社 Semiconductor device and manufacturing method thereof
US20080150083A1 (en) * 2006-12-21 2008-06-26 Sanyo Electric Co., Ltd. Semiconductor Device and Method of Manufacturing the Same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101114671A (en) * 2006-07-28 2008-01-30 三洋电机株式会社 Semiconductor device and manufacturing method thereof
US20080150083A1 (en) * 2006-12-21 2008-06-26 Sanyo Electric Co., Ltd. Semiconductor Device and Method of Manufacturing the Same

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
KARANAM BALA ET AL.,: "Ion Implantation Issues in Microelectronic Device Manufacturing", 《ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE》, 24 May 1995 (1995-05-24), pages 51 - 57 *
YOSHIHISA FUJISAKI ET AL.,: "Characterization of tungsten-related deep levels in bulk silicon crystal", 《JOURNAL OF APPLIED PHYSICS》, vol. 63, no. 7, 23 October 1987 (1987-10-23), pages 2304 - 2306 *
周享春: "《普通化学》", 1 September 2013, article "第10章 过渡元素", pages: 232 *

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Application publication date: 20140226