CN103595410A - Image sensor and column analog-to-digital converter thereof - Google Patents

Abstract

The invention provides an image sensor and a column analog-to-digital converter thereof. The row analog-to-digital converter comprises a counter for providing a counting result, a ramp signal generator for providing a ramp signal and a start signal, a sampling and comparing array, a first latch array, a second latch array and an operation unit. The sampling and comparing array outputs a plurality of brightness conversion signals according to the ramp signal, the initial signal and the brightness voltage of the plurality of photosensitive pixels. The first and second latch arrays latch the counting result in response to the luminance conversion signals, and output a plurality of first luminance latch values during a first period and a plurality of second luminance latch values during a second period. The operation unit is coupled to calculate the brightness values of the photosensitive pixels according to the first brightness latch values and the second brightness latch values.

Description

Imageing sensor and column analog-to-digital converter thereof

Technical field

The invention relates to a kind of imageing sensor and column analog-to-digital converter thereof, and particularly relevant for a kind of low noise imageing sensor and column analog-to-digital converter thereof.

Background technology

In recent years, along with significantly improving of numeral science and technology, and the fast development of Internet and multimedia application, many images all wish to be converted to digital picture, so that process and transmit, the imageing sensor that therefore image can be converted to digital picture becomes gradually important in multimedia application.

Generally speaking, imageing sensor is consisted of electronic component, and the electrical characteristic of electronic component and circuit can be approached ideal characterisitics, but cannot reach the requirement of ideal characterisitics completely, so that electronic component and circuit may have noise (being unexpected voltage or signal), and then the digital picture exported of imageing sensor.With amplifier, due to two of amplifier relatively inputs there is offset voltage (being non-existent in ideal characterisitics), therefore utilize comparison circuit that amplifier forms can be subject to the impact of offset voltage, cause comparative result can produce error, and then affect the correctness of digital picture.Therefore, how to reduce or the caused noise of unreasonably phase behaviour of eliminating electronic component or circuit becomes an emphasis of designed image transducer.

Summary of the invention

The invention provides a kind of imageing sensor and column analog-to-digital converter thereof, can reduce the impact that circuit noise causes, the correctness of the brightness value being sensed to improve.

The invention provides a kind of column analog-to-digital converter (column analog to digital converter), be suitable for having a pel array of the photosensitive pixel of several column.Column analog-to-digital converter comprises that a counter, a ramp signal maker, a sampling and comparator array, one first latch array, one second and latch array and an arithmetic element.Counter foundation one clock signal is to provide a count results.Ramp signal maker provides a ramp signal according to clock signal, and an initial signal is provided.Sampling has a plurality of samplings and comparison circuit with comparator array, in the middle of these samplings and comparison circuit, each is respectively according to ramp signal and initial signal, and an initial voltage and a luminance voltage of the photosensitive pixel of a respective column in these photosensitive pixels, export a brightness transition signal.First latchs array has a plurality of the first latchs, wherein in the middle of these first latchs, each couples respectively counter, with within a first period, the response brightness transition signal that a corresponding person is exported in the middle of these samplings and comparison circuit, and count results is latched and becomes one first brightness latched value.Second latchs array has a plurality of the second latchs, wherein in the middle of these second latchs, each couples respectively counter, with within a second phase different from first period, the response brightness transition signal that a corresponding person is exported in the middle of these samplings and comparison circuit, and count results is latched and becomes one second brightness latched value.Arithmetic element couples first and latchs array and second and latch array, with receive in the middle of these first latchs each the first brightness latched value and these the second latchs in the middle of each the second brightness latched value, and according to the first brightness latched value receiving and the second brightness latched value, calculate a brightness value of the photosensitive pixel of respective column.

In one embodiment of this invention, during first period is the first phase place of a phase signal, and during the second phase is one second phase place of a phase signal.

In one embodiment of this invention, arithmetic element is to calculate a summation of the first brightness latched value receive and the second brightness latched value as the brightness value of the photosensitive pixel of respective column.

In one embodiment of this invention, arithmetic element is to calculate a mean value of the first brightness latched value receive and the second brightness latched value as the brightness value of the photosensitive pixel of respective column.

In one embodiment of this invention, arithmetic element comprises a plurality of sub-arithmetic elements, in the middle of each is coupled to respectively a corresponding person and the central corresponding person of these the second latchs in the middle of these first latchs, this a little arithmetic element is in order at one time, according to these the first brightness latched values of these the first latchs and these the second brightness latched values of these the second latchs, parallel computing goes out these brightness values of the photosensitive pixel of these row.

In one embodiment of this invention, arithmetic element is in order to sequentially in different time, respectively according to the first brightness latched value of the one in the middle of these first latchs, with the second brightness latched value of one in the middle of these second latchs, and calculate the brightness value of the photosensitive pixel of the one in these broomrapes.

In one embodiment of this invention, in the middle of these samplings and comparison circuit, each comprises that one first compares switch, one second relatively switch, one first electric capacity, one second electric capacity, an amplifier, a handshaking device, the first sampling switch and the second sampling switch.The first comparison switch has first end and is coupled to ramp signal, and has one second end.The second comparison switch has first end and is coupled to initial signal, and has one second end.The first electric capacity has the second end and the luminance voltage that first end is coupled to the first comparison switch, and has one second end.The second electric capacity has the second end and the initial voltage that first end is coupled to the first comparison switch, and has one second end.Amplifier has the first relatively input and the second input relatively, and the first relatively output and the second output relatively, and brightness transition signal is according to first, to compare output and second compare in the middle of output the voltage quasi position of one at least and produce.Handshaking device is coupled between first and second electric capacity and amplifier, to control the second end of the first electric capacity and the second end of the second electric capacity, be to be coupled to respectively first of amplifier to compare relatively input of input and second, or coupling to second of amplifier compare relatively input of input and first.The first sampling switch is coupled in first of amplifier and compares between input and a reference voltage.The second sampling switch is coupled in second of amplifier and compares between input and reference voltage.

In one embodiment of this invention, column analog-to-digital converter more comprises a luminance voltage switch and an initial voltage switch.Luminance voltage switch is coupled between luminance voltage and the first end of the first electric capacity.Initial voltage switch is coupled between initial voltage and the first end of the second electric capacity.

In one embodiment of this invention, luminance voltage switch and initial voltage switch be between the sampling date during one first phase place of a phase signal in conducting in proper order, and between the comparable period during the first phase place of phase signal and internal cutting off during one second phase place of phase signal.

In one embodiment of this invention, in between the comparable period during one first phase place of a phase signal, handshaking device is the second end of the second end of the first electric capacity and the second electric capacity to be coupled to respectively to first of amplifier compare relatively input of input and second, and between the comparable period during one second phase place of phase signal, handshaking device is the second end of the second end of the first electric capacity and the second electric capacity to be coupled to respectively to second of amplifier compare relatively input of input and first.

In one embodiment of this invention, in between the sampling date before the position during the first phase place of phase signal is between the comparable period, first and second sampling switch conducting, and first and second relatively switch cut-out, and between the comparable period between the comparable period during the first phase place of phase signal and during the second phase place of phase signal, first and second sampling switch cuts off, and first and second compares switch conduction.

In one embodiment of this invention, when the first voltage quasi position that compares input compares the voltage quasi position of input higher than second, first compares output output one first level, second compares output output one second level, when first, relatively the voltage quasi position of input is low or equal second relatively during the voltage quasi position of input, first compares output exports the second level, and second compares relatively level of output output first.

In one embodiment of this invention, in the middle of these samplings and comparison circuit, each also comprises a switching signal generation unit, the the first comparison output and second that couples amplifier compares one of output and sampling and comparison circuit and compares between output, to compare the relatively voltage quasi position of output of output and first, output brightness switching signal according to first.

In one embodiment of this invention, switching signal generation unit is when the voltage quasi position of the first comparison output and the second comparison output equates in fact, switches the voltage quasi position of brightness transition signal.

In one embodiment of this invention, switching signal generation unit comprises a RS latch.RS latch have one first latch input terminal be coupled in first relatively output, one second latch input terminal be coupled in second relatively output, one first latch output and one second and latch output.

In one embodiment of this invention, switching signal generation unit also comprises a logical block.Logical block have one first logic input terminal be coupled in first latch output, one second logic input terminal is coupled in the second latch input terminal, and a logic output terminal, wherein logical block is according to the voltage quasi position of the voltage quasi position switch logic output of the first logic input terminal and the second logic input terminal.

In one embodiment of this invention, logical block comprises an anti-or lock, and wherein a plurality of inputs anti-or lock couple respectively the first logic input terminal and the second logic input terminal, and an output anti-or lock couples logic output terminal.

In one embodiment of this invention, switching signal generation unit comprises a signal shifter.Signal shifter has the first comparison output that the first switching input is coupled to amplifier, be coupled to second of amplifier with the second switching input and compare output, and one exchange output, it is coupled to the first switching input and within the second phase, is coupled to the second switching input within first period.

In one embodiment of this invention, in the middle of these samplings and comparison circuit, each comprises a handshaking device and an amplifier.Handshaking device comprises one first exchange input and one second exchange input, and one first exchange output exchange output with one second, under first mode, the first exchange input and the second exchange input are coupled to respectively the first exchange output and the second exchange output, under one second pattern, the first exchange input and the second exchange input are coupled to respectively the second exchange output and the first exchange output.Amplifier comprises that one first compares relatively input of input and one second, be coupled to respectively the first exchange output and the second exchange output, and comprise one first relatively output and one second output relatively, brightness transition signal be according to first relatively output and second compare in the middle of output the voltage quasi position of one at least and produce.In between the sampling date within first period, handshaking device is operated in first mode, so that the first comparison input and second compares input, is to be coupled to respectively luminance voltage and initial voltage.In between the comparable period within first period, handshaking device is operated in first mode, so that the first comparison input and second compares input, is to be coupled to respectively ramp signal and initial signal.In between the comparable period within the second phase, handshaking device is operated in the second pattern, so that the first comparison input and second compares input, is to be coupled to respectively initial signal and ramp signal.

In one embodiment of this invention, in the middle of these samplings and comparison circuit, each also comprises that one first electric capacity, one second electric capacity, one first compare relatively switch of switch and one second.The first electric capacity has first end and the second end, the second end are coupled to the first exchange input.The second electric capacity has first end and the second end, the second end are coupled to the second exchange input.First compares switch is coupled between ramp signal and the first end of the first electric capacity.Second compares switch is coupled between initial signal and the first end of the second electric capacity.

In one embodiment of this invention, in the middle of these samplings and comparison circuit, each also comprises a luminance voltage switch and an initial voltage switch.Luminance voltage switch is coupled between luminance voltage and the first end of the first electric capacity.Initial voltage switch is coupled between initial voltage and the first end of the second electric capacity.

In one embodiment of this invention, in the middle of these samplings and comparison circuit, each also comprises one first sampling switch and one second sampling switch.The first sampling switch is coupled to first of amplifier and compares between input and a reference voltage.The second sampling switch is coupled to second of amplifier and compares between input and reference voltage.

In one embodiment of this invention, within first period with the second phase in, sampling with comparator array be to be operated in respectively first mode and the second pattern, under first mode and the second pattern, brightness transition signal is to have different functional relations from luminance voltage.

The present invention also provides a kind of imageing sensor, comprises a pel array and column analog-to-digital converter as above.Pel array has the photosensitive pixel of several column.Above-mentioned column analog-to-digital converter is coupled to pel array.

Based on above-mentioned, the imageing sensor of the embodiment of the present invention and column analog-to-digital converter thereof, a ramp signal and an initial signal that one initial voltage of its photosensitive pixel according to respective column and a luminance voltage and a ramp signal maker provide produce a brightness transition signal, and the first latch according to the corresponding brightness transition signal count results that latching accumulator provides in a first period to export one first brightness latched value, the second latch according to the corresponding brightness transition signal count results that latching accumulator provides in a second phase to export one second brightness latched value, arithmetic element is calculated a brightness value of the photosensitive pixel of this respective column according to the first brightness latched value of correspondence and the second brightness latched value of correspondence.Whereby, can reduce the impact that circuit noise causes, the correctness of the brightness value being sensed to improve.

For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.

Accompanying drawing explanation

Fig. 1 is the system schematic according to the imageing sensor of one embodiment of the invention;

Fig. 2 A is the circuit diagram according to the sampling in Fig. 1 of one embodiment of the invention and comparison circuit;

Fig. 2 B is the drive waveforms schematic diagram according to the sampling in Fig. 2 A of one embodiment of the invention and comparison circuit;

Fig. 3 A is the circuit diagram according to the sampling in Fig. 1 of another embodiment of the present invention and comparison circuit;

Fig. 3 B is the drive waveforms schematic diagram according to the sampling in Fig. 3 A of one embodiment of the invention and comparison circuit;

Fig. 4 A is according to the present invention more sampling in Fig. 1 of another embodiment and the circuit diagram of comparison circuit;

Fig. 4 B is the drive waveforms schematic diagram according to the sampling in Fig. 4 A of one embodiment of the invention and comparison circuit;

Fig. 5 is according to the sampling in Fig. 1 of another embodiment again of the present invention and the circuit diagram of comparison circuit.

Description of reference numerals:

100: imageing sensor;

110: pel array;

120: column analog-to-digital converter;

121: counter;

123: ramp signal maker;

125: sampling and comparator array;

Latch array at 127: the first;

Latch array at 129: the second;

131: arithmetic element;

140: phase-locked loop;

310,410: switching signal generation unit;

420: logical block;

A, I: first switches input;

AP1: amplifier;

B, J: second switches input;

BRL1: the first brightness latched value;

BRL2: the second brightness latched value;

BRV: brightness value;

BT1～BT3, BT1a～BT1c: brightness transition signal;

C: the first exchange output;

C1: the first electric capacity;

C2: the second electric capacity;

CLK: clock signal;

CTR: count results;

D: the second exchange output;

E: first compares input;

F: second compares input;

G: first compares output;

H: second compares output;

K: exchange output;

L: the first latch input terminal;

LT11～LT13: the first latch;

LT21～LT23: the second latch;

M: the second latch input terminal;

N: first latchs output;

NR1: anti-or lock;

O: second latchs output;

OC1: compare output;

P: the first logic input terminal;

PCP1, PCP2: between the comparable period;

PH1: during the first phase place;

PH2: during the second phase place;

PS: photosensitive pixel;

PSP: between sampling date;

Q: the second logic input terminal;

R: logic output terminal;

RS1:RS latch;

SA1～SA3: sub-arithmetic element;

SC1～SC3, SC1a～SC1d: sampling and comparison circuit;

SE1～SE3: handshaking device;

SWC1: first compares switch;

SWC2: second compares switch;

SWS1: the first sampling switch;

SWS2: the second sampling switch;

SWVR: initial voltage switch;

SWVS: luminance voltage switch;

VE, VF, VG, VH, VN, VO: waveform;

VRAMP: ramp signal;

VRST: initial voltage;

VSGN: luminance voltage;

VSTART: initial signal;

ψ: phase signal.

Embodiment

Fig. 1 is the system schematic according to the imageing sensor of one embodiment of the invention.Please refer to Fig. 1, in the present embodiment, imageing sensor 100 comprises pel array 110, column analog-to-digital converter 120 and phase-locked loop 140.Pel array 110 has the photosensitive pixel PS of several column (n) and plural number row (m), and wherein each photosensitive pixel PS all can provide an initial voltage VRST and a luminance voltage VSGN.Pel array 110 can be exported line by line, therefore n initial voltage VRST and n luminance voltage VSGN that n pixel in exportable certain a line of each time provides.Phase-locked loop 140 is in order to provide a clock signal clk.Column analog-to-digital converter 120 is coupled to initial voltage VRST and the luminance voltage VSGN that pel array 110 is provided to receive these photosensitive pixels PS, and is coupled to phase-locked loop 140 with receive clock signal CLK.The brightness value BRV that column analog-to-digital converter 120 calculates these photosensitive pixels PS according to initial voltage VRST and the luminance voltage VSGN of clock signal clk and these photosensitive pixels PS.

In the present embodiment, column analog-to-digital converter 120 comprises that a counter 121, a ramp signal maker 123, a sampling and comparator array 125, one first latch array 127, one second and latch array 129 and an arithmetic element 131.Counter 121 couples phase-locked loop 140 with receive clock signal CLK, and counts to provide a count results CTR according to clock signal clk.Ramp signal maker 123 couples phase-locked loop 140 with receive clock signal CLK, and provides a ramp signal VRAMP according to clock signal clk, and an initial signal VSTART is provided.Wherein, the voltage quasi position of ramp signal VRAMP can be arranged to increasing or decreasing in time, and the count results CTR of the corresponding counter 121 of the voltage quasi position of ramp signal VRAMP meeting, and initial signal VSTART can be arranged to a direct voltage, and its level is the starting voltage level that ramp signal VRAMP carries out increasing or decreasing.

Sampling and comparator array 125 have a plurality of samplings and comparison circuit (as SC1～SC3... etc.).In the middle of these samplings and comparison circuit (as SC1～SC3), each couples respectively ramp signal maker 123 to receive ramp signal VRAMP and initial signal VSTART, and a photosensitive pixel PS who couples a respective column in these photosensitive pixels PS is to receive corresponding initial voltage VRST and corresponding luminance voltage VSGN.Each sampling is exported a brightness transition signal (as BT1～BT3) with comparison circuit (as SC1～SC3) according to ramp signal VRAMP, initial signal VSTART, the initial voltage VRST being received and the luminance voltage VSGN that received.

In addition, sampling can be operated in first mode and the second pattern with comparison circuit SCi (wherein i=1～n).Under first mode with the second pattern under, the numerical digit code code of brightness transition signal BTi representative _ifrom between the voltage quasi position of luminance voltage VSGN, have different functional relations.If represent with mathematical expression, under first mode, the numerical digit code code of brightness transition signal BTi representative _ithere is one first functional relation with the voltage quasi position of luminance voltage VSGN

under the second pattern, the numerical digit code code of brightness transition signal BTi _ithere is one second functional relation with the voltage quasi position of luminance voltage VSGN ${\mathrm{code}}_i=g_{1^i}\left(\mathrm{VSGN}\right).$

In a specific embodiment, sampling can, in the pressure reduction of the approximate luminance voltage VSGN of the voltage quasi position that detects ramp signal VRAMP and initial voltage VRST, be switched the voltage quasi position of brightness transition signal BTi with comparison circuit SCi.In other words, the numerical digit code code of brightness transition signal BTi representative _ibe to define switching time by the voltage level of brightness transition signal BTi, and this numerical digit code is the pressure reduction that corresponds to luminance voltage VSGN and initial voltage VRST.On mathematics, can be expressed as: under first mode,

and under the second pattern, ${\mathrm{code}}_i=g_{1^i}\left(\mathrm{VSGN}\right)=G_{1^i}(\mathrm{VRST}-\mathrm{VSGN}).$

Preferably, within first period, sampling is all operated in first mode with comparison circuit SC1～SCn; And within the second phase not identical with this first period, sampling all can be operated in the second pattern with comparison circuit SC1～SCn.Sampling for example can be by the control that receives a phase signal ψ with comparison circuit SCi, and above-mentioned first period is (during high voltage level) during the first phase place of phase signal ψ, and the second phase be (during low-voltage level) during one second phase place of phase signal ψ.

First latchs array 127 has a plurality of the first latchs (as LT11～LT13).Each couples respectively counter 121 with count pick up result CTR in the middle of these first latchs (as LT11～LT13), and couple respectively corresponding sampling with comparison circuit (as SC1～SC3) to receive corresponding brightness transition signal (as BT1～BT3).Within first period, the count results CTR of counter 121 can provide these first latchs (as LT11～LT13) that latch array 127 to first, and within this first period, each first latch (as LT11～LT13), in response to corresponding brightness transition signal (as BT1～BT3), becomes one first brightness latched value BRL1 (for example comprising BRL11～BR1n) and in time count results CTR is latched.

For example, the count results CTR producing when counter 121 is in time during increasing or decreasing, each first latch LT1j (wherein j=1～n) all can wait until when count results CTR changes to the numerical value of the brightness transition signal BTj representative that equals corresponding, just count results CTR can be latched and become the first corresponding brightness latched value BRL1j.In a specific embodiment, be the luminance voltage VSGN that represents respective pixel the switching time of the voltage level of the brightness transition signal BTi that sampling and comparison circuit SCi (wherein i=1～n) produce, and the first the first latch LT1i latching in array 127 is the switch operating of responding at the voltage level of brightness transition signal BTi, and immediately count results CTR is latched, becomes the first brightness latched value BRLli.On mathematics, within first period, sampling all can be operated in first mode with comparison circuit SC1～SCn, if so numerical digit code of the first brightness latched value BRLli representative

the first brightness latched value BRLli also can represent identical numerical digit code code _i.

Second latchs array 129 has a plurality of the second latchs (as LT21～LT23).Each couples respectively and couples respectively counter 121 with count pick up result CTR in the middle of these second latchs (as LT21～LT23), and couple respectively corresponding sampling with comparison circuit (as SC1～SC3) to receive corresponding brightness transition signal (as BT1～BT3).Within the second phase, the count results CTR of counter 121 provides these second latchs (as LT21～LT23) that latch array 129 to second, and within this second phase, each second latch (as LT21～LT23), in response to corresponding brightness transition signal (as BT1～BT3), becomes one second brightness latched value BRL2 (for example comprising BRL21～BR2n) and in time count results CTR is latched.

For example, the count results CTR producing when counter 121 is in time during increasing or decreasing, each second latch LT 2j (wherein j=1～n) all can wait until when count results CTR changes to the numerical value that equals this corresponding brightness transition signal BTj representative, just count results CTR can be latched and become the second brightness latched value BRL2j.In a specific embodiment, be the luminance voltage VSGN that represents respective pixel the switching time of the voltage level of the brightness transition signal BTi that sampling and comparison circuit SCi (wherein i=1～n) produce, and the second the second latch LT2i latching in array 129 is in response to the switch operating of the voltage level of brightness transition signal BTi, and immediately count results CTR is latched, becomes the second brightness latched value BRL2i.On mathematics, within the second phase, sampling all can be operated in the second pattern with comparison circuit SC1～SCn, if so numerical digit code of the second brightness latched value BRL2i representative

the second brightness latched value BRL2i also can represent identical numerical digit code code _i.

It should be noted that the voltage quasi position of brightness transition signal BTi and the triggering relation of the first latch and the second latch can have all different configurations.For example, in some specific embodiments, sampling is with the voltage quasi position of the changeable brightness transition signal of comparison circuit SCi BTi to form positive edge or negative edge, and the first latch (as LT11～LT13) and the second latch (as LT21～LT23) can be configured to accordingly two edge and trigger.In some other embodiment, sampling is with the voltage quasi position of the changeable brightness transition signal of comparison circuit SCi BTi to form positive edge, and the first latch (as LT11～LT13) and the second latch (as LT21～LT23) can be configured to accordingly positive edge and trigger.In some other embodiment again, sampling is with the voltage quasi position of the changeable brightness transition signal of comparison circuit SCi BTi to form negative edge, and the first latch (as LT11～LT13) and the second latch (as LT21～LT23) can be configured to accordingly negative edge and trigger.In addition, the voltage quasi position that sampling and comparison circuit SCi are configured to switch brightness transition signal BTi is to form in the situation of positive pulse wave, and the first latch (as LT11～LT13) and the second latch (as LT21～LT23) can be arranged to high levle and trigger.Otherwise, in the situation that the voltage quasi position that sampling and comparison circuit SCi are configured to switch brightness transition signal BTi to be to form negative pulse wave, the first latch (as LT11～LT13) and the second latch (as LT21～LT23) can be arranged to accordingly low level and be triggered.

Arithmetic element 131 couples first and latchs array 127 and second and latch array 129, with receive in the middle of these first latchs (as LT11～LT13) each the first brightness latched value BRL1 and these the second latchs (as LT21～LT23) in the middle of each the second brightness latched value BRL2, and the brightness value BRV that calculates each photosensitive pixel PS according to the first brightness latched value BRL1 receiving and the second brightness latched value BRL2.

Comprehensively above-mentioned, because each sampling is according to ramp signal VRAMP with comparison circuit (as SC1～SC3), initial signal VSTART, the initial voltage VRST of one photosensitive pixel PS of one respective column and luminance voltage VSGN export a brightness transition signal (as BT1～BT3), and first latchs array 127 and second, and to latch array 129 be all to produce respectively the first brightness latched value BRL1 and the second brightness latched value BRL2 according to brightness transition signal, therefore arithmetic element 131 can be according to the first brightness latched value BRL1 and the second brightness latched value BRL2, calculate the brightness value BRV of photosensitive pixel PS.To represent on mathematics, the brightness value of the photosensitive pixel PS that i lists $\mathrm{BRVi}=H(F_{1^i}(\mathrm{VRST}-\mathrm{VSGN}),G_{1^i}(\mathrm{VRST}-\mathrm{VSGN})),$ Wherein H represents the arithmetic expression that arithmetic element is performed.

Arithmetic element 131 can be utilized different account forms, carrys out to calculate according to the first brightness latched value BRL1 and the second brightness latched value BRL2 the brightness value BRV of the photosensitive pixel PS of respective column.For example, in the situation that the first brightness latched value BRL1, the second brightness latched value BRL2 are identical with the figure place of brightness value BRV, arithmetic element 131 can be configured to a mean value of the first brightness latched value BRL1 that calculating receives and the second brightness latched value BRL2 receiving as the brightness value BRV of a photosensitive pixel PS of respective column.To represent on mathematics, the brightness value of the photosensitive pixel PS that i lists

or in the situation that the figure place that the figure place of the first brightness latched value BRL1 and the second brightness latched value BRL2 is brightness value BRV subtracts 1, arithmetic element 131 can be configured to a summation of the first brightness latched value BRL1 that calculating receives and the second brightness latched value BRL2 receiving as the brightness value BRV of a photosensitive pixel PS of respective column.To represent on mathematics, the brightness value of the photosensitive pixel PS that i lists $\mathrm{BRVi}=(F_{1^i}(\mathrm{VRST}-\mathrm{VSGN})+G_{1^i}(\mathrm{VRST}-\mathrm{VSGN})).$

In this embodiment, the account form of arithmetic element 131 is to be embodied as parallel processing.In other words, arithmetic element 131 configurable at one time in, according to the first brightness latched value (BRL11～BRL13... etc.) of the first latch (LT11～LT13... etc.) and the second brightness latched value (BRL21～BRL23... etc.) of the second latch (LT21～LT23... etc.), parallel computing goes out those brightness values BRV1～BRVn of the photosensitive pixel of n row simultaneously.

For reaching this object, as shown in the embodiment of Fig. 1, arithmetic element 131 can comprise a plurality of sub-arithmetic elements (as SA1～SA3).In the middle of this little arithmetic element (as SA1～SA3) each be coupled to respectively in the middle of these first latchs (as LT11～LT13) corresponding person with the central corresponding person of these second latchs (as LT21～LT23) to receive respectively the first corresponding brightness latched value BRL1 and the second brightness latched value BRL2.And, this a little arithmetic element (as SA1～SA3) is in order at one time, according to these first brightness latched value BRL1 of these the first latchs (as LT11～LT13) and these the second brightness latched values BRL2 of these the second latchs (as LT21～LT23), parallel computing goes out these brightness values BRV1～BRVn of the photosensitive pixel of these row.

Yet, it should be noted that the account form of arithmetic element 131 also can be embodied as batch processed in other embodiment (not shown)s, be also the brightness value BRV that arithmetic element 131 once calculates the photosensitive pixel in corresponding a certain row.Therefore, arithmetic element 131 sequentially, in different time, successively calculates the brightness value BRV of n photosensitive pixel PS in certain a line.In other words, calculating each time, arithmetic element 131 is according to one (such as the LT1i in the middle of these first latchs, i=1～n wherein) the first brightness latched value (such as BRL1i), with one (such as the LT2i in the middle of these second latchs, i=1～n wherein) the second brightness latched value (such as BRL2i), calculates the brightness value BRVi of the photosensitive pixel PS in the one (for example i row) in these broomrapes.

At following embodiment, will describe in detail, by sampling is carried out to suitable circuit design with comparison circuit SC, can be configured to sampling and comparison circuit SCi in the voltage level deviation (voltage offset level) of an amplifier have a positive correlation, and

voltage level deviation is had to a negative correlation.And then can utilize the suitable computing of arithmetic element 131, eliminate the error that the voltage level deviation of this amplifier causes for brightness value BRV.

Fig. 2 A is the circuit diagram according to the sampling in Fig. 1 of one embodiment of the invention and comparison circuit.Please refer to Fig. 1 and Fig. 2 A, in the present embodiment, sampling is to be denoted as SC1a with comparison circuit, the brightness transition signal of its generation is to be denoted as BT1a, wherein to can be respectively in Fig. 1 any sampling be to be denoted as BTi with comparison circuit SCi and its brightness transition signal producing for SC1a and BT1a, wherein i=1～n.

In the present embodiment, sampling is to be configured to when the voltage quasi position that detects ramp signal VRAMP is similar to the pressure reduction of luminance voltage VSGN and initial voltage VRST with comparison circuit SC1a, switch the voltage quasi position of brightness transition signal BT1a, and then trigger the first the first latch (as LT11～LT13) that latchs array 127 and latch count results CTR and become the first brightness latched value BRL1 and trigger the second the second latch (as LT21～LT23) that latchs array 129 and latch count results CTR and become the second brightness latched value BRL2.

Referring to Fig. 2 A, sampling comprises that with comparison circuit SC1a first compares interrupteur SW C1, second relatively interrupteur SW C2, the first capacitor C 1, the second capacitor C 2, amplifier AP1, handshaking device SE1, the first sampling switch SWS1, the second sampling switch SWS2, luminance voltage interrupteur SW VS and initial voltage interrupteur SW VR.Handshaking device SE1 has the first switching input A, second and switches input B, the first exchange output C and the second exchange output D.Amplifier AP1 has the first comparison input E, second relatively voltage quasi position and the second comparison output H of input F, the first comparison output G, and the second comparison output H is the direct comparison output OC1 of circuit SC1a as a comparison, and output voltage V H is as brightness transition signal BT1a.

First compares interrupteur SW C1 has first end, this first end is coupled to ramp signal VRAMP, and there is the second end, and this second end is coupled to the first end of the first capacitor C 1, and also the first comparison interrupteur SW C1 is coupled between ramp signal VRAMP and the first end of the first capacitor C 1.Luminance voltage interrupteur SW VS has first end, this first end couples luminance voltage VSGN, and thering is the second end, this second end couples the first end of the first capacitor C 1, is also that luminance voltage interrupteur SW VS is coupled between luminance voltage VSGN and the first end of the first capacitor C 1.Under this configuration, the first end of the first capacitor C 1 compares interrupteur SW C1 by first and is coupled to ramp signal VRAMP or is coupled to luminance voltage VSGN by luminance voltage interrupteur SW VS.In addition, the second end of the first capacitor C 1 is coupled to the first switching input A of handshaking device SE1.

Similarly, second compares interrupteur SW C2 has first end, and this first end is coupled to initial signal VSTART, and has the second end, this the second end is coupled to the first end of the second capacitor C 2, and also the second comparison interrupteur SW C2 is coupled between initial signal VSTART and the first end of the second capacitor C 2.Initial voltage interrupteur SW VR has first end, this first end couples initial voltage VRST, and thering is the second end, this second end couples the first end of the second capacitor C 2, is also that initial voltage interrupteur SW VR is coupled between initial voltage VRST and the first end of the second capacitor C 2.Under this configuration, the first end of the second capacitor C 2 can compare interrupteur SW C2 by second and be coupled to initial signal VSTART or be coupled to initial voltage VRST by initial voltage interrupteur SW VR.In addition, the second end of the second capacitor C 2 couples the second switching input B of handshaking device SE1.

The first exchange output C of handshaking device SE1 is coupled to first of amplifier AP1 and compares input E, the second exchange output D of handshaking device SE1 is coupled to the second comparison input F of amplifier AP1, is also that the second end, the second end of the second capacitor C 2 and the first comparison input E and second of amplifier that handshaking device SE1 is coupled in the first capacitor C 1 compares between input F.

In addition, the control that handshaking device SE1 for example can receiving phase signal ψ, and have different output to input relation.In the time of in phase signal ψ is during the first phase place, also sampling is operated under first mode with comparison circuit SC1a, handshaking device SE1 controls first according to phase signal ψ and switches input A and be coupled to the first exchange output C and second and switch input B and be coupled to the second exchange output D, also the second end of the first capacitor C 1 be coupled to amplifier AP1 first relatively the second end of input E and the second capacitor C 2 be coupled to the second input F relatively of amplifier AP1.In the time of in phase signal ψ is during the second phase place, also sampling is operated under the second pattern with comparison circuit SC1a, handshaking device SE1 controls first according to phase signal ψ and switches input A and be coupled to the second exchange output D and second and switch input B and be coupled to the first exchange output C, also the second end of the first capacitor C 1 be coupled to amplifier AP1 second relatively the second end of input F and the second capacitor C 2 be coupled to the first input E relatively of amplifier AP1.

The first sampling switch SWS1 is coupled in first of amplifier AP1 and compares between input E and reference voltage VR.The second sampling switch SWS2 is coupled in second of amplifier AP1 and compares between input F and reference voltage VR.Wherein, reference voltage VR can be high voltage level or low-voltage level, and the embodiment of the present invention is not as limit.

According to first, relatively voltage quasi position and the second voltage quasi position that compares input F of input E determine that the first voltage quasi position and second that compares output G compares the voltage quasi position of output H to amplifier AP1.For example, when the first voltage quasi position that compares input E compares the voltage quasi position of input F higher than second, the first comparison exportable the first level of output G (for example high voltage level), and the second comparison exportable the second level of output H (for example low-voltage level); When first, relatively the voltage quasi position of input E is low or equal second relatively during the voltage quasi position of input F, the first exportable the second level of output G relatively, and the second output H exportable first level relatively relatively.

In the present embodiment, the whole circuit structure forming of the first capacitor C 1, the second capacitor C 2, the first sampling switch SWS1, the second sampling switch SWS2, luminance voltage interrupteur SW VS and initial voltage interrupteur SW VR can be considered a correlated double sampling (correlated double sampling, CDS) circuit, wherein the first capacitor C 1 is in order to sample luminance voltage VSGN, and the second capacitor C 2 is in order to sample initial voltage VRST.The whole circuit structure forming of handshaking device SE1, the first sampling switch SWS1, the second sampling switch SWS2 and amplifier AP1 can be considered a comparison circuit, in order to relatively first to exchange the voltage quasi position of output C and the voltage quasi position of the second exchange output D, and produce brightness transition signal BT1a according to comparative result.

In the course of work of sampling and comparison circuit SC1a, first CDS circuit can sample the voltage of luminance voltage VSGN and initial voltage VRST, next, in sampling, be operated under first mode with comparison circuit SC1a, comparison circuit can be by relatively first exchanging the voltage quasi position of output C and the voltage quasi position of the second exchange output D, with the voltage quasi position at ramp signal VRAMP approximate or equal the pressure reduction of luminance voltage VSGN and initial voltage VRST in, the voltage level of switching brightness transition signal BT1a.Next, sampling can switch to the second pattern with comparison circuit SC1a, and similarly, comparison circuit can be by relatively first exchanging the voltage quasi position of output C and the voltage quasi position of the second exchange output D, with the voltage quasi position at ramp signal VRAMP approximate or equal the pressure reduction of luminance voltage VSGN and initial voltage VRST in, the voltage quasi position of switching brightness transition signal BT1a.

In this embodiment, the voltage quasi position relation of luminance voltage VSGN and initial voltage VRST is arranged at after sampling, when the cross-pressure of the first capacitor C 1 can be greater than the cross-pressure of the second capacitor C 2, it is also the voltage quasi position that the first voltage quasi position that switches input A is greater than the second switching input B.In the case, thus ramp signal VRAMP can be arranged to and successively decrease accordingly, to drag down gradually the voltage quasi position of the first switching input A.Thus, that time at the voltage quasi position of the first switching input A lower than the voltage quasi position of the second switching input B, first to switch the voltage quasi position of input A the most close with the voltage quasi position of the second switching input B.Now, the height relation of the voltage quasi position of the voltage quasi position of the first exchange output C and the second exchange output D also can exchange, so that at the first voltage quasi position and the second voltage quasi position that compares output H that compares output G, can exchange, to represent that the voltage quasi position of ramp signal VRAMP is instantly similar to or equals the pressure reduction of luminance voltage VSGN and initial voltage VRST.

Yet, in other other embodiment, the voltage quasi position relation of luminance voltage VSGN and initial voltage VRST is arranged to after sampling, the cross-pressure of the first capacitor C 1 can be less than the cross-pressure of the second capacitor C 2, is also the voltage quasi position that the first voltage quasi position that switches input A is less than the second switching input B.In the case, ramp signal VRAMP can be arranged to and increase progressively accordingly, to draw high gradually the voltage quasi position of the first switching input A.Thus, that time at the voltage quasi position of the first switching input A higher than the voltage quasi position of the second switching input B, first to switch the voltage quasi position of input A the most close with the voltage quasi position of the second switching input B.Now, the height relation of the voltage quasi position of the voltage quasi position of the first exchange output C and the second exchange output D also can exchange, so that at the first voltage quasi position and the second voltage quasi position that compares output H that compares output G, can exchange, to represent that the voltage quasi position of ramp signal VRAMP is instantly similar to or equals the pressure reduction of luminance voltage VSGN and initial voltage VRST.

Comprehensively above-mentioned, no matter be under first mode or under the second pattern, in the approximate luminance voltage VSGN of voltage quasi position of ramp signal VRAMP and the pressure reduction of initial voltage VRST, amplifier AP1 first relatively output G voltage quasi position and second relatively the voltage quasi position of output H can exchange (be also voltage level becomes equal in fact), to switch the voltage quasi position of brightness transition signal BTi.

If represent with mathematical expression, within first period, the numerical digit code of brightness transition signal BT1a representative ${\mathrm{code}}_i=F_{1^i}(\mathrm{VRST}-\mathrm{VSGN})=\mathrm{VRST}-\mathrm{VSGN}+\mathrm{VOSCMP}+\mathrm{VFLICKER}\left(t1\right),$ And within the second phase, the numerical digit code of brightness transition signal BT1a representative ${\mathrm{code}}_i=G_{1^i}(\mathrm{VRST}-\mathrm{VSGN})=\mathrm{VRST}$ $-\mathrm{VSGN}-\mathrm{VOSCMP}+\mathrm{VFLICKER}\left(t2\right),$ Wherein VOSCMP represents the voltage level deviation (voltage offset level) of amplifier AP1, and VFLICKER (t1) representative flicker noise in amplifier APT1 (flicker noise) within first period, and VFLICKER (t2) representative flicker noise in amplifier APT1 within the second phase.

Fig. 2 B is the drive waveforms schematic diagram according to the sampling in Fig. 2 A of one embodiment of the invention and comparison circuit.Please refer to Fig. 2 A and Fig. 2 B, in the present embodiment, when the approximate luminance voltage VSGN of voltage quasi position of ramp signal VRAMP instantly and the pressure reduction of initial voltage VRST, the voltage quasi position of sampling and the changeable brightness transition signal of comparison circuit SC1a BTi is to form positive edge or negative edge.Accordingly, the first latch (as LT11～LT13) and the second latch (as LT21～LT23) can be arranged to two edge and trigger, but are not limited to this.

In the present embodiment, the voltage quasi position according to phase signal ψ can be divided into the first phase place period P H1 (the in this case high voltage level of corresponding phase signal ψ) and the second phase place period P H2 (the in this case low-voltage level of corresponding phase signal ψ).In the one first phase place period P H1 of phase signal ψ, sampling is under first mode with comparison circuit SC1a, also to be handshaking device SE1 control first according to phase signal ψ switches input A and is coupled to the first exchange output C and second and switches input B and be coupled to the second exchange output D, also the second end of the first capacitor C 1 be coupled to amplifier AP1 first relatively the second end of input E and the second capacitor C 2 be coupled to the second input F relatively of amplifier AP1.

Between a sampling date of the one first phase place period P H1 of phase signal ψ in PSP, the first sampling switch SWS1 and the second sampling switch SWS2 can conducting (on) so that relatively input E and second input F relatively of reference voltage VR to the first to be provided, and first relatively interrupteur SW C1 and second compare interrupteur SW C2 and can cut off (off).Now, first of amplifier AP1 compares relatively output H output LOW voltage level (respectively with reference to waveform VG and VH) of output G and second, is also that brightness transition signal BTi is low-voltage level.And, luminance voltage interrupteur SW VS and initial voltage interrupteur SW VR conducting in proper order, the first end of luminance voltage VSGN to the first capacitor C 1 to be provided in proper order and the first end of initial voltage VRST to the second capacitor C 2 is provided, and the first capacitor C 1 can sample luminance voltage VSGN, the second capacitor C 2 can sample initial voltage VRST.First of amplifier AP1 compares input E and is coupled to luminance voltage VSGN by handshaking device SE1 and the first capacitor C 1, and second of amplifier AP1 compares input F and is coupled to initial voltage VRST by handshaking device SE1 and the second capacitor C 2.Wherein, after carrying out voltage sampling, be that to take the cross-pressure that the cross-pressure of the first capacitor C 1 is greater than the second capacitor C 2 be example.

Between a comparable period of the one first phase place period P H1 of phase signal ψ in PCP1, the first sampling switch SWS1, the second sampling switch SWS2, luminance voltage interrupteur SW VS and initial voltage interrupteur SW VR can cut off, and the first relatively relatively interrupteur SW C2 meeting conducting of interrupteur SW C1 and second, the first end of ramp signal VRAMP to the first capacitor C 1 to be provided and the second end of initial signal VSTART to the second capacitor C 2 is provided, wherein ramp signal VRAMP is decremented to example.At this, first of amplifier AP1 compares input E and is coupled to ramp signal VRAMP by handshaking device SE1 and the first capacitor C 1, and second of amplifier AP1 compares input F and is coupled to initial signal VSTART by handshaking device SE1 and the second capacitor C 2.Because the cross-pressure of the first capacitor C 1 is greater than the cross-pressure of the second capacitor C 2, also be the voltage quasi position (respectively with reference to waveform VE and VF) that the first voltage quasi position that compares input E can first be greater than the second comparison input F, so that in the first comparison output G output HIGH voltage level, and the second comparison output H output LOW voltage level.

Then, when first relatively the voltage quasi position of input E be subject to the impact of ramp signal VRAMP and little second relatively during the voltage quasi position of input F, first compares output G and second voltage quasi position that relatively output H exports can exchange, also be the first comparison output G output LOW voltage level, and the second comparison output H output HIGH voltage level is also that brightness transition signal BTi switches to high voltage level to form positive edge.

In the one second phase place period P H2 of phase signal ψ, sampling and comparison circuit SC1a are in the second pattern, also to be handshaking device SE1 control first according to phase signal ψ switches input A and is coupled to the second exchange output D and second and switches input B and be coupled to the first exchange output C, also the second end of the first capacitor C 1 be coupled to amplifier AP1 second relatively the second end of input F and the second capacitor C 2 be coupled to the first input E relatively of amplifier AP1.

Between a comparable period of the second phase place period P H2 of phase signal ψ in PCP2, the first sampling switch SWS1, the second sampling switch SWS2, luminance voltage interrupteur SW VS and initial voltage interrupteur SW VR still can cut off, and first relatively interrupteur SW C1 and the second comparison interrupteur SW C2 still can conductings, the first end of ramp signal VRAMP to the first capacitor C 1 to be provided and the second end of initial signal VSTART to the second capacitor C 2 is provided, wherein ramp signal VRAMP is decremented to example.At this, first of amplifier AP1 compares input E and is coupled to initial signal VSTART by handshaking device SE1 and the first capacitor C 1, and second of amplifier AP1 compares input F and is coupled to ramp signal VRAMP by handshaking device SE1 and the second capacitor C 2.Because the cross-pressure of the first capacitor C 1 is greater than the cross-pressure of the second capacitor C 2, also be the voltage quasi position that the second voltage quasi position that compares input F can first be greater than the first comparison input E, so that in the first comparison output G output LOW voltage level, and the second comparison output H output HIGH voltage level.

Then, when second relatively the voltage quasi position of input F be subject to the impact of ramp signal VRAMP and be less than first relatively during the voltage quasi position of input E, first compares output G and second voltage quasi position that relatively output H exports can exchange, also be the first comparison output G output HIGH voltage level, and the second comparison output H output LOW voltage level is also that brightness transition signal BTi switches to low-voltage level to form negative edge.

Comprehensively above-mentioned, within first period, the numerical digit code of brightness transition signal BT1a representative ${\mathrm{code}}_i=F_{1^i}(\mathrm{VRST}-\mathrm{VSGN})=\mathrm{VRST}-\mathrm{VSGN}+\mathrm{VOSCMP}+\mathrm{VFLICKER}\left(t1\right),$ And within the second phase, the numerical digit code of brightness transition signal BT1a representative ${\mathrm{code}}_i=G_{1^i}(\mathrm{VRST}-\mathrm{VSGN})=\mathrm{VRST}$ $-\mathrm{VSGN}-\mathrm{VOSCMP}+\mathrm{VFLICKER}\left(t2\right),$ Wherein VOSCMP represents the voltage level deviation of amplifier AP1, and VFLICKER (tl) representative flicker noise in amplifier APT1 (flicker noise) within first period, VFLICKER (t2) represents the flicker noise in amplifier APT1 within the second phase.

As previously mentioned, the brightness value of the photosensitive pixel PS that the i that arithmetic element 131 calculates lists can be expressed as: $\mathrm{BRVi}=H(F_{1^i}(\mathrm{VRST}-\mathrm{VSGN}),G_{1^i}(\mathrm{VRST}-\mathrm{VSGN})).$ Therefore, if arithmetic element is carried out sum operation, brightness value BRVi=2 (VRST-VSGN)+VFLICKER (t1)-VFLICKER (t2).If arithmetic element averages computing, brightness value BRVi=(VRST-VSGN)+(VFLICKER (t1)-VFLICKER (t2))/2.Can observe, in the arithmetic expression of this two brightness value, the error that the voltage level deviation that the brightness value BRVi that arithmetic element 131 produces can erase amplifier AP1 causes.In addition, arithmetic expression H that it should be noted that the impact of the voltage level deviation that other can erase amplifier AP1 also can analogize and be adopted, and even also can utilize other function F, G, by consider and arithmetic expression H between relation, can obtain other forms of brightness value.

Fig. 3 A is the circuit diagram according to the sampling in Fig. 1 of another embodiment of the present invention and comparison circuit.Please refer to Fig. 2 A and Fig. 3 A, sampling is approximately identical to sampling and comparison circuit SCi with comparison circuit SC1b, and its difference is to increase a switching signal generation unit 310.

The first comparison output G and second that switching signal generation unit 310 can couple amplifier AP1 compares between the comparison output OC1 of output H and sampling and comparison circuit SC1b, to compare the relatively voltage quasi position of output H of output G and second, output brightness switching signal BT1b according to first.In other words, when the first voltage quasi position and second that compares output G compares the voltage quasi position exchange of output H, switching signal generation unit 310 can switch the voltage quasi position of brightness transition signal BT1b with responding.

In circuit design, switching signal generation unit 310 can be configured to according to the first voltage quasi position of one at least and produce brightness transition signal BT in the middle of output G and the second comparison output H relatively.More specifically, in certain embodiments, switching signal generation unit 310 can be configured to according to first and compares relatively both voltage quasi position output brightness switching signal BT1b of output H of output G and second.Or in some other embodiment, switching signal generation unit 310 only can be configured to and compares according to first the voltage quasi position output brightness switching signal BT1b that output G and second compares the central one of output H.

In Fig. 3 A, also show the embodiment of a thin portion structure of switching signal generation unit 310.In this embodiment, switching signal generation unit 310 is for utilizing signal shifter SE2 to realize.Signal shifter SE2 has the first switching input I, second and switches input J and exchange output K.The first switching input I of signal shifter SE2 is coupled to first of amplifier AP1 and compares output G, the second switching input J of signal shifter SE2 is coupled to second of amplifier AP1 and compares output H, and the exchange output K of signal shifter SE2 is coupled to the comparison output OC1 of sampling and comparison circuit SC1b.Signal shifter SE2 receiving phase signal ψ, and be coupled to exchange output K according to phase signal ψ control the first switching input I or the second switching input J.

Fig. 3 B is the drive waveforms schematic diagram according to the sampling in Fig. 3 A of one embodiment of the invention and comparison circuit.Please refer to Fig. 2 A, Fig. 2 B, Fig. 3 A and Fig. 3 B, sampling is approximately identical to sampling and comparison circuit SCi with the function mode of comparison circuit SC1b, and its difference is brightness transition signal BT1b.

In the one first phase place period P H1 of phase signal ψ, handshaking device SE2 controls the first switching input I according to phase signal ψ and is coupled to exchange output K.Therefore, when first relatively the voltage quasi position of input E be subject to the impact of ramp signal VRAMP and be less than second relatively during the voltage quasi position of input F, first compares output G and second voltage quasi position that relatively output H exports can exchange, also be the first comparison output G output LOW voltage level, and the second comparison output H output HIGH voltage level.Now, the brightness transition signal BT1b that switching signal generation unit 310 clubs provide can switch to low-voltage level to form negative edge by high voltage level.

In the one second phase place period P H2 of phase signal ψ, handshaking device SE2 controls the second switching input J according to phase signal ψ and is coupled to exchange output K.Therefore, when first relatively the voltage quasi position of input E be subject to the impact of ramp signal VRAMP and be greater than second relatively during the voltage quasi position of input F, first compares output G and second voltage quasi position that relatively output H exports can exchange, also be the first comparison output G output HIGH voltage level, and the second comparison output H output LOW voltage level.Now, the meeting that switching signal generation unit 310 clubs provide switches to low-voltage level to form negative edge by high voltage level.

According to above-mentioned, the present embodiment is applicable to the first latch (as LT11～LT13) and the second latch (as LT21～LT23) that negative edge triggers.If being positive edge, the first latch (as LT11～LT13) and the second latch (as LT21～LT23) trigger, be adjusted at accordingly the second switching input J in the first phase place period P H1 and be coupled to exchange output K, in the second phase place period P H2, the first switching input I is coupled to exchange output K.

Fig. 4 A is according to the present invention more sampling in Fig. 1 of another embodiment and the circuit diagram of comparison circuit.Please refer to Fig. 3 A and Fig. 4 A, sampling is approximately identical to sampling and comparison circuit SC1b with comparison circuit SC1c, and its difference is that switching signal generation unit 410 is for utilizing RS latch RS1 and a logical block 420 to realize.

RS latch RS1 comprises that the first latch input terminal L, the second latch input terminal M, first latch output N and second and latch output O.Logical block 420 comprises the first logic input terminal P, the second logic input terminal Q and logic output terminal R.The first latch input terminal L of RS latch RS1 is coupled in first and compares output G, and the second latch input terminal M of RS latch RS1 is coupled in second and compares output H.The first logic input terminal P of logical block 420 is coupled in first of RS latch RS1 and latchs output N, the second logic input terminal Q of logical block 420 is coupled in second of RS latch RS1 and latchs output O, the logic output terminal R output brightness switching signal BT1c of logical block 420.Wherein, logical block 420 is according to the voltage quasi position (also switching the voltage quasi position of brightness transition signal BT1c) of the voltage quasi position switch logic output R of the first logic input terminal P and the second logic input terminal Q.

In the present embodiment, logical block 420 comprises an anti-or lock NR1, and a plurality of inputs anti-or lock NR1 couple respectively the first logic input terminal P and the second logic input terminal Q, and an output anti-or lock NR1 couples logic output terminal R.

Fig. 4 B is the drive waveforms schematic diagram according to the sampling in Fig. 4 A of one embodiment of the invention and comparison circuit.Please refer to Fig. 2 A, Fig. 2 B, Fig. 4 A and Fig. 4 B, sampling is approximately identical to sampling and comparison circuit SC1b with the function mode of comparison circuit SC1c, and its difference is that first of RS latch RS1 latchs voltage quasi position (respectively with reference to waveform VN and VO) and brightness transition signal BT1c that output N and second latchs output O.

Between a comparable period of the one first phase place period P H1 of phase signal ψ in PCP1, first compares the first output HIGH voltage level of output G meeting, and the first output LOW voltage level of the second comparison output H meeting, now first to latch output N be low-voltage level, and second to latch output O be high voltage level.Then, when first relatively the voltage quasi position of input E be subject to the impact of ramp signal VRAMP and start to be less than second relatively during the voltage quasi position of input F, first compares output G and second voltage quasi position that relatively output H exports can exchange, also be the first comparison output G output LOW voltage level, and the second comparison output H output HIGH voltage level.Now, second latch output O can be controlled by second relatively output H high voltage level and first switch to low-voltage level, and the second low-voltage level that latchs output O can cause first to latch output N and switch to high voltage level after back coupling.Latch output N and can be later than the second latch input terminal O switched voltage level due to first, therefore first latch output N and the second latch input terminal O can temporarily be all low-voltage level, so that form positive pulse wave at brightness transition signal BT1c.

Between a comparable period of the one second phase place period P H2 of phase signal ψ in PCP2, first compares the first output LOW voltage level of output G meeting, and the first output HIGH voltage level of the second comparison output H meeting, now first to latch output N be high voltage level, and second to latch output O be low-voltage level.Then, when second relatively the voltage quasi position of input F be subject to the impact of ramp signal VRAMP and be less than first relatively during the voltage quasi position of input E, first compares output G and second voltage quasi position that relatively output H exports can exchange, also be the first comparison output G output HIGH voltage level, and the second comparison output H output LOW voltage level.Now, first latch output N can be controlled by first relatively output G low-voltage level and first switch to low-voltage level, and the first low-voltage level that latchs output N can cause second to latch output O and switch to high voltage level after back coupling.Latch output O and can be later than the first latch input terminal N switched voltage level due to second, therefore first latch output N and the second latch input terminal O can temporarily be all low-voltage level, so that brightness transition signal BT1c forms positive pulse wave.

According to above-mentioned, the present embodiment is applicable to the first latch (as LT11～LT13) and the second latch (as LT21～LT23) that high levle triggers.If the first latch (as LT11～LT13) and the second latch (as LT21～LT23) are low level, trigger, can configure accordingly inverter between the output of anti-or lock NR1 and logic output terminal R or utilization or lock are realized logical block 420.

Fig. 5 is according to the sampling in Fig. 1 of another embodiment again of the present invention and the circuit diagram of comparison circuit.Please refer to Fig. 2 A and Fig. 5, sampling is approximately identical to sampling and comparison circuit SC1a with comparison circuit SC1d, its difference is that the position of handshaking device SE3 moves on between the first sampling switch SWS1, the second sampling switch SWS2 and amplifier AP1, and wherein the running of handshaking device SE3 is similar in appearance to handshaking device SE1.More specifically, the first sampling switch SWS1 is coupled between second end and reference voltage VR of the first capacitor C 1.The second sampling switch SWS2 is coupled between second end and reference voltage VR of the second capacitor C 2.Handshaking device SE3 is coupled in the second end of the first capacitor C 1, between the second comparison input F of the first comparison input E of the second end of the second capacitor C 2, amplifier AP1 and amplifier AP1.According to circuit running, the circuit running of comparison circuit SC1d is same as sampling and comparison circuit SC1a.Other structures can, with reference to the explanation of Fig. 2 A and 2B, not repeat them here with the correlative detail in work.In addition, similarly, the embodiment of Fig. 5 also can increase by a switching signal generation unit and extend to different embodiment in the rear end of amplifier AP1, and its structure can, with reference to the explanation of Fig. 3 A to 4B, not repeat them here with the correlative detail in work.

" coupling " word using in this case specification full text (comprising claim) can refer to any direct or indirect connection means.For example, if describe first device in literary composition, be coupled in the second device, should be construed as this first device and can directly be connected to this second device, or this first device can be connected to indirectly by other devices or certain connection means this second device.In addition, " signal " word using in this case specification full text (comprising claim), can refer to single signal, or a plurality of signal.

In sum, the imageing sensor of the embodiment of the present invention and column analog-to-digital converter thereof, a ramp signal and an initial signal that one initial voltage of its photosensitive pixel according to respective column and a luminance voltage and a ramp signal maker provide produce a brightness transition signal, and the first latch according to the corresponding brightness transition signal count results that latching accumulator provides in a first period to export one first brightness latched value, the second latch according to the corresponding brightness transition signal count results that latching accumulator provides in a second phase to export one second brightness latched value, arithmetic element is calculated a brightness value of the photosensitive pixel of this respective column according to the first brightness latched value of correspondence and the second brightness latched value of correspondence.Whereby, can reduce the impact that circuit noise causes, the correctness of the brightness value being sensed to improve.

Finally it should be noted that: each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit above; Although the present invention is had been described in detail with reference to aforementioned each embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or some or all of technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.

Claims (24)

1. a column analog-to-digital converter, is suitable for having a pel array of the photosensitive pixel of several column, it is characterized in that, comprising:

One counter, foundation one clock signal is to provide a count results;

One ramp signal maker, provides a ramp signal according to this clock signal, and an initial signal is provided;

One sampling and comparator array, there is a plurality of samplings and comparison circuit, in the middle of those samplings and comparison circuit, each is respectively according to this ramp signal and this initial signal, and an initial voltage and a luminance voltage of the photosensitive pixel of a respective column in those photosensitive pixels, export a brightness transition signal;

One first latchs array, there are a plurality of the first latchs, wherein in the middle of those first latchs, each couples respectively this counter, with within a first period, response this brightness transition signal that a corresponding person is exported in the middle of those samplings and comparison circuit, becomes one first brightness latched value and this count results is latched;

One second latchs array, there are a plurality of the second latchs, wherein in the middle of those second latchs, each couples respectively this counter, with within a second phase different from this first period, response this brightness transition signal that a corresponding person is exported in the middle of those samplings and comparison circuit, becomes one second brightness latched value and this count results is latched; And

One arithmetic element, coupling this first latchs array and this second and latchs array, with receive in the middle of those first latchs each this first brightness latched value and those the second latchs in the middle of each this second brightness latched value, an and brightness value that calculates the photosensitive pixel of this respective column according to this first brightness latched value receiving and this second brightness latched value.

2. column analog-to-digital converter according to claim 1, is characterized in that, during this first period is the first phase place of a phase signal, and during this second phase is one second phase place of a phase signal.

3. column analog-to-digital converter according to claim 1, is characterized in that, this arithmetic element is to calculate a summation of this first brightness latched value receive and this second brightness latched value as this brightness value of the photosensitive pixel of this respective column.

4. column analog-to-digital converter according to claim 1, is characterized in that, this arithmetic element is to calculate a mean value of this first brightness latched value receive and this second brightness latched value as this brightness value of the photosensitive pixel of this respective column.

5. column analog-to-digital converter according to claim 1, it is characterized in that, this arithmetic element comprises a plurality of sub-arithmetic elements, in the middle of each is coupled to respectively a corresponding person and the central corresponding person of those the second latchs in the middle of those first latchs, this a little arithmetic element is in order at one time, according to those the first brightness latched values of those the first latchs and those the second brightness latched values of those the second latchs, parallel computing goes out those brightness values of the photosensitive pixel of those row.

6. column analog-to-digital converter according to claim 1, it is characterized in that, this arithmetic element is in order to sequentially in different time, respectively according to this first brightness latched value of the one in the middle of those first latchs, with this second brightness latched value of one in the middle of those second latchs, and calculate this brightness value of the photosensitive pixel of the one in those broomrapes.

7. column analog-to-digital converter according to claim 1, is characterized in that, in the middle of those samplings and comparison circuit, each comprises:

One first compares switch, and it has first end and is coupled to this ramp signal, and has one second end;

One second compares switch, and it has first end and is coupled to this initial signal, and has one second end;

One first electric capacity, it has this second end and this luminance voltage that first end is coupled to this first comparison switch, and has one second end;

One second electric capacity, it has this second end and this initial voltage that first end is coupled to this first comparison switch, and has one second end;

One amplifier, it has first and compares relatively input of input and second, and first relatively output and the second output relatively, this brightness transition signal is according to this first output and this second voltage quasi position of one at least and producing in the middle of output relatively relatively;

One handshaking device, be coupled between first and second electric capacity and this amplifier, to control this second end of this first electric capacity and this second end of the second electric capacity, be this first relatively input and this second input relatively that is coupled to respectively this amplifier, or coupling is to this second input and this first input relatively relatively of this amplifier;

One first sampling switch, is coupled between this first comparison input and a reference voltage of this amplifier; And

One second sampling switch, is coupled between this second comparison input and this reference voltage of this amplifier.

8. column analog-to-digital converter according to claim 7, is characterized in that, also comprises:

One luminance voltage switch, is coupled between this luminance voltage and this first end of this first electric capacity; And

One initial voltage switch, is coupled between this initial voltage and this first end of this second electric capacity.

9. column analog-to-digital converter according to claim 8, it is characterized in that, this luminance voltage switch and initial voltage switch be between the sampling date during one first phase place of a phase signal in conducting in proper order, and between the comparable period during this first phase place of this phase signal and internal cutting off during one second phase place of this phase signal.

10. column analog-to-digital converter according to claim 7, it is characterized in that, in between the comparable period during one first phase place of a phase signal, this handshaking device is this second end of this second end of this first electric capacity and the second electric capacity to be coupled to respectively to this first comparison input and this second comparison input of this amplifier, and between the comparable period during one second phase place of this phase signal, this handshaking device is this second end of this second end of this first electric capacity and the second electric capacity to be coupled to respectively to this second comparison input and this first comparison input of this amplifier.

11. column analog-to-digital converters according to claim 10, it is characterized in that, in between the sampling date before the position during this first phase place of this phase signal is between this comparable period, this first and second sampling switch conducting, and this first and second comparison switch cuts off, and between this comparable period between this comparable period during this first phase place of this phase signal and during this second phase place of this phase signal, this first and second sampling switch cuts off, and this first and second switch conduction relatively.

12. column analog-to-digital converters according to claim 7, it is characterized in that, when this first relatively the voltage quasi position of input higher than this second relatively during the voltage quasi position of input, this the first comparison output output one first level, this the second comparison output output one second level, when this, first relatively the voltage quasi position of input is low or equal this second relatively during the voltage quasi position of input, this the first comparison output is exported this second level, and this second comparison output is exported this first comparison level.

13. column analog-to-digital converters according to claim 7, it is characterized in that, in the middle of those samplings and comparison circuit, each also comprises: a switching signal generation unit, couple between this first comparison output of this amplifier and a comparison output of this second comparison output and this sampling and comparison circuit, with the voltage quasi position according to this first comparison output and this first comparison output, export this brightness transition signal.

14. column analog-to-digital converters according to claim 13, is characterized in that, this switching signal generation unit is when the voltage quasi position of this first comparison output and this second comparison output equates in fact, switches the voltage quasi position of this brightness transition signal.

15. column analog-to-digital converters according to claim 13, is characterized in that, this switching signal generation unit comprises:

One RS latch, have one first latch input terminal be coupled in this first relatively output, one second latch input terminal be coupled in this second relatively output, one first latch output and one second and latch output.

16. column analog-to-digital converters according to claim 15, is characterized in that, this switching signal generation unit also comprises:

One logical block, there is one first logic input terminal and be coupled in that this first latchs output, one second logic input terminal is coupled in this second latch input terminal, and a logic output terminal, wherein this logical block is switched the voltage quasi position of this logic output terminal according to the voltage quasi position of this first logic input terminal and this second logic input terminal.

17. column analog-to-digital converters according to claim 16, it is characterized in that, this logical block comprises an anti-or lock, and wherein these a plurality of inputs anti-or lock couple respectively this first logic input terminal and this second logic input terminal, and this output anti-or lock couples this logic output terminal.

18. column analog-to-digital converters according to claim 13, is characterized in that, this switching signal generation unit comprises:

One signal shifter, it has this first comparison output that the first switching input is coupled to this amplifier, be coupled to this second output relatively of this amplifier with the second switching input, and an exchange output, it is coupled to this and first switches input and within this second phase, be coupled to this and second switch input within this first period.

19. column analog-to-digital converters according to claim 1, is characterized in that, in the middle of those samplings and comparison circuit, each also comprises:

One handshaking device, comprise one first exchange input and one second exchange input, and one first exchange output exchange output with one second, when this sampling and comparison circuit are operated under a first mode, this first exchange input and this second exchange input are coupled to respectively this first exchange output and this second exchange output, when this sampling and comparison circuit are operated under one second pattern, this first exchange input and this second exchange input are coupled to respectively this second exchange output and this first and exchange output; And

One amplifier, comprise that one first compares relatively input of input and one second, be coupled to respectively this first exchange output and this second exchange output, and comprise that one first compares relatively output of output and one second, this brightness transition signal is according to this first voltage quasi position of one at least and producing in the middle of output and this second comparison output relatively, wherein

In between the sampling date within this first period, this handshaking device is operated in this first mode, so that this first comparison input and this second comparison input are to be coupled to respectively this luminance voltage and this initial voltage,

In between the comparable period within this first period, handshaking device is operated in this first mode, so that this first comparison input and this second comparison input are to be coupled to respectively this ramp signal and this initial signal, and

In between the comparable period within this second phase, handshaking device is operated in this second pattern, so that this first comparison input and this second comparison input are to be coupled to respectively this initial signal and this ramp signal.

20. column analog-to-digital converters according to claim 19, is characterized in that, in the middle of those samplings and comparison circuit, each also comprises:

One first electric capacity, has first end and the second end, and this second end is coupled to this first exchange input;

One second electric capacity, has first end and the second end, and this second end is coupled to this second exchange input;

One first compares switch, is coupled between this ramp signal and this first end of this first electric capacity; And

One second compares switch, is coupled between this initial signal and this first end of this second electric capacity.

21. column analog-to-digital converters according to claim 20, is characterized in that, in the middle of those samplings and comparison circuit, each also comprises:

One luminance voltage switch, is coupled between this luminance voltage and this first end of this first electric capacity; And

One initial voltage switch, is coupled between this initial voltage and this first end of this second electric capacity.

22. column analog-to-digital converters according to claim 19, wherein in the middle of those samplings and comparison circuit, each more comprises:

One first sampling switch, is coupled between this first comparison input and a reference voltage of this amplifier; And

One second sampling switch, is coupled between this second comparison input and this reference voltage of this amplifier.

23. column analog-to-digital converters according to claim 19, it is characterized in that, within this first period with this second phase in, this sampling and comparator array are to be operated in respectively this first mode and this second pattern, under this first mode and this second pattern, this brightness transition signal is to have different functional relations from this luminance voltage.

24. 1 kinds of imageing sensors, is characterized in that, comprising:

One pel array, it has the photosensitive pixel of several column; And

One column analog-to-digital converter according to claim 1, is coupled to this pel array.

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