CN103595373A - Nine-component mixed signal generator and generation method of nine-component mixed signal - Google Patents

Abstract

The invention discloses a nine-component mixed signal generator and a generation method of a nine-component mixed signal. The nine-component mixed signal comprises a direct current component, a pulse component and seven sine components, and the amplitude, the frequency, the pulse width and the initial phase of each component can be set. A waveform generation circuit comprises a single FPGA and an analog circuit, wherein the analog circuit comprises four links of amplitude transformation, impulse wave transformation, sine wave mixing and full-component overlapping, and the FPGA and the analog circuit are provided with 15 logic signal connecting lines. The waveform generation circuit does not use a storage or a DAC or an analog multiplier, and is low in hardware cost of circuits. The nine-component mixed signal generator permits the input of four external signals in order to increase the total number of the components. When multiple groups of analog circuits are controlled by the single high-capacity FPGA and work, the nine-component mixed signal generator can be upgraded to be a multi-path nine-component mixed signal generator, and signals among channels can be synchronized.

Description

A nine-component mixed signal generator and nine-component mixed signal generation method

(1) Technical field

The invention relates to a nine-component mixed signal generator. The mixed signal includes 1 direct current component, 1 pulse component and 7 sine components, in particular to a low-cost mixed signal generator with complex waveforms and independent superimposition of multiple components.

(2) Background technology

Arbitrary wave generators have been widely used in electronic testing and excitation simulation because they can generate complex waveforms, and have become a basic electronic measuring instrument. The waveform generation circuit of the arbitrary waveform generator includes three parts: external interface circuits (such as USN, LAN, etc.) for waveform data transmission, digital logic circuits, and analog circuits. The digital logic circuit is composed of control logic, waveform memory, phase accumulator and other units to form a DDS circuit, which outputs waveform data to the analog circuit part at a higher rate; the analog circuit part consists of a waveform conversion DAC, an amplitude setting DAC, a low-pass filter, and a multiplier The DAC receives the waveform data output by the digital circuit part at the same rate.

There are three main technical improvements of arbitrary waveform generators: one is the improvement of waveform conversion DAC conversion rate and related high-speed circuit design, the other is the expansion of waveform storage capacity, and the third is arbitrary waveform generation methods and waveform data transmission. There are two main sources of arbitrary waveform data: one is the real signal time series collected directly, and the other is the time series sampled at time intervals of complex time functions.

Signals in nature are complex, often a mixture of independent signals from multiple sources; according to the principle of Fourier transform, a single complex periodic signal can be expanded into the sum of multi-level sine harmonics. When natural signals are simulated by electrical signals, they often have DC components and pulsations, so a mixture of DC components, multiple pulse components, and sinusoidal components can be used to simulate real natural signals well. However, when an arbitrary waveform generator simulates a complex waveform formed by mixing multiple components, its inability is due to major defects in the ease of operation and the authenticity of the waveform.

When one or more parameters of the mixed signal need to be changed, all the arbitrary waveform data will be changed. The computer first needs to recalculate and generate new waveform data, and then transmit the new waveform data to the arbitrary wave generator through the external interface, and the arbitrary wave generator transforms the new waveform data into complex waveforms. Every time a parameter is changed, the above-mentioned process needs to be repeated. The operation is cumbersome and requires computer assistance, which takes a long time to change the parameters. Without computer assistance, it is almost impossible to change the parameters of the mixed signal.

A mixed signal formed by several independent components can be regarded as a random signal in time. However, due to the limited capacity of the waveform memory of the arbitrary waveform generator, the output arbitrary waveform is still a periodic signal in time, and the quantization of complex time functions will produce truncation errors. When the arbitrary wave generator outputs a signal for a long time, due to the periodicity of the waveform and the accumulation of truncation errors, compared with the ideal value of the mixed signal superimposed by independent components, distortion will occur. The longer the time, the greater the distortion.

The required multi-component mixed signal can be simulated by superimposing the output signals of multiple function/arbitrary wave generators. The increase of instruments will bring a lot of inconvenience; the time base of each instrument is different, and the increase of time will also cause the distortion of the superimposed signal waveform to increase.

(3) Contents of the invention

The purpose of the present invention is to provide a kind of digital circuit part that waveform generation does not need to use memory, only needs to use single-chip FPGA; Analog circuit part needn't use integrated DAC and analog multiplier, only needs to use common operational amplifier, analog multi-way switch, and Resistors, capacitors, inductance components, nine-component mixed-signal generator with low hardware cost.

The purpose of the present invention is achieved in that it includes a programmable logic device and an analog circuit unit, and the programmable logic device is provided with a microprocessor interface unit, a clock generation circuit unit, an amplitude control logic unit, a pulse control logic unit and 7 The phase-frequency control logic unit, the microprocessor interface unit is connected to the clock generation circuit unit, the microprocessor interface unit, and the clock generation circuit unit are respectively connected to the amplitude control logic unit, the pulse control logic unit and 7 phase-frequency control logic units, and the clock generation circuit The unit, the amplitude control logic unit, the pulse control logic unit and the seven phase frequency control logic units are respectively connected to the analog circuit unit.

The present invention also has some technical characteristics:

1. The clock generation circuit unit includes a digital phase-locked loop frequency multiplication unit, an even number frequency division unit and a counter frequency division unit, the external crystal oscillator is connected to the digital phase-locked loop frequency multiplication unit, and the digital phase-locked loop frequency multiplication unit is connected to the even number division unit respectively. The frequency unit and the counter frequency division unit, the even number frequency division unit and the counter frequency division unit are respectively connected to the amplitude control logic unit, the pulse control logic unit and 7 phase frequency control logic units, and the even number frequency division unit is connected to the analog circuit unit;

2. The amplitude control logic unit includes a nine-component amplitude parameter setting circuit, a 4-to-1 bus data switch and a data comparator, the microprocessor interface unit is connected to the amplitude parameter setting circuit, and the amplitude parameter setting circuit is connected to a 4-to-1 bus data switch , the 4-to-1 bus data switch is connected to the data comparator, the counter frequency division unit is respectively connected to the 4-to-1 bus data switch and the data comparator, and the data comparator is connected to the analog circuit unit;

3. The pulse control logic circuit includes a pulse parameter latch, a pulse logic NC oscillator, a pulse logic phase adder and a data comparator, the digital phase-locked loop frequency multiplication unit is connected to the pulse logic NC oscillator, and the pulse logic NC oscillator The pulse logic phase adder is connected to the pulse logic phase adder, the pulse logic phase adder is connected to the data comparator, and the data comparator is connected to the analog circuit unit;

4. The phase-frequency control logic unit includes a phase-frequency parameter latch, a phase-frequency logic numerical control oscillator and a phase-frequency logic phase adder, the digital phase-locked loop frequency multiplication unit is connected to the phase-frequency logic numerical control oscillator, and the phase-frequency logic The digitally controlled oscillator is connected to the phase-frequency logic phase adder, and the phase-frequency logic phase adder is connected to the analog circuit unit;

5. The analog circuit unit includes a component amplitude conversion unit, a pulse wave conversion unit, a sinusoidal component mixing unit, and a full component superposition unit connected in sequence; the component amplitude conversion unit includes a first two-choice analog switch, a first active Source low-pass filter, the second one-of-two analog switch, the second active low-pass filter, the third one-of-two analog switch, the third active low-pass filter, dual four-one analog switch and the sample-and-hold device, the data comparator of the amplitude control logic unit is respectively connected to the first two-to-one analog switch, the second two-to-one analog switch and the third two-to-one analog switch, and the first two-to-one analog switch , the second one-two analog switch and the third one-two analog switch are respectively connected to the first active low-pass filter, the second active low-pass filter and the third active low-pass filter , the first active low-pass filter is connected to the full component superposition unit, the second active low-pass filter and the third active low-pass filter are connected to the dual-four-selection-one analog switch, and the dual-four-selection-one analog switch is connected to Sample holder; the pulse wave conversion unit includes a pulse wave conversion differential amplifier and a pulse wave conversion two-choice analog switch, the sample holder is connected to the pulse wave conversion two-choice one analog switch, and the pulse wave conversion two-choice analog switch is connected to the pulse wave conversion Differential amplifier, pulse control logic unit and 7 phase-frequency control logic units are respectively connected to pulse wave conversion two-choice analog switch; sine component mixing includes the first-stage adder connected in sequence, the first-stage passive low-pass filter and the in-phase Amplifier, sinusoidal component two-choice analog switch, sinusoidal component differential amplifier and second-stage passive low-pass filter and non-inverting amplifier, pulse wave conversion differential amplifier is connected to the first-stage adder and full-component superposition unit, and the second stage The passive low-pass filter and the non-inverting amplifier are connected to the full-component superposition unit.

Another object of the present invention is to overcome the deficiencies in the prior art and provide a method for generating a nine-component mixed signal. The mixed signal is composed of 1 DC component, 1 pulse component, and 7 sinusoidal components. The amplitude and frequency of each component , pulse width, and initial phase can be set independently. The signal generating circuit is composed of an analog circuit and a single-chip FPGA. There is no need to use integrated DAC and analog multiplier in the analog circuit, and the FPGA does not need to use memory resources. The analog circuit can be divided into four links: amplitude transformation, pulse wave transformation, sine component mixing, and full component superposition. FPGA has built-in microprocessor interface unit, clock generation circuit, amplitude control logic unit, pulse control logic unit, and 7 phase frequency control logic units. The model of FPGA can be determined according to the parameter index of each component. Both the phase-frequency control logic and the pulse control logic require the use of a numerically controlled oscillator with phase preset function. Its working principle is discussed in detail in DDS waveform synthesis technology, so it can be used directly.

The nine-component mixed signal generation method of the present invention comprises the following steps:

(1) The interface unit converts the serial bus from the microprocessor into the internal parallel bus BUS to set all component parameters; the interface unit also introduces the global reset signal SRST from the microprocessor.

(2) The clock generation unit generates three kinds of clock signals: the first one is the high-frequency clock signal Fsys, which is generated after the external crystal oscillator clock is multiplied by the digital phase-locked loop, and is used as all phase-frequency control logic units and pulse control logic units. System clock; the second is the base frequency square wave signal FBAS obtained by Fsys through even frequency division, as the difference frequency clock during the sine component mixing conversion; the third is the clock array Fout obtained by Fsys after frequency division by the counter [27..0], as a control signal for the amplitude control logic unit.

(3) The amplitude control logic unit outputs a logic signal with a fixed frequency and a preset pulse width, representing the amplitude PWMA of the DC component; outputs two logic signals PWMB and PWMC with a fixed frequency and four pulse widths that change sequentially at equal time intervals (Characterize the amplitude of 1 pulse component and 7 sinusoidal components); output 2 channel selection signals CH[1..0] and 1 hold enable signal OUTE. Fout[27..26] is used as the selection signal of 4 channels to control CH[1..0], Fout[25] is the sampling enable signal OUTE, and the low bit of Fout determines the frequency of the amplitude logic signal.

The internal bus BUS sets 9 amplitude parameters. The low bit of Fout is compared with the amplitude parameter of the DC component, and the output of the data comparator (less than or equal to the logical relationship) PWMA signal represents the DC component; the channel selection signal CH[1..0] controls two 4 to 1 bus data switches, and the two groups Characterize each of the 4 amplitude data into 2 variable data streams respectively, the low bits of Fout are compared with the 2 variable data streams respectively, the output of the 2 data comparators (less than or equal to the logical relationship) PWMB and PWMC signal frequency is fixed, pulse Width changes at equal time intervals.

(4) The pulse control logic circuit is composed of a numerically controlled oscillator, a phase adder, and a data comparator. The working clock of the numerical control oscillator is Fsys, which is reset synchronously by the SRST signal, and the setting parameters are frequency word, phase word, and pulse width word; the high-order output of the numerical control oscillator is added to the phase word; the high-order output of the adder is compared with the pulse width word, The less than or equal output of the data comparator is the required pulse logic signal SW ₀ ; the frequency word, phase word and pulse width word are set by the microprocessor.

(5) The circuit structures of the seven phase-frequency control logic units are exactly the same, and seven phase-frequency logic signals SW _{1 ~ 7} are generated. The phase-frequency control logic circuit is composed of a numerical control oscillator, a phase adder, etc.; the working clock of the numerical control oscillator is Fsys, which is reset synchronously by the SRST signal, and the setting parameter is a frequency word; the high-order output of the numerical control oscillator is added to the phase word, and the adder The highest bit output is the phase-frequency logic signal; the frequency word and phase word are set by the microprocessor.

(6) In the analog circuit, the logic signal PWMA controls the two inputs of the first two-choice analog switch to be connected to the positive and negative references respectively, and the common terminal signal of the switch is connected to the first active low-pass filter, and the filter output VDC represents The DC component of the mixed signal; the logic signal PWMB controls the two inputs of the second alternative analog switch to be connected to the positive reference and ground respectively, and the switch common terminal signal is connected to the second active low-pass filter, and the output of the filter represents 4 components of the mixed signal; the logic signal PWMC controls the two inputs of the third alternative analog switch to be connected to the positive reference and ground respectively, and the switch common terminal signal is connected to the third active low-pass filter, and the output of the filter is also The other 4 components of the mixed signal are characterized. Under the control of the channel selection signal CH[1..0] and the conduction enable signal OUTE, the two common terminals of the dual 4-to-1 analog switch are respectively connected to the second and third active low-pass filter outputs, analog The 8 outputs of the switch are respectively connected to the sample-and-hold devices (composed of resistors, capacitors and voltage followers) to generate 8 DC signals V _{0 ~ 7} . This part of the analog circuit can be regarded as a component amplitude conversion link.

The common terminals of the 8 alternative analog switches are respectively connected to 8 DC signals V _{0 ~ 7} , and the two outputs of each analog switch are used as the two inputs of each differential amplifier, and the output signals of the differential amplifier are respectively AS _{0 ~ 7} , the driving signals of the 8 analog switches are SW _{0 ~ 7} respectively. AS ₀ represents the pulse component of the mixed signal, and AS _{1 ~ 7} represent the 7 sinusoidal components of the mixed signal. This part of the circuit can be regarded as a pulse wave transformation link.

In the analog circuit of the present invention, AS _{1 to 7} are added with equal weights by the first-stage adder, and the weight resistance of the adder adopts an 8-resistor integrated exclusion to ensure equal weights. The superimposed signal is filtered by the first-stage passive low-pass filter, amplified in the same phase, and then sent to the common terminal of the two-choice analog switch. The basic frequency square wave signal FBAS controls the two-choice analog switch. The two outputs of the analog switch As the two inputs of the differential amplifier respectively, the output of the differential amplifier is SINS after the second-stage passive low-pass filter and in-phase amplification, and SINS mixes all sinusoidal components. This part of the circuit can be regarded as a sine component mixing link.

In the analog circuit of the present invention, the second-stage adder has 7 inputs: 1 is the mixed signal SINS of the sinusoidal component, 1 is the pulse component AS0, 1 is the DC component VDC, and the other 4 inputs are used as external The signal input terminal is to realize the superposition of more components; each input equal weight of this adder, the weight resistor of the adder adopts an 8 resistor integrated exclusion, to realize equal weight, the output of the adder is exactly the nine that will take place in the present invention Component mixed signal SMIX. This part of the analog circuit can be regarded as a full component superposition link.

In the analog circuit of the present invention, in order to generate the mixed signal of 7 sinusoidal components, a 2-stage passive low-pass filter is used for filtering. According to the signal filtering theory, it can be seen that the signal filtered by the first-stage filter can be regarded as the superposition of seven sinusoidal components; the frequency of each sinusoidal component is the same frequency as the phase-frequency signal output by the phase-frequency control logic unit, the amplitude ratio changes, and the phase shift and It is determined by its own frequency and the parameters of the first-stage filter; the high-order harmonics of each sinusoidal component have a large attenuation and can be regarded as noise. The signal filtered by the second-stage filter can be regarded as seven sinusoidal components after frequency conversion and superposition; the frequency of each sinusoidal component is the difference between the phase-frequency logic signal output by the phase-frequency control logic unit and the frequency of the fundamental square wave FBAS, The amplitude of each component changes proportionally, and the phase shift of each component is determined by its own frequency and the parameters of the two-stage passive low-pass filter.

When the analog circuit generating the nine-component mixed signal described in the present invention is regarded as a mixed signal analog conversion unit, a plurality of mixed signal analog conversion units can work in parallel under the support of a single chip FPGA and a microprocessor to become a multi-channel Nine-component mixed-signal generator. All components of each channel are synchronized by SRST and use the same system clock, enabling multi-channel mixed-signal synchronization. At this time, the sinusoidal components of the channel can continue to be superimposed through the external input terminal, up to 35 sinusoidal components.

Through the analysis of the analog circuit, it can be found that the amplitude gain of the DC component, the pulse component, and the sinusoidal component are different, and the amplitude-frequency characteristics and phase-frequency characteristics of each sinusoidal component are consistent. Therefore, the parameters that need to be calibrated include: DC component gain, pulse component gain, sinusoidal component gain, amplitude-frequency characteristics of the sinusoidal component, and phase-frequency characteristics of the sinusoidal component. The calibration process is as follows:

The amplitude gain calibration process of the DC component is as follows: set the amplitude of all components to zero, the frequency of each sine component to the upper limit, and the frequency of the pulse component to 0 through the microprocessor; change the amplitude code value of the DC component, and measure the DC output of the mixed signal with a digital multimeter. The voltage value can be converted to determine the gain factor of the DC component.

The amplitude gain calibration process of the sine component is as follows: through the microprocessor, the amplitude of all components is zero, the frequency of each sine component is the upper limit, and the frequency of the pulse component is 0; the amplitude code value of the 7th channel is changed, and the frequency of SW ₇ is the fundamental frequency. Wave FBAS frequency plus 1kHz; use a digital multimeter to measure the AC voltage value of the mixed signal output, and the gain factor of the AC component can be determined after conversion.

The calibration process of the amplitude-frequency characteristics of the sine component is as follows: through the microprocessor, the amplitude of all components is zero, the frequency of the sine component is the upper limit, the frequency of the pulse component is 0, and the amplitude of the 7th channel is full scale; the constantly changing SW ₇ frequency value, The frequency of SW ₇ is increased by a specific step value (such as 1kHz) on the basis of the fundamental frequency square wave FBAS frequency. Use an oscilloscope to measure the AC voltage value of the mixed signal output at different frequencies. After conversion, the amplitude-frequency characteristics of the sinusoidal signal can be determined. .

The calibration process of the phase-frequency characteristic of the sine component is as follows: through the microprocessor, the amplitude of all components is zero, the frequency of SW _{1 ~ 5} is the upper limit, the frequency of the pulse component is 0, the amplitude of the 7th channel is full scale, and the frequency of SW _{1 ~ 7} is The initial phase is 0. The frequency of SW ₇ is based on the frequency of the fundamental square wave FBAS and increases with a specific step value (such as 1kHz). The frequency of SW ₆ is the frequency of SW ₇ minus the frequency of the fundamental square wave FBAS. Every time the frequency of SW ₇ is set , SRST synchronizes once, use an oscilloscope to measure the phase difference between the mixed signal output and SW6 under different frequency conditions (the two are the same frequency), so as to determine the phase-frequency characteristics of the sinusoidal component.

The advantage of the present invention is also that: the digital circuit part of waveform generation does not need to use a memory, but only needs to use a single-chip FPGA; , capacitance, and inductance components, so the hardware cost of the nine-component mixed signal generator described in the present invention is low.

(4) Description of drawings

Fig. 1 is an overall block diagram of a nine-component mixed signal generator implementing the present invention.

Fig. 2 is a functional block diagram of the amplitude control logic unit built into the single-chip FPGA in Fig. 1 .

FIG. 3 is a functional block diagram of a pulse control logic unit built into a single-chip FPGA in FIG. 1 .

FIG. 4 is a functional block diagram of the phase-frequency control logic unit built into the single-chip FPGA in FIG. 1 .

Fig. 5 is a functional block diagram of the steps of amplitude conversion and pulse wave conversion in the analog circuit of Fig. 1 .

Fig. 6 is a functional block diagram of the sine component mixing and full component superposition link in the analog circuit of Fig. 1 .

Fig. 7 is an overall block diagram of a two-way nine-component mixed signal generator.

(5) Specific implementation methods

Two preferred implementation modes of the present invention will be introduced below with reference to the accompanying drawings.

Embodiment one:

In conjunction with Fig. 1, it is the first preferred embodiment of the present invention. The mixed signal is composed of 1 DC component, 1 pulse component, and 7 sine components superimposed, and there are 9 components in total. The waveform generation circuit is composed of a single chip EP2C5T144 and analog circuits. In the FPGA, the microprocessor sets all the component parameters and provides the global synchronous signal SRST through the interface circuit. The crystal oscillator clock outputs a high-frequency system clock Fsys after being frequency-multiplied by a digital phase-locked loop. Fsys is usually 280MHz, which provides the same system clock for the pulse control logic unit and phase-frequency control logic unit; Fsys generates a base frequency of 140kHz after even frequency division The square wave signal FBAS is used as the difference frequency signal required for the sine component mixing in the analog circuit; the clock array Fout[27..0] obtained by Fsys after frequency division by the 28Bit binary counter is used as the control signal of the amplitude control logic unit.

Figure 2 is a schematic diagram of the structure of the amplitude control logic unit in Figure 1. The working principle of the circuit is as follows: the clock array Fout[15..0] is compared with the 16Bit DC amplitude word, and the output of the 16Bit data comparator is less than or equal to PWMA, which is used for Characterizes the DC magnitude. The clock array Fout[27..26] controls two 4-to-1 data switches with a data width of 16Bit, and turns eight 16Bit data representing one pulse component amplitude and seven sine component amplitudes into two 16Bit variable data streams ;The clock array Fout[15..0] is compared with two 16Bit variable data streams respectively, and the two 16it data comparators are less than or equal to output PWMB, PWMC, PWMB and PWMC have fixed frequency, pulse width and other time intervals Change in turn; Fout[27..26] output as channel selection signal CH[1..0], Fout[25] output as sampling enable OUTE signal.

Fig. 3 is a schematic structural diagram of the pulse control logic unit in Fig. 1, and its working principle of the circuit is as follows: the parameter setting circuit sets the 40Bit frequency word, the 12Bit phase word and the 10Bit pulse width word; the 40Bit frequency word is used as the numerical control oscillator input, its The working clock is Fsys, which is reset synchronously by the SRST signal; the high 12Bit output of the numerical control oscillator is added to the 12Bit phase word; the high 10Bit of the adder is compared with the pulse width of 10Bit, and the less than or equal output of the comparator is the pulse logic signal SW ₀ ; The normal operating frequency range of SW ₀ is 0 ~ 100kHz, the frequency resolution is better than 1mHz, the initial phase resolution is better than 0.1 degree, and the pulse width resolution is better than 0.1%.

FIG. 4 is a schematic diagram of the circuit structure of a single phase-frequency control logic unit in FIG. 1 , and there are 7 phase-frequency control logic units in the FPGA. The working principle of the phase frequency control logic unit circuit is as follows: the parameter setting circuit sets the 40Bit frequency word and the 12Bit phase word; the 40Bit frequency word is used as the input of the numerical control oscillator, and its working clock is Fsys, which is reset synchronously by the SRST signal; the high frequency word of the numerical control oscillator The 12Bit output is added to the 12Bit phase word; the highest bit output of the adder is the phase frequency logic signal. The output SW _{1 ~ 7} of the 7 phase frequency control logic units has a working frequency range of 140kHz ~ 240kHz, a frequency resolution better than 1mHz, and an initial phase resolution better than 0.1 degree.

Fig. 5 is a schematic block diagram of the amplitude conversion and pulse wave conversion links in the analog circuit of Fig. 1, and Fig. 6 is a schematic block diagram of the sinusoidal component mixing and full component superposition links in the analog circuit of Fig. 1, and the working principle of the four link circuits. Discuss in detail. The passband frequency of the first-stage 9-order passive elliptic filter is 150 kHz, and the pass-band frequency of the second-stage 9-order passive elliptic filter is 110 kHz. The analog circuit part uses 4 pieces of three-way two-to-one analog switches (such as 74HC4053), one double-four-to-one analog switch (such as 74HC4052), 5 pieces of four op amps (such as AD8513), 2 exclusions (8 resistor integrated package).

In the implementation of the above-mentioned nine-component mixed signal generator, it is necessary to calibrate the gain of the DC component, the pulse component, and the sinusoidal component, and the calibration method has been discussed in detail in the invention part.

Embodiment two:

Referring to FIG. 7 , it is a second preferred implementation mode of the present invention, which can generate a two-way mixed signal. Compared with Figure 2, in the single-chip FPGA in this figure, the number of amplitude control logic units, pulse control logic units, and phase frequency control logic units are all doubled, so the logic resources used are almost doubled, and EP2C5T144 can still be implemented. Each analog circuit in this figure is identical to the analog circuit in Figure 2. Since each component of the two-way mixed signal uses the same clock Fsys and the same global synchronous SRST, the two-way mixed signal can be synchronized. Its calibration method is basically the same as the calibration method described for the single-channel mixed signal generator.

The above are only specific embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (7)

1. a component mixed signal generator, it is characterized in that: it is to consist of analog circuit and monolithic programmable logic device, programmable logic device is embedded with interface unit, clock generation unit, amplitude logic generating unit, pulse logic generating unit, phase frequency logic generating unit; Interface circuit connects microprocessor, clock generation unit connects outside input clock, interface circuit connects respectively amplitude logic generating unit, pulse logic generating unit and phase frequency logic generating unit, and clock generation unit connects respectively amplitude logic generating unit, pulse logic generating unit, phase frequency logic generating unit and analog circuit; Amplitude logic generating unit comprises that range parameter arranges latch, 4 and selects 1 bus data switch, pulse logic generating unit comprises that pulse parameter arranges latch, pulse logic generation digital controlled oscillator, pulse logic generation phase place adder and data comparator, clock generation unit connects pulse logic generation digital controlled oscillator, pulse logic generation digital controlled oscillator connects pulse logic generation phase place adder, pulse logic generation phase place adder connection data comparator, data comparator connecting analog circuit; Phase frequency logic generating unit comprises phase frequency parameter latch, phase frequency logic generation digital controlled oscillator and phase frequency logic generation phase place adder, clock generation unit connects phase frequency logic generation digital controlled oscillator, phase frequency logic generation digital controlled oscillator connects phase frequency logic generation phase place adder, phase frequency logic generation phase place adder connecting analog circuit.

2. a kind of nine component mixed signal generators according to claim 1, it is characterized in that: described clock generation unit comprises frequency multiplication of phase locked loop unit and even frequency division unit, outside input clock connects frequency multiplication of phase locked loop unit, frequency multiplication of phase locked loop unit connects respectively even frequency division unit, amplitude logic generating unit, pulse logic generating unit and phase frequency logic generating unit, even frequency division unit connecting analog circuit.

3. a kind of nine component mixed signal generators according to claim 1, is characterized in that: described analog circuit comprises amplitude converter unit, impulse wave converter unit, sinusoidal component mixed cell, full component superpositing unit four parts; Amplitude converter unit connects impulse wave converter unit, impulse wave converter unit is connected sinusoidal component mixed cell with even frequency division unit, sinusoidal component mixed cell, amplitude converter unit, impulse wave converter unit and outside input are connected full component superpositing unit, and full component superpositing unit output is final output.

4. a kind of nine component mixed signal generators according to claim 3, it is characterized in that: described amplitude converter unit comprises first order alternative analog switch, first order active low-pass filter, second level alternative analog switch, second level active low-pass filter, third level alternative analog switch, third level active low-pass filter, two four select an analog switch and sampling holder, the data comparator of amplitude logic generating unit connects respectively first order alternative analog switch, second level alternative analog switch and third level alternative analog switch, first order alternative analog switch, second level alternative analog switch and third level alternative analog switch are connected respectively first order active low-pass filter, second level active low-pass filter and third level active low-pass filter, first order active low-pass filter connects full component superpositing unit, second level active low-pass filter is connected two four and selects an analog switch with third level active low-pass filter, two four select an analog switch to connect sampling holder.

5. a kind of nine component mixed signal generators according to claim 3, it is characterized in that: described impulse wave converter unit comprises impulse wave conversion differential amplifier and impulse wave conversion alternative analog switch, sampling holder connects impulse wave conversion alternative analog switch, impulse wave conversion alternative analog switch connects impulse wave conversion differential amplifier, and pulse logic generating unit is connected respectively impulse wave conversion alternative analog switch with 7 phase frequency logic generating units.

6. a kind of nine component mixed signal generators according to claim 3, it is characterized in that: described sinusoidal component mixed cell comprises the first order adder connecting successively, the passive low pass filtered of the first order involves in-phase amplifier, sinusoidal component alternative analog switch, sinusoidal component differential amplifier, second level passive low ventilating filter and in-phase amplifier, impulse wave conversion differential amplifier connects first order adder and full component superpositing unit, first order active filter, the passive low pass filtered in the second level involves in-phase amplifier, external analog input connects full component superpositing unit.

7. a kind of nine component mixed signal method for generation according to claim 1, is characterized in that: mixed signal is comprised of 1 DC component, 1 pulse component, 7 sinusoidal components, and all component parameters all independently arrange; Signal generating circuit is comprised of monolithic FPGA and analog circuit, programmable logic device is built-in interface circuit, clock generating circuit, amplitude logic generating unit, pulse logic generating unit and 7 groups of phase frequency logic generating units, and the method step comprises:

(1) interface circuit changes the universal serial bus of microprocessor into inner parallel bus, so that frequency word, the phase place word of each sinusoidal component of mixed signal to be set, the amplitude word of frequency word, phase place word, pulsewidth word and the DC component of pulse component is set, and interface circuit is also introduced reset signal SRST from microprocessor;

(2) clock generation unit produces three kinds of clock signals: first is high frequency clock signal Fsys, and it is that external crystal-controlled oscillation clock produces after digital phase-locked loop frequency multiplication, as the system clock of all phase frequency logic generating units and pulse logic generating unit; Second is the fundamental frequency square-wave signal FBAS being obtained after even frequency division by Fsys, the difference frequency clock while converting as sinusoidal component mixing; The 3rd is Fsys clock array Fout[27..0 out after counter frequency division], as the control signal of amplitude logic generating unit;

(3) 1 frequency of amplitude logic generating unit output fix, logical signal that can preset pulsewidth, characterize the amplitude PWMA of DC component; Export the amplitude that 2 frequencies are fixed, 4 pulsewidths of constant duration change successively logical signal PWMB and PWMC(characterize 1 pulse component and 7 sinusoidal components); Export 2 channel selecting signal CH[1..0] and 1 maintenance permission signal CH[2]; Fout[27..26] as the selection signal controlling CH[1..0 of 4 passages], Fout[25] allow signal CH[2 for sampling], Fout low level is determined the frequency of amplitude logical signal;

(4) pulse logic generating unit produces pulse control signal SW ₀, in pulse logic generating unit, parameters is frequency word, phase place word, pulsewidth word, and work clock is Fsys, resets and is realized by SRST, and high position output and the phase place word of digital controlled oscillator are added; High position output and the comparison of pulsewidth word of adder, the output that is less than or equal to of data comparator is required pulse logical signal SW ₀;

(5) 7 phase frequency logic generating units produce phase frequency control signal SW _{1 ~ 7}, 7 phase frequency logic generating unit circuit structures are identical; In each phase frequency logic generating unit, parameters with the phase frequency logic generation digital controlled oscillator of phase place preparatory function is frequency word and phase place word, work clock is Fsys, reset is realized by SRST, the highest order output of phase frequency logic generation digital controlled oscillator be phase frequency control signal, and corresponding sinusoidal component frequency is the poor of this phase frequency control signal and fundamental frequency square-wave signal FBAS frequency;

(6) analog circuit comprises amplitude converter unit, impulse transfer unit, sinusoidal component mixed cell and full component superpositing unit, controlled by FPGA; Amplitude converter unit is at PWMA, PWMB, PWMC, the CH[2:0 of FPGA output] control pass through alternative analog switch down, active low-pass filter, four selects an analog switch, sampling holder obtains characterizing the direct voltage of whole 9 component amplitude; Impulse transfer unit is at the SW of FPGA output _{0 ~ 7}under control, through the conversion of 8 groups of alternative analog switches and differential amplifier, obtain characterizing amplitude, the frequency of 1 pulse component and 7 sinusoidal components, the pulse signal AS of phase place respectively _{0 ~ 7}, sinusoidal component mixed cell after equal weight stack, low-pass filtering and homophase amplify, amplifies through either-or switch conversion, low-pass filtering, homophase the mixed signal that obtains 7 sinusoidal components by 7 pulse signals under the FBAS of FPGA output controls; Full component superpositing unit obtains full component signal SMIX by direct current signal, pulse signal, sinusoidal component mixed signal and 4 external input signal stacks;

(7) when a plurality of analog circuits are under monolithic FPGA and microprocessor are supported during concurrent working, i.e. upgrading becomes many components of multichannel mixed signal generator, and it is synchronous to realize multichannel mixed signal, the sinusoidal component of passage can continue stack by external input terminals, can reach at most 35 sinusoidal components.

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