CN103595357A - 0.1-1.2GHz CMOS (complementary metal oxide semiconductor) ultra-wideband radiofrequency power amplifier - Google Patents

Abstract

The invention discloses a 0.1-1.2GHz CMOS ultra-broadband radio frequency power amplifier, which includes a multi-stage amplifier circuit, and the multi-stage amplifier circuit includes a drive stage amplifier circuit for realizing the gain of the entire amplifier and ensuring the input matching of the entire circuit (S11 parameters) to meet the requirements; the intermediate stage amplifier circuit is used to ensure the gain, efficiency and inter-stage matching of the entire circuit; the power output stage amplifier circuit is used to ensure good output matching (S22 parameters) and power output of the entire circuit. Also included are driver stage active biasing and matching circuits, intermediate stage active biasing and matching circuits, and output stage active biasing and matching circuits. The present invention adopts a three-stage single-end Class A circuit structure, which can produce better linearity. The invention adopts the CMOS Si technology, and the single-end structure can save the input and output baluns of the whole circuit, thereby saving the chip area and improving the performance of the whole circuit.

Description

A 0.1-1.2GHz CMOS ultra-wideband RF power amplifier

technical field

The invention relates to the field of complementary metal oxide semiconductor (CMOS) radio frequency power amplifiers and integrated circuits, in particular to a CMOS ultra-wideband radio frequency power amplifier for industry private network applications.

Background technique

With the rapid development of modern wireless communication technology, the RF front-end transceivers are continuously promoted to the direction of high integration, low power consumption, compact structure and low price. The power amplifier (referred to as the power amplifier) is an essential part of the wireless transmitter, and it is also the part that consumes the most energy in the entire transmitter, and the output power is generally relatively large. At present, people have higher and higher requirements on the design of power amplifiers, especially the power, efficiency, bandwidth and linearity of power amplifiers. Therefore, in the current radio system, the broadband power amplifier plays a decisive role, and its performance will directly affect the working conditions of the entire radio system.

Compared with other wireless transceiver components, high power, high linearity and high efficiency are the basic design requirements of power amplifiers. In addition to improving the operating frequency bandwidth of the power amplifier, the progress of CMOS technology makes it more difficult to improve the output power, linearity, PAE and other indicators, and it is even more difficult to realize. From the perspective of frequency domain, UWB is different from traditional narrowband and broadband, and its frequency band is wider. At present, broadband wireless access devices with a frequency in the range of 100MHz-1.2GHz are mainly used in industrial private networks, but the frequency points and bandwidths of industrial private networks are various, and the standards are not uniform. The research and development of broadband power amplifiers in our country started relatively late, especially CMOS broadband power amplifiers. Moreover, most of the RF front-end chips used in the industry private network are monopolized by foreign companies. There are still many problems in the application of foreign chips to the core components of the industry private network. Therefore, we urgently need to develop RF front-end chips with independent intellectual property rights.

Contents of the invention

In view of the above prior art, the present invention provides a 0.1-1.2GHz CMOS ultra-wideband radio frequency power amplifier, which is used for the design of a 0.1-1.2GHz ultra-wideband radio frequency power amplifier circuit chip for industry private network applications, which has sufficient gain, bandwidth and output power with good linearity.

In order to solve the above-mentioned technical problems, a 0.1-1.2GHz CMOS ultra-wideband radio frequency power amplifier of the present invention includes a multi-stage amplifier circuit, which is used to realize the gain of the entire amplifier and ensure the input matching of the entire circuit (S11 parameter ) to meet the requirements, the multi-stage amplifier circuit includes an input DC blocking capacitor C1, a driver stage bias and input matching circuit, a driver stage amplifier circuit, a stage interval direct capacitor C2, an intermediate stage bias and an interstage matching circuit, and an intermediate stage amplifier Circuit, stage interval straight capacitor C3, power stage bias and interstage matching circuit, power stage amplifying circuit, output direct blocking capacitor C4 and chip power supply, the chip power supply adopts voltage node VDD; the intermediate stage amplifying circuit is used to ensure The gain, efficiency and inter-stage matching of the whole circuit; the power output stage amplifier circuit is used to ensure good output matching (S22 parameter) and power output of the whole circuit. The driving stage amplifying circuit includes two NMOS transistors M1 and NMOS transistors M2 with a cascode structure, and an off-chip inductor L0 with an inductance value of at least 100nH; the intermediate stage amplifying circuit includes two cascode structures NMOS transistor M4 and NMOS transistor M5, an off-chip inductance L1, the inductance value of which is at least 100nH; the power stage amplifier circuit includes a common source NMOS transistor M7 and an off-chip inductance L2, the inductance value of which is at least 100nH, A feedback resistor Rf is provided between the drain and the gate of the NMOS transistor M7, and the feedback resistor Rf is used to improve output matching, bandwidth gain flatness and stability. The drive stage bias and input matching circuit, the intermediate stage bias and interstage matching circuit and the power stage bias and interstage matching circuit have the same structure, and all include an NMOS transistor, a first resistor and a second resistor respectively; In the driver stage amplifier circuit, the source of the NMOS transistor M2 is grounded, and the gate of the NMOS transistor M2 is connected to the input terminal of the amplifier after driving the driver stage bias and input matching circuit and the input DC blocking capacitor C1 Vin, the drain of the NMOS transistor M2 is connected to the source of the NMOS transistor M1, the gate bias of the NMOS transistor M1 is connected to the voltage node VDD, and the drain of the NMOS transistor M1 is connected to the off-chip The inductor L0 is connected, and the other end of the off-chip inductor L0 is connected to the voltage node VDD; the intermediate stage amplifier circuit adopts the same bias structure and amplification structure as the driver stage amplifier circuit, that is, in the intermediate stage amplifier circuit, the The source of the NMOS transistor M5 is grounded, and the gate of the NMOS transistor M5 is connected to the drain of the NMOS transistor M1 through an intermediate stage bias, an interstage matching circuit and a straight capacitor C2 between stages, and the NMOS transistor M5 The drain of the NMOS transistor M4 is connected to the source of the NMOS transistor M4, the gate of the NMOS transistor M4 is biased as the chip power supply, that is, the node VDD, and the drain of the NMOS transistor M4 is connected to the off-chip inductor L1, so The other end of the off-chip inductance L1 is connected to the voltage node VDD; the power stage amplifier circuit adopts the same bias structure as the previous two stages, in the power stage amplifier circuit, the source of the NMOS transistor M7 is grounded, and the The gate of the NMOS transistor M7 is connected to the drain of the NMOS transistor M4 through the power stage bias, the interstage matching circuit and the straight capacitor C3 between stages, and the drain of the NMOS transistor M7 is connected to the off-chip inductor L2 , the drain of the NMOS transistor M7 is connected in parallel with the output DC blocking capacitor C4 and then connected to the output port Vout of the amplifier, and the other end of the off-chip inductor L2 is connected to the voltage node VDD.

Compared with prior art, the beneficial effect of the present invention is:

In order to realize broadband power output and higher gain under CMOS technology, the present invention adopts a three-stage single-end Class A circuit structure, thereby producing better linearity. The first stage in the amplifier of the present invention is a driving stage, which is used to realize the gain of the whole amplifier and the input matching of the circuit; the second stage is an intermediate transition stage of the circuit, which is used to realize the adjustment of the gain of the whole circuit and the matching between stages; the third stage The stage is the power output stage, which is used to ensure the final good output matching and maximum power output of the circuit. The present invention adopts the CMOS Si process, and the single-ended structure can save the input and output baluns of the whole circuit, thereby saving the chip area and improving the performance of the whole circuit.

Description of drawings

Fig. 1 is the principle block diagram of CMOS ultra-wideband radio frequency power amplifier of the present invention;

Fig. 2 is a schematic circuit diagram of an embodiment of a CMOS ultra-wideband radio frequency power amplifier of the present invention.

Fig. 3 is the stability Kf value curve figure of amplifier of the present invention;

Fig. 4 is the S parameter graph of amplifier of the present invention;

Fig. 5 is the output power curve figure of amplifier of the present invention;

Fig. 6 is a graph of the power added efficiency of the amplifier of the present invention.

Detailed ways

The circuit of the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

As shown in Figure 1, a 0.1-1.2GHz CMOS ultra-wideband radio frequency power amplifier of the present invention adopts a three-stage single-ended amplification structure, uniformly adopts 3.3V power supply, and includes the first stage as a driver stage amplifier circuit to realize The high gain of the circuit, the second stage is an intermediate stage amplifier circuit to ensure the gain, efficiency and inter-stage matching of the entire circuit; the third stage is a power output amplifier stage circuit to ensure good output matching of the entire circuit and the final larger power output. The circuit also includes a driver stage active biasing and matching circuit, an intermediate stage active biasing and matching circuit, and an output stage active biasing and matching circuit.

As shown in Figure 2, the driver stage amplifier circuit includes two cascode NMOS transistors M1 and NMOS transistor M2, an off-chip inductor L0, the inductance value is greater than 100nH; the intermediate stage amplifier circuit includes two common The NMOS tube M4 and the NMOS tube M5 of the source common gate structure, an off-chip inductance L1, the inductance value is greater than 100nH; The described power output stage amplifier circuit includes a common source structure NMOS tube M7 and an off-chip inductance L2, the inductance value is greater than 100nH, a feedback resistor Rf is provided between the drain and the gate of the NMOS transistor M7; the active bias and matching circuit of the driver stage, the active bias and matching circuit of the intermediate stage and the active bias and matching circuit of the output stage The matching circuits have the same structure, and each includes an NMOS transistor, a first resistor, and a second resistor.

In the amplifier circuit of the driver stage, the source of the NMOS transistor M2 is grounded, and the gate of the NMOS transistor M2 is connected to the input of the amplifier after being actively biased by the driver stage, an input matching circuit and an off-chip DC blocking capacitor C1 Terminal Vin, the drain of the NMOS transistor M2 is connected to the source of the NMOS transistor M1, the gate of the NMOS transistor M1 is biased to the voltage node VDD, the drain of the NMOS transistor M1 is connected to the off-chip The inductor L0 is connected, and the other end of the off-chip inductor L0 is connected to the voltage node VDD; in the active bias and matching circuit of the driver stage, the drain of the NMOS transistor M0 is connected in series with the first resistor R0 and connected to the voltage node VDD, so The gate of the NMOS transistor M0 is connected to the drain, and connected to the second resistor R1 to bias the gate of the NMOS transistor M1.

In the intermediate stage amplifying circuit, the source of the NMOS transistor M5 is grounded, and the gate of the NMOS transistor M5 is connected to the The drain of the NMOS transistor M1, the drain of the NMOS transistor M5 is connected to the source of the NMOS transistor M4, the gate of the NMOS transistor M4 is biased to the voltage node VDD, and the drain of the NMOS transistor M4 is connected to the source of the NMOS transistor M4. The off-chip inductance L1 is connected, and the other end of the off-chip inductance L1 is connected to the voltage node VDD; in the intermediate stage active bias and matching circuit, the drain of the NMOS transistor M3 is connected in series with the first resistor R2 and connected to the voltage node Node VDD, the gate of the NMOS transistor M3 is connected to the drain, and connected to the second resistor R3 to bias the gate of the NMOS transistor M5.

In the power output stage amplifying circuit, the source of the NMOS transistor M7 is grounded, and the grid of the NMOS transistor M7 is connected through the active bias of the power output stage and the on-chip DC blocking capacitor C3 in the interstage matching circuit. To the drain of the NMOS transistor M4, the drain of the NMOS transistor M7 is connected to the off-chip inductor L2, and the drain of the NMOS transistor M7 is connected to the output of the amplifier after being connected to an off-chip DC blocking capacitor C4 port Vout, the off-chip DC blocking capacitor C4 is used to prevent additional DC power consumption, and the other end of the off-chip inductor L2 is connected to the voltage node VDD. In the power stage active bias and matching circuit, the drain of the NMOS transistor M6 is connected in series with the first resistor R4 and connected to the voltage node VDD, and the gate of the NMOS transistor M6 is connected to the drain and connected to the second resistor R5 Then bias the gate of the NMOS transistor M7. The power output stage amplifying circuit in the present invention adopts a common source amplifying structure to obtain a larger voltage output swing, thereby ensuring that the entire circuit obtains the maximum output power. Moreover, the common source structure can save a part of chip area compared with the cascode structure, and can also achieve the required power output index.

The working process of the CMOS ultra-broadband radio frequency power amplifier of the present invention is as follows:

As shown in Figure 2, first, the RF signal flows from the input terminal Vin of the amplifier through the off-chip capacitor C1 into the first stage of the amplifier circuit, that is, the driver stage amplifier circuit, and the NMOS transistor M0 generates a voltage bias under the action of the power supply VDD and passes through the first stage The two resistors R1 are added to the gate of the amplifying circuit, and under the action of the bias voltage, the two NMOS transistors M1 and M2 of cascode structure start to work. The signal flows into the common gate tube through the common source tube and finally outputs from its drain terminal. Due to the effect of the off-chip inductance L0 at the drain end, the signal will not flow out from the drain end of the NMOS transistor M2 to the VDD end. Finally, after the signal is amplified by the driver amplifier circuit of the first stage, it flows into the intermediate stage amplifier circuit of the second stage through the on-chip capacitor C2 between the stages.

Under the action of the same bias circuit as that of the driver stage amplifier circuit of the first stage, the cascode circuit of the intermediate stage amplifier circuit of the second stage also starts to amplify the signal and outputs it through the drain terminal. The role of off-chip inductance L1 and inter-stage on-chip capacitor C3 is the same as that of the first stage.

After the signal flows out from the second stage circuit, it flows into the power output stage amplifier circuit of the third stage through the on-chip interstage capacitor C3. Similarly, under the action of the bias circuit, the third-stage common-source amplifier circuit starts to work to further amplify the signal. The NMOS transistor M7 adopts a common source structure to generate a larger output swing, and can save chip area at the same time. The feedback resistor Rf between the drain and gate of the NMOS transistor M7 forms a feedback loop with the NMOS transistor M7, which can improve the broadband output matching of the circuit. Therefore, the off-chip inductance L2 and off-chip capacitor C4 of the power output stage work together with the feedback resistor Rf to make the entire amplifier circuit get the best output matching, thereby realizing the maximum power output.

In the design process of the entire broadband amplifier circuit, the size of each transistor, resistor and capacitor is determined after comprehensively considering the bandwidth, gain, output power and efficiency of the entire circuit. And through the layout design and rational layout optimization in the later stage, the required output indicators can be realized to the greatest extent, and high gain, high linearity, large output power and efficiency can be realized under the ultra-wideband of 0.1-1.2GHz, and Occupies a smaller chip area.

The following is a specific design example. In the actual design, the gate width/gate length ratio of all NMOS transistors M0~M5 in the first two stages is 200um/0.35um, and the size of the third stage NMOS transistors M6 and M7 are both 400um/0.35um; the resistance R0 is 167ohm, R1 is 30ohm, R2 is 317ohm, R3 is 220ohm, R4 is 500ohm, R5 is 230ohm, feedback resistor Rf is 840ohm; off-chip DC blocking capacitors C1 and C4 are 1uF, C2 and C3 are 20pF; inductors L0, L1, L2 Both take 200nH.

As shown in FIG. 3 , the simulation result of the stability Kf value of the power amplifier of the present invention is shown. When the Kf value is greater than 1, the amplifier is stable. It can be seen from the figure that the Kf value is greater than 4.8e5 in the entire 0.1-1.2GHz frequency band, so the circuit is stable.

As shown in Fig. 4, it is the simulation result of the S parameter curve of this power amplifier. It can be seen from the figure that in the entire frequency range, the gain curve S21 is above 28dB; the input and output return loss S11 and S22 are both below -10dB, mostly around -20dB; the isolation S12 is less than -150dB.

FIG. 5 is a graph showing the output power of the power amplifier of the present invention. It can be seen from the figure that the saturated output power of the power amplifier is 21.6dBm.

FIG. 6 is a graph showing the power added efficiency of the power amplifier of the present invention. It can be seen from the figure that under the condition of output power saturation, the efficiency of the amplifier is about 35%.

Based on the simulation results of Fig. 3, Fig. 4, Fig. 5 and Fig. 6, it can be known that the power amplifier of the present invention has good performance indicators in the 0.1-1.2 GHz frequency band and can meet the design requirements.

Although the present invention has been described above in conjunction with the drawings, the present invention is not limited to the above-mentioned specific embodiments, and the above-mentioned specific embodiments are only illustrative, rather than restrictive. Under the inspiration, many modifications can be made without departing from the gist of the present invention, and these all belong to the protection of the present invention.

Claims (2)

1. A CMOS ultra-broadband radio frequency power amplifier of 0.1～1.2GHz comprises a multistage amplifying circuit, wherein the multistage amplifying circuit comprises an input DC blocking capacitor C1, a driving stage bias and an input matching circuit, and a driving stage amplifying circuit , stage interval straight capacitor C2, intermediate stage bias and interstage matching circuit, intermediate stage amplifying circuit, stage interval direct capacitor C3, power stage bias and interstage matching circuit, power stage amplifying circuit, output DC blocking capacitor C4 and chip A power supply, the chip power supply adopts a voltage node VDD; The driver stage amplifier circuit includes two NMOS transistors M1 and NMOS transistors M2 with a common-gate common-source structure, and an off-chip inductor L0 whose inductance value is at least 100nH; The intermediate stage amplifier circuit includes two NMOS transistors M4 and NMOS transistors M5 with a common-gate common-source structure, and an off-chip inductor L1 whose inductance value is at least 100nH; The power stage amplifying circuit includes an NMOS transistor M7 with a common source structure and an off-chip inductor L2, the inductance value of which is at least 100nH, and a feedback resistor Rf is provided between the drain and the gate of the NMOS transistor M7; The drive stage bias and input matching circuit, the intermediate stage bias and interstage matching circuit and the power stage bias and interstage matching circuit have the same structure, each including an NMOS transistor, a first resistor and a second resistor; In the driver stage amplifier circuit, the source of the NMOS transistor M2 is grounded, and the gate of the NMOS transistor M2 is connected to the input of the amplifier after driving the driver stage bias and input matching circuit and the input DC blocking capacitor C1 Terminal Vin, the drain of the NMOS transistor M2 is connected to the source of the NMOS transistor M1, the gate bias of the NMOS transistor M1 is connected to the voltage node VDD, the drain of the NMOS transistor M1 is connected to the chip The external inductance L0 is connected, and the other end of the off-chip inductance L0 is connected to the voltage node VDD; In the intermediate-stage amplifying circuit, the source of the NMOS transistor M5 is grounded, and the gate of the NMOS transistor M5 is connected to the NMOS transistor M1 after passing through the intermediate-stage bias and inter-stage matching circuit and the straight capacitor C2 between stages. The drain of the NMOS transistor M5 is connected to the source of the NMOS transistor M4, the gate bias of the NMOS transistor M4 is connected to the voltage node VDD, and the drain of the NMOS transistor M4 is connected to the source of the NMOS transistor M4. The off-chip inductor L1 is connected, and the other end of the off-chip inductor L1 is connected to the voltage node VDD; In the power stage amplifying circuit, the source of the NMOS transistor M7 is grounded, and the gate of the NMOS transistor M7 is connected to the NMOS transistor M4 after passing through a power stage bias, an inter-stage matching circuit and a straight capacitor C3 between stages. The drain of the NMOS transistor M7 is connected to the off-chip inductor L2, the drain of the NMOS transistor M7 is connected to the output DC blocking capacitor C4 in parallel, and then connected to the output port Vout of the amplifier. The other end of the off-chip inductor L2 is connected to the voltage node VDD. 2. The 0.1-1.2GHz CMOS ultra-broadband radio frequency power amplifier according to claim 1, wherein the drain of the NMOS transistor M0 in the driver stage bias and input matching circuit is connected in series with the first resistor R0 to the voltage node VDD , the gate of the NMOS transistor M0 is connected to the drain, and connected in series with the second resistor R1 to bias the gate of the NMOS transistor M1.

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