CN103594444B - Semiconductor component with dual connection channels between interposer and coreless substrate - Google Patents

Abstract

The present invention relates to a semiconductor component having dual connection channels between an interposer and a coreless substrate. The semiconductor component comprises a semiconductor element, an interposer having a through hole, a coreless substrate, and a reinforcing layer. The semiconductor element is flipped on the interposer, and the interposer is fixed to the coreless substrate via an adhesive and extends into a through hole of a reinforcing layer, and the reinforcing layer provides mechanical support for the coreless substrate. The electrical connection between the interposer and the coreless substrate comprises wire bonding and conductive microvias, and the coreless substrate can provide fan-out routing from the interposer.

Description

Semiconductor component with dual connection channels between interposer and coreless substrate

technical field

The invention relates to a semiconductor component, especially a semiconductor component with a flip-chip semiconductor element on an interposer, wherein the interposer is fixed on a coreless substrate. The intermediary layer has a through hole, and the connection between the intermediary layer and the coreless substrate is flexibly connected through conductive micro-holes and wire bonding.

Background technique

High-performance semiconductor chips usually use a dielectric layer with a low-k value as an interlayer material. When the dielectric material with low-k value is porous, fragile, and very sensitive to interface stress, traditional flip-chip packaging with laminated substrates will face problems due to the low-k value chip and the thermal expansion coefficient between the laminated substrates. Matching, which leads to various reliability problems and pass rate problems. In order to solve the above problems, attempts have been made to reduce interface stress by incorporating a CTE-matched interposer (eg, silicon) between the chip and the laminated substrate. In addition, the interposer can provide ultra-fine circuit routing. Therefore, before connecting the chip to the laminated substrate through the through hole, multiple chips are placed on the interposer to prepare semiconductor components with high packing density and improved performance. method has been paid attention to.

In addition, laminate substrates that provide interposer mechanical support and signal routing typically include a double-sided board "core layer" with multiple "build-up" structures on each side of the core layer. The double-sided core layer uses a plurality of covered perforations as internal vertical connections, and a build-up structure with micropores as connections between layers. For example, a 4-2-4 substrate refers to a two-layer core layer with four build-up structures attached to each side. In order to reduce the warpage of a package substrate, a thickness of about 0.8-0.4 mm core layer. The use of a thick core layer can reduce the problem of warpage, but the requirement of high-performance components for shorter routing lengths is almost impossible to achieve. To solve this problem, a coreless substrate has been developed with various reinforcement supports to minimize warpage and deformation.

Therefore, it is very ideal to solve the problems of productivity and reliability by using an interposer with perforated holes that has a similar thermal expansion coefficient to the silicon chip, and to use a coreless substrate without a core layer to improve the electrical performance of the component. .

U.S. Patent No. 7,738,258 to Ohno et al., U.S. Patent No. 8,183,678 to Lee et al., U.S. Patent No. 8,379,400 to Sanuhara, U.S. Patent No. 8,384 to Rahman et al. , No. 225, and Wang's U.S. Patent No. 8,310,063 discloses a component in which a silicon interposer with vias is stacked between a chip and a laminate substrate to provide lateral and vertical connections. Although through-holes in the silicon interposer can improve system performance, when the density of through-holes is very high, mutual interference between through-holes will become a limiting factor. Costs increase, and because of low volumes, the price of the product will also be increased.

U.S. Patent Nos. 6,570,248 and 6,281,042 to Ahn et al., U.S. Patent No. 7,750,452 to Do et al., and U.S. Patent No. 8,263,434 to Pagaila et al. A device structure including a silicon interposer in a substrate cavity is disclosed. A plurality of through holes formed through the silicon interposer for micromachining are used to pair a plurality of semiconductor elements on opposite surfaces of the silicon interposer. This structure can provide excellent electrical performance between the attached components, but the traditional wire bonding technology to connect the interposer and the laminated substrate will encounter performance limitations and can only accommodate a low number of pin modules. In addition, when there are different thermal expansion coefficients between the silicon and resin substrates, and the interposer barely adheres to the sidewalls of the surrounding substrate, the fragility due to insufficient support, and the thermal cycling process due to the thin and brittle nature of the interposer Problems such as cracks are prone to occur in the structure, making the preparation of such structures prohibitive and impractical.

U.S. Patent No. 7,902,660 to Lee et al., U.S. Patent No. 7,754,598 to Lin et al., U.S. Patent No. 8,227,703 to Maruyamo et al., U.S. Patent Application to Monensen et al. No. 2012/0005887, and U.S. Patent Application No. 2012/0074209 to Wu et al. disclose various coreless substrate structures for packaging. Some coreless substrates can have acceptable coplanar properties through reinforcement or structural modification, however, warpage usually occurs again when the substrate size reaches a certain size or when the substrate is subjected to high temperature processing in the assembly process . For example, when packaging a semiconductor chip larger than 10 square millimeters, the coplanarity of the substrate may increase beyond 30 microns after solder reflow, which is unacceptable for packaging requirements.

U.S. Patent No. 7,605,476 to Gfini, U.S. Patent No. 7,663,245 to Lim, U.S. Patent No. 8,372,692 to Liou et al., and U.S. Patent No. 7,309 to Shim et al. No. 913 discloses a component structure that has an interposer stacked on semiconductor elements and packaging substrates. When the interposer does not have perforations to provide the shortest route in the vertical direction, when the system needs to send or receive high-frequency signals, The signal integrity of the assembly components will be adversely affected.

Although various component architectures using active or passive interposers have been reported in the literature, many performance or reliability issues remain. For example, the solder used to connect the silicon interposer to the package substrate may have reliability issues, although the interface is filled with a resin material to enhance its structure.

Contents of the invention

The present invention is developed in view of the above circumstances, and its purpose is to provide a semiconductor component, wherein the semiconductor element is flip-chip mounted on an interposer, and the interposer is fixed on a coreless substrate as a mechanical support. A reinforcement layer acts as a further support for the interposer and the coreless substrate, and can be used to suppress warping and bending of the components. The strengthening layer has a through hole, and the intermediate layer extends into the through hole of the strengthening layer and is electrically connected to the coreless substrate. The electrical connection between the interposer and the coreless substrate is flexibly connected through one or more conductive vias in the interposer and one or more conductive microholes in the coreless substrate, and through one or more A mechanically formed wire bond is directly connected to the coreless substrate, thereby reducing the number of conductive vias in the interposer, and can be balanced using wire bonds according to system requirements, thereby improving the yield of the assembly and get affordable costs. For example, the power/ground I/Os of the semiconductor device can be connected through conductive vias, while the signal I/Os can be connected through bonding wires, and vice versa. Accordingly, the present invention provides a composite circuit board and a semiconductor component, which include a semiconductor element electrically connected to the composite circuit board, wherein the composite circuit board includes an interposer, a coreless substrate, and a reinforcement layer .

In a preferred embodiment, a semiconductor device such as a microprocessor, a controller, or a memory chip can be flip-chip disposed on the first surface of the interposer via a bump array. However, in most cases, more than one chip needs to be connected to the interposer. For example, a logic chip might connect four memory chips for fast data processing, or an array of partitioned logic chips connected to each other on an interposer, reducing the cost of manufacturing a single large chip. The bumps can be solder, gold, or solder-coated copper pillars, and the choice of bumps can depend on their spacing requirements. For example, in a component with a very fine pitch, it is preferable to use solder-coated copper pillars because solder slump can be minimized during solder reflow to avoid solder-to-solder bridging.

The interposer can be made of silicon, ceramic, or glass, and has a plurality of contact pads on two opposite surfaces. Specifically, in the interposer, a first surface facing a first vertical direction may include a plurality of first contact pads, and one or more bond fingers, and face a second vertical direction. There are a plurality of second contact pads on a second surface. The first contact pads on the first surface can be electrically connected to the corresponding second contact pads on the second surface through vertical connection elements (such as conductive vias). Alternatively, the first contact pads on the first surface may be electrically connected to the bonding fingers on the first surface via a lateral circuit formed in the interposer. The circuitry in the interposer may have one or more wiring layers and at one location may distribute signals in a lateral direction to other locations. Therefore, part of the first contact pads can be vertically connected to the second contact pads on the second surface through conductive vias, while other parts of the first contact pads can be connected to the bonding fingers on the first surface through circuits. Accordingly, when the semiconductor element is connected to the first contact pad of the interposer in the flip-chip chip set, the I/O pad of the flip-chip semiconductor element can be connected to the first contact pad of the interposer through the conductive via. The second contact pad is then connected to the coreless substrate via conductive microvias, or can be connected to the bonding finger, which replaces the conductive through hole in the interposer by bonding to electrically connect to the coreless substrate. . More specifically, the first contact pad on the peripheral edge of the flip chip can send/receive electrical signals from the circuit, conductive vias, and the second contact pad, or can send/receive electrical signals from the circuit, bond fingers, and Wired electronic signal. Although the interposer is described as a passive device in this embodiment, it should be understood that the interposer can include transistors integrated in the interposer, so that the interposer can become an active semiconductor device .

The bonding wires can be made of gold, aluminum, copper, or alloys thereof. The bonding wire serves as a connection channel between the interposer and the coreless substrate, and may have one end contacting with a bonding finger of the interposer and the other end connected with a connection pad of the coreless substrate.

The connection pads of the coreless substrate can be made of metal. For example, for connection purposes, the connection pad may consist essentially of copper, copper coated with nickel, palladium, gold, or alloys thereof. The bonding wire can be exposed from the surface of the coreless substrate along the first vertical direction, aligned with the through hole of the reinforcement layer, and extending to the through hole of the reinforcement layer. More specifically, the connection pad can be laterally aligned with the peripheral edge of the interposer and the sidewall of the through hole of the stiffener in the lateral direction, and can be aligned from the peripheral edge of the interposer and the stiffener in the lateral direction. extending laterally between the sidewalls of the through hole. The connection pad is electrically connected to the connection pad of the intermediary layer through the bonding wire, and can also be electrically connected to the circuit of the coreless substrate through the conductive microhole in the coreless substrate.

The coreless substrate can cover the intermediate layer and the reinforcement layer in the second vertical direction, and includes one or more connection pads, a first dielectric layer, and one or more first wires. For example, the first dielectric layer covers the interposer, the connection pad, and the reinforcement layer in the second vertical direction, and extends to the peripheral edge of the device. The first dielectric layer includes one or more first microholes, and the microholes are disposed adjacent to the connection pad and the second contact pad of the interposer, and optionally adjacent to the reinforcement layer. One or more first wires are disposed on the first dielectric layer (for example: extending from the first dielectric layer toward the second vertical direction and extending laterally on the first dielectric layer) and at The first vertical direction extends into the first microhole to form one or more conductive microholes, and the conductive microholes are electrically connected to the connection pad and the second contact pad, thereby providing the connection pad and the interposer The signal routing of the second contact pad, and selectively provide the electrical connection of the strengthening layer. Specifically, the first wire can directly contact the connection pad and the second contact pad to provide signal routing for the interposer, so the electrical connection between the interposer and the coreless substrate can be via bidirectional channel and can be solder-free. The first wire can also directly contact the strengthening layer as a ground, or as an electrical connection to passive components such as thin film transistors or capacitors disposed on the strengthening layer.

For further signal routing requirements, the coreless substrate may include additional dielectric layers, additional microporous layers, and additional wiring layers. For example, the coreless substrate may further include a second dielectric layer, one or more second microholes, and one or more second wires. The second dielectric layer with one or more second microholes inside is disposed on the first dielectric layer and the first wire (for example: from the first dielectric layer and the first wire toward the extending in a second vertical direction), and may extend to the peripheral edge of the component. The second microhole is disposed adjacent to the first wire. one or more second wires are disposed on the second dielectric layer (for example: extending from the second dielectric layer toward the second vertical direction and extending laterally on the second dielectric layer), and extending into the second microhole in the first vertical direction to provide electrical connection to the first wire. In addition, the first microhole and the second microhole may have the same size, and the first dielectric layer, the first wire, the second dielectric layer, and the second wire may have elongated and flat a surface facing the second vertical direction.

The coreless substrate may include one or more interconnection pads to provide the next-level component (such as a motherboard), and/or another electronic component (such as a semiconductor component), or another semiconductor component (such as a BGA semiconductor component) electrical connection. The interconnection pad can extend to the first wire in the second vertical direction, or extend beyond the first wire, and includes a contact surface exposed toward the second vertical direction. For example, the inner connection pad can be adjacent to and integrally formed with the second conductive line. In addition, the first wire and the second wire can provide an electrical connection between the inner connection pad, the connection pad, and the second contact pad of the interposer. Therefore, the electrical connection points (for example: the first contact pad of the interposer and the inner connection pad of the coreless substrate) can be electrically connected to each other and located on opposite surfaces facing opposite vertical directions, so that a Or multiple semiconductor chips can be flip-chip onto a semiconductor device.

The reinforcement layer has a through hole and can extend to the peripheral edge of the component to provide mechanical support for the coreless substrate and the interposer, and the reinforcement layer can be a single-layer structure or a multi-layer structure (such as a circuit board , or a multilayer ceramic plate, or a laminate of a substrate and a conductive layer). The strengthening layer can be made of ceramics, metals, or other inorganic materials, such as aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), silicon nitride (SiN), silicon (Si), copper (CU, copper Alloy (for example: Cu/Mo/Cu), aluminum (AI), stainless steel, etc. The strengthening layer can also be made of organic materials such as copper foil laminate.

The coreless substrate of the present invention may further include a positioning member, which is used as a guide for disposing the interposer, and is laterally aligned with the peripheral edge of the interposer and the connection pad, and on the interposer The outer peripheral edge of the connecting pad and the outer side of the connection pad are extended to prevent unnecessary displacement of the interposer when the interposer is attached. In any case, the interposer and the locator can be aligned with and extend into the through hole of the reinforcement layer. The spacer can be made of metal such as copper, aluminum, nickel, iron, tin, or alloys thereof.

The coreless substrate of the present invention may further include a configuration guide, the configuration guide of the reinforcement layer may be close to the peripheral edge of the reinforcement layer, laterally aligned with the peripheral edge of the reinforcement layer, and at the peripheral edge of the reinforcement layer Extend laterally. Like the positioning member, the reinforcing layer arrangement guide may be made of metal such as copper, aluminum, nickel, iron, tin, or alloys thereof.

The positioning member, the configuration guide, and the connection pad may contact the first dielectric layer of the coreless substrate, extend from the first dielectric layer of the coreless substrate toward the first vertical direction, and may while being formed of the same material (eg, copper). Additionally, the positioning member and the deployment guide may have patterns to avoid unnecessary movement of the interposer and the reinforcement layer, respectively. For example, the positioner and the arrangement guide may comprise a continuous or discontinuous array of slats or studs, and the positioner and the arrangement guide may be formed simultaneously and have the same or different patterns. Specifically, the positioning member can laterally align the four side surfaces of the interposer to stop the lateral displacement of the interposer. For example, the positioning member can be aligned along four sides, two diagonal corners, or four corners of the interposer, and the gap between the intermediary layer and the positioning member is preferably within a range of about 0.001 to 1 mm. The interposer can be kept at a distance from the inner wall of the through hole by the spacer and the connection pad, and a bonding material can be added between the interposer and the reinforcing layer to increase its rigidity. Similarly, the configuration guide can be laterally aligned with the four outer surfaces of the reinforcement layer to stop the lateral displacement of the reinforcement layer. For example, the configuration guide can be aligned along the four outer sides, two outer diagonal corners, or four outer corners of the reinforcement layer, and the gap between the peripheral edge of the reinforcement layer and the configuration guide is preferably about In addition, the thickness of the positioning member and the configuration guide is preferably in the range of 10 to 200 microns.

The interposer and the reinforcement layer can be fixed and mechanically connected to the first dielectric layer of the coreless substrate using an adhesive. The adhesive can contact the interposer, the reinforcement layer, the positioning member, the placement guide, and the first dielectric layer, and be between the interposer and the coreless substrate, and between the reinforcement layer and between the coreless substrates. In any case, the adhesive can be coplanar with the positioning member, the deployment guide, and the connection pad in the second vertical direction, and be lower than the positioning member, the deployment guide, and the bonding pad in the first vertical direction. and the connection pad. When the adhesive under the intermediary layer and the reinforcement layer is lower than the positioning member and the arrangement guide in the first vertical direction, the positioning member and the arrangement guide can prevent the intermediary layer and the reinforcement layer from curing Unwanted displacement caused by adhesive.

The invention also provides a three-dimensional semiconductor device, wherein the interposer is an active semiconductor device. In this application, a first semiconductor element such as a chip can be electrically connected to the first contact pad of the interposer (such as a semiconductor chip) exposed by the through hole of the stiffener layer using various connection media, The connection medium includes gold, solder, or copper pillar bumps.

The present invention has many advantages. The conductive vias in the interposer can improve the power stability of the attached chip. In addition to the vias in the interposer, the bond wires can provide alternative interconnection paths between the interposer and the coreless substrate, thereby reducing the number of vias required in the interposer. Thus, the size of the interposer can be reduced, or the yield of the product can be increased due to the lower perforation density in the interposer. Therefore, adding wire bonding can significantly reduce the cost of the interposer and the semiconductor device. The positioning member of the coreless substrate can accurately limit the placement position of the interposer, so as to avoid the electrical connection error between the interposer and the coreless substrate caused by the lateral displacement of the interposer, thereby greatly improving The product pass rate. The electrical connection between the interposer and the coreless substrate does not contain solder and is directly connected, so it is beneficial to exhibit high I/O value, high performance, and high reliability. The reinforcement layer can provide a power/ground platform, heat sink, and stable mechanical support for the interposer and the coreless substrate. The semiconductor component using it has high reliability, low price, and is very suitable for mass production.

Description of drawings

The present invention may be more clearly understood by the following detailed description of the preferred embodiments with reference to the accompanying drawings, in which:

1A-1J are cross-sectional views of a method of manufacturing a semiconductor device including an interposer, a semiconductor chip, a stiffener, and a coreless substrate electrically connected to the interposer in accordance with an embodiment of the present invention.

FIG. 1K is a cross-sectional view of a three-dimensional assembly including semiconductor components attached to two sides of a composite circuit board according to an embodiment of the present invention.

2 is a cross-sectional view of a three-dimensional component with an additional internal connection between the stiffener and the coreless substrate and a heat sink attached to the semiconductor chip and the stiffener in another embodiment of the present invention.

【Symbol Description】

Composite circuit board 101 Positioning piece 113 Connection pad 111

Adhesive 131 Metal layer 11 Configuration guide 115

Semiconductor package 110, 210 Support plate 23 Coreless substrate 20

Opening 293 First wire 241 Covering layer 24

First Dielectric Layer 21 Second Conductor 281 Inner Connection Pad 284

Second dielectric layer 261 First microhole 213 Solder mask material 291

First conductive microhole 243 Second microhole 263 Second conductive microhole 283

Three-dimensional component 310 first surface 311 second surface 313

Interposer 31 First contact pad 312 Second contact pad 314

Wire Bonding 321 Conductive Via 318 Bonding Finger 316

Lateral circuit 320 Reinforcing layer 41 Through hole 411

Semiconductor chips 51, 53 Solder bumps 61, 63 Sealing material 71

Heat sink 81 Thermally conductive adhesive 801

detailed description

In the following, examples will be provided to illustrate practical aspects of the invention in detail. Other advantages and effects of the present invention will be more obvious through the contents disclosed in the present invention. It should be noted that these accompanying drawings are simplified drawings, and the number, shape, and size of components shown in the drawings can be modified according to actual conditions, and the configuration of elements may be more complicated. Other aspects of practice or application can also be carried out in the present invention, and various changes and adjustments can be made without departing from the defined spirit and scope of the present invention.

[Example 1]

1A-1J are according to an implementation aspect of the present invention, a method of manufacturing a semiconductor component, the semiconductor component includes an interposer, a semiconductor chip, a reinforcement layer, and a coreless substrate, the coreless substrate via wire bonding And the conductive microholes are electrically connected to the intermediary layer.

As shown in FIG. 1J , the semiconductor component 110 includes an interposer 31 , a strengthening layer 41 , a semiconductor chip 51 , a coreless substrate 20 , and bonding wires 321 . The interposer 31 includes a first surface 311 , a second surface 313 opposite to the first surface 311 , a first contact pad 312 and bonding fingers 316 on the first surface 311 , and a second contact pad 314 on the second surface 313 , the conductive via 318 partially connected to the first contact pad 312 and the second contact pad 314 , and the lateral circuit 320 electrically connected to the bonding finger 316 and a portion of the first pad 312 . The interposer 31 may be a silicon interposer, a glass interposer, or a ceramic interposer, which includes a conductive pattern fanning out from a portion of the fine pitch of the first contact pads 312 to the coarse pitch of the second contact pads 314 , and further includes a conductive pattern extending laterally from a portion of the first contact pad 312 to the bonding finger 316 . The coreless substrate 20 is electrically connected to the interposer 31, and includes a connection pad 111, a positioning member 113, a configuration guide 115, a first dielectric layer 21, a first wire 241, a second dielectric layer 261, and a second wire 281. The positioning member 113 extends upward from the first dielectric layer 21 and is close to the peripheral edge of the intermediary layer 31 . The connection pads 111 , the positioning elements 113 , and the interposer 31 are aligned with the through holes 411 of the reinforcement layer 41 and extend into the through holes 411 of the reinforcement layer 41 .

FIG. 1A is a cross-sectional view of a laminated substrate including a metal layer 11 , a first dielectric layer 21 , and a support plate 23 . The metal layer 11 shown in the figure is a copper layer with a thickness of 35 microns. However, the metal layer 11 can also be various metal materials, and is not limited to the copper layer. In addition, the metal layer 11 can be deposited on the dielectric layer 21 by various techniques, including lamination, electroplating, electroless plating, evaporation, sputtering, and combinations thereof to deposit a single-layer or multi-layer structure, and its The thickness is preferably in the range of 10 to 200 microns.

The first dielectric layer 21 is generally made of epoxy resin, glass epoxy resin, polyimide, and the like, and has a thickness of 50 microns. In this embodiment, the first dielectric layer 21 is interposed between the metal layer 11 and the support plate 23 . However, the support plate 23 may be omitted in some aspects. The support plate 23 is usually made of copper, but copper alloy and other materials can be used. The thickness of the support plate 23 can be in the range of 25 to 1000 microns, and considering the process and cost, it is preferably 35 to 100 microns. in the micron range. In this implementation aspect, the support plate 23 is a copper plate with a thickness of 35 microns.

1B and 1B′ are respectively a cross-sectional view and a top view of the structure for forming the connection pad 111 , the positioning member 113 , and the configuration guide 115 on the first dielectric layer 21 . The connection pads 111, the positioning elements 113, and the configuration guides 115 can be formed by removing selected parts of the metal layer 11 by photolithography and wet etching. In this illustration, as shown in FIG. 1B', the positioning elements 113 includes a plurality of metal studs in a rectangular array, and coincides with four sides of an interposer subsequently disposed on the dielectric layer 21 . Likewise, the configuration guide 115 includes a plurality of metal studs in a rectangular row, and conforms to four sides of the strengthening layer 41 that is subsequently disposed on the first dielectric layer 21 . However, the form of the positioning member 113 and the configuration guide 115 is not limited thereto, and may be any pattern that prevents unnecessary displacement of the interposer and the reinforcing layer disposed subsequently. For example, the positioning member 113 and the disposition guide member 115 can also be composed of continuous or discontinuous strips, and conform to the four sides, two diagonal corners, or four corners of the intermediate layer and the reinforcement layer to be disposed later. In addition, the positioning part 113 and the arrangement guide 115 can be omitted, but considering the accuracy of the components to be arranged later, it is better for the positioning part 113 and the arrangement guide 115 to exist.

FIG. 1C is a cross-sectional view of the interposer 31 disposed on the first dielectric layer 21 using an adhesive 131 . The interposer 31 includes a first surface 311 , a second surface 313 opposite to the first surface 311 , a first contact pad 312 on the first surface 311 and bonding fingers 316 , and a second contact pad on the second surface 313 314 , the conductive via 318 electrically connected to part of the first contact pad 312 and the second contact pad 314 , and the lateral circuit 320 electrically connected to the bonding finger 316 and part of the first contact pad 312 . The interposer 31 can be a silicon interposer, a glass interposer, or a ceramic dielectric layer, which includes a conductive pattern that fans out from a portion of the fine pitch of the first contact pad 312 to a portion of the second contact pad 314. The pitch is coarse, and further includes a conductive pattern extending laterally from a portion of the first contact pad 312 to the bonding finger 316 .

The positioning member 113 can be used as a disposition guide for the interposer 31 , so that the interposer 31 is accurately placed on a predetermined position, and the second surface 313 thereof faces the first dielectric layer 21 . The positioning member 113 extends upward from the first dielectric layer 21, and extends beyond the second surface 313 of the interposer 31, and is laterally aligned with the four sides of the interposer 31 in the side direction, and on the sides of the interposer 31. The four sides extend laterally. When the positioning member 113 is close to the four sides of the intermediary layer 31 and conforms to the four sides of the intermediary layer 31, and the adhesive 131 under the intermediary layer 31 is lower than the positioning member 113, it is possible to avoid any problem of the intermediary layer 31 when curing the adhesive. Unnecessary displacement. Preferably, the gap between the intermediary layer 31 and the positioning member 113 is in the range of 0.001 to 1 mm.

FIG. 1D is a cross-sectional view of the structure where the reinforcing layer 41 is disposed on the first dielectric layer 21 using the adhesive 131 . The interposer 31 , the positioning element 113 , and the connection pad 111 are aligned with the through hole 411 of the reinforcement layer 41 and inserted into the through hole 411 of the reinforcement layer 41 . The through holes 411 are formed on the reinforcement layer 41 by laser drilling, and can also be formed by other techniques such as punching and mechanical drilling. The reinforcement layer 41 in the drawings is a ceramic sheet with a thickness of about 0.6 mm, but it can also be other single-layer or multi-layer structures, such as multi-layer circuit boards, glass plates, or metal plates.

The inner side walls of the interposer 31 and the through hole 411 are kept at a distance from each other by the positioning member 113 and the connection pad 111. In this figure, the reinforcing layer 41 can be accurately set at a predetermined position through the arrangement guide 115, and the arrangement The guide 115 extends upward from the first dielectric layer 21 and extends beyond the attachment surface of the reinforcement layer 41, and extends laterally beyond the four peripheral edges of the reinforcement layer 41, and laterally aligns the four edges of the reinforcement layer 41. In addition, the adhesive 131 under the reinforcement layer 41 is lower than the configuration guide 115. When the configuration guide 115 is close to and conforms to the four outer surfaces of the reinforcement layer 41 in the side direction, and the adhesive 131 under the reinforcement layer 41 is lower than the configuration guide, it is possible to prevent the reinforcement layer 41 from being damaged before the adhesive 131 is completely cured. any unnecessary displacement. Preferably, the gap between the reinforcement layer 41 and the configuration guide 115 is in the range of 0.001 to 1 mm.

1E is a cross-sectional view of the structure of the first microhole 213 formed through the support plate 23 , the first dielectric layer 21 , and the adhesive 131 to expose the second contact pad 314 and the connection pad 111 . The first microhole 213 can be formed by various techniques, including laser drilling, plasma etching and photolithography. A pulsed laser can be used to increase laser drilling efficiency, or a metal mask and a scanned laser beam can be used. For example, a copper plate can be etched to create a metal window before the laser beam is irradiated. The first micropores 213 typically have a diameter of 50 microns. Referring to FIG. 1F, the first wire 241 formed on the first dielectric layer 21 is deposited on the support plate 23 by depositing the coating layer 24, and deposited into the first microhole 213, and then patterned on the support plate 23 and the coating thereon. Layer 24 is formed. Alternatively, when the laminated substrate does not have the support plate 23 or in some implementations where the support plate 23 is removed after the step in FIG. 1D , the first dielectric layer 21 can be directly metallized to form The first wire 241.

Coating layer 24 may be deposited as a single-layer or multi-layer structure by various techniques, including electroplating, electroless plating, evaporation, sputtering, and combinations thereof. For example, the coating layer 24 is firstly deposited by immersing the structure in an activator solution to make the first dielectric layer 21 react with the electroless copper plating catalyst, and then coat a thin copper layer as a seed layer by electroless plating, Then a second copper layer with required thickness is formed on the seed layer by electroplating. Alternatively, the seed layer can be sputtered to form a thin film such as Ti/Cu before depositing an electroplated copper layer on the seed layer, and once the desired thickness is reached, the support plate can be patterned using various techniques 23 and the coating layer 24 to form the first wire 241 , which includes wet etching, electrochemical etching, laser-assisted etching and a combination thereof with an etching mask (not shown) to define the first wire 241 . Therefore, the first wire 241 extends downward from the first dielectric layer 21 , extends laterally on the first dielectric layer 21 , and extends into the first microhole 213 in an upward direction to form an electrical connection to the second contact. The pad 314 and the first conductive microhole 243 connecting the pad 111 .

For ease of description, the support plate 23 and the coating layer 24 thereon are shown as a single layer. Since copper is coated with a homogeneous layer, the boundaries between metal layers (both shown in dotted lines) may be difficult to detect or even undetectable. However, the coating layer 24 The boundary with the first dielectric layer 21 is clearly visible.

FIG. 1G is a cross-sectional view of the structure where the second dielectric layer 261 is disposed on the first wire 241 and the first dielectric layer 21 . The second dielectric layer 261 can be made of epoxy, glass epoxy, polyimide, and the like, and is formed by various techniques including film lamination, roll coating, spin coating Cloth and spray deposition methods, and usually have a thickness of 50 microns. Preferably, the first dielectric layer 21 and the second dielectric layer 261 are made of the same material.

FIG. 1H is a structural cross-sectional view of a second microhole 263 formed through the second dielectric layer 261 to expose a selected portion of the first conductive line 241 . Like the first microhole 213, the second microhole 263 can be formed by various techniques including laser drilling, plasma etching and photolithography, and its diameter is typically 50 microns. Preferably, the first microhole 213 and the second microhole 263 have the same size.

Referring to FIG. 1I , a second wire 281 is formed on the second dielectric layer 261 to complete the composite circuit board 101 . The composite circuit board 101 includes an interposer 31 , a reinforcement layer 41 , and a coreless substrate 20 . In this figure, the coreless substrate 20 includes a positioning member 113, a connection pad 111, a configuration guide 115, and includes a first dielectric layer 21, a first wire 241, a second dielectric layer 261, and a second wire 281 build-up circuit. The second wire 281 extends downward from the second dielectric layer 261 , extends laterally on the second dielectric layer 261 , and extends upward into the second microhole 263 to form an electrical connection with the first wire 241 The second conductive microhole 283.

The second wire 281 can be deposited as a conductive layer by various techniques, including electroplating, electroless plating, sputtering, and combinations thereof, and then pattern the conductive layer by various methods, including wet etching, electrochemical etching, etc. , laser-assisted etching and its combination with an etching mask (not shown), so as to define the second wire 281 . Preferably, the first wire 241 and the second wire 281 use the same material and have the same thickness.

The interposer 31 and the reinforcing layer 41 are attached to the first dielectric layer 21 via the adhesive 131 , the adhesive 131 contacts the interposer 31 and the first dielectric layer 21 , and is interposed between the interposer 31 and the first dielectric layer 21 , and between the reinforcement layer 41 and the first dielectric layer 21, the interposer 31 and the reinforcement layer 41 are held with each other by the spacers 113 between the interposer 31 and the reinforcement layer 41 and the connection pads 111 of the coreless substrate 20 distance. The positioning piece 113, the connection pad 111, and the configuration guide 115 extend upward from the first dielectric layer 21, wherein the positioning piece 113 is close to the peripheral edge of the interposer 31, and the connection pad 111 is located on the peripheral edge of the positioning piece 113 and the reinforcement layer 41 between the inner side walls, and the configuration guide 115 is close to the peripheral edge of the outer side wall of the reinforcing layer 41 . The adhesive 131 contacts the positioning member 113, the connection pad 111, and the configuration guide 115, and is coplanar with the positioning member 113, the connection pad 111, and the configuration guide 115 in the downward direction, and is lower than the positioning member 113 in the upward direction. , the connection pad 111 , and the configuration guide 115 .

As shown in FIG. 1J , the connection pads 111 of the coreless substrate 21 and the bonding fingers 316 of the interposer 31 are electrically connected by bonding wires 321 , and the semiconductor chip is bonded via the solder bumps 61 on the first contact pads 312 of the interposer 31 . 51 is flip-chip on the first surface 311 of the interposer 31 . The first wire 241 of the coreless substrate 20 is in direct contact with the second contact pad 314 of the interposer 31 . The first wire 241 is also in direct contact with the connection pad 111 , and the connection pad 111 of the coreless substrate 21 is electrically connected to the bonding finger 316 of the interposer 31 through the bonding wire 321 . Therefore, the electrical connection between the interposer 31 and the coreless substrate 20 is flexibly connected through the combination of the bonding wire 321 and the first conductive microhole 243 , and there is no solder between the interposer 31 and the coreless substrate 20 . Accordingly, after flip-chip assembly, the connection between the semiconductor chip 51 and the coreless substrate 20 can be via the first contact pad 312 of the interposer 31, the conductive through hole 318, and the second contact pad 314 of the interposer 31, and then It is connected to the coreless substrate 20 through the microvias, while passing through the bonding fingers 316 of the interposer 31 , and then connected to the coreless substrate 20 by wire bonding.

FIG. 1K is a cross-sectional view of a semiconductor device 210 with another semiconductor chip 53 attached on the coreless substrate 20 . The semiconductor chip 53 is aligned on the interposer 31 and electrically connected to the coreless substrate 20 via the solder bumps 63 on the interconnection pads 284 exposed from the opening 293 of the solder mask material 291 . Accordingly, the semiconductor chips 51 , 53 can be electrically connected to each other via the interposer 31 , the coreless substrate 20 , and the solder bumps 61 , 63 .

In addition, the remaining inner connection pad 284 exposed from the opening 293 of the solder mask material 291 can accommodate a conductive contact, such as a solder bump, solder ball, pin, and the like, as an electrical connection to other components or external components. Sexual interconnection and mechanical attachment. The solder mask opening 293 can be formed by various methods, including photolithography, laser drilling, and plasma etching.

[Example 2]

FIG. 2 is a structural cross-sectional view of another three-dimensional device 310 according to another embodiment of the present invention with an additional first conductive microhole 243 directly contacting the interposer 41 for grounding or electrical connection with passive components. FIG. 2 also shows the sealing material 71 and the heat sink 81 . The sealing material 71 (such as molding compound) fills the via hole 411 in an upward direction and covers the connection pad 111 , the spacer 113 , the first dielectric layer 21 , and the interposer 31 . A heat sink 81 (such as copper or aluminum) is attached to the reinforcement layer 41 and the semiconductor chip 51 via a thermally conductive adhesive 801 to assist heat dissipation, and the heat sink 81 covers the reinforcement layer 41 , the sealing material 71 , and the semiconductor chip 51 in an upward direction.

The above-mentioned semiconductor components and circuit boards are only illustrative examples, and the present invention can also be realized through other various embodiments. In addition, the above-mentioned embodiments may be mixed and matched with each other or used with other embodiments based on design and reliability considerations. For example, the reinforcement layer may include ceramic materials or epoxy-based laminates, and may be embedded with single-layer wires or multi-layer wires. The stiffener can include multiple vias to accommodate additional interposers, passives, or other electronic components, and the coreless substrate can include additional wires to accommodate high I/O components, passives, or other electronic components .

As shown in the above embodiments, the semiconductor device of the present invention can be used alone or share an interposer with other semiconductor devices. For example, a single semiconductor device can be disposed on the interposer, or multiple semiconductor devices can be disposed on the interposer. For example, four small chips arranged in a 2x2 array can be attached to an interposer that provides additional electrical connection points for additional chips to receive routing for additional chip pads. This approach is more economical than providing an interposer per chip. Likewise, the vias of the stiffener may include sets of spacers to accommodate additional interposers therein, and the build-up circuitry may include additional wires to accommodate additional interposers.

The semiconductor device in this case can be packaged or unpackaged chips. In addition, the semiconductor element can be a bare chip or a wafer level packaged die, etc. A variety of connection media can be used to mechanically and electrically connect the semiconductor device to the interposer, including using gold or solder bumps. The spacer can be customized according to the interposer. For example, the pattern of the spacer can be square or rectangular, so as to be the same or similar to the shape of the interposer. A heat dissipation element such as a heat sink or a heat sink can be attached to the semiconductor element via thermally conductive adhesive or solder material, and the heat dissipation element can also be attached to the reinforcement layer to extend the contact area to increase the efficiency of the heat dissipation path of the semiconductor element.

As used herein, the word "adjacent" means that the elements are integrally formed (form a single body) or contact each other (without spacing or separation from each other). For example, the first wire is adjacent to the second contact pad, but not adjacent to the first contact pad.

The term "overlapping" means overlying and extending within the perimeter of an underlying element. "Overlapping" includes extending within, outside, or within the perimeter. For example, when the second contact pad surface of the interposer faces upward, the stiffener overlaps the dielectric layer, because an imaginary vertical line can run through the stiffener and the dielectric layer at the same time, regardless of whether the stiffener and the dielectric Whether there is another element (such as adhesive) that is also penetrated by the imaginary vertical line between the layers, and regardless of whether there is another imaginary vertical line that only penetrates the dielectric layer and does not penetrate the reinforcement layer (the passage located in the reinforcement layer inside the hole). Likewise, the adhesive overlaps the dielectric layer, the reinforcement layer overlaps the adhesive, and the reinforcement layer is overlapped by the adhesive. Also, "overlapping" is synonymous with "on top", and "overlapped" is synonymous with "below".

The term "contact" means direct contact. For example, the wire contacts the second contact pad but not the first contact pad.

The term "coverage" means incomplete as well as complete coverage in vertical and/or lateral directions. For example, when the first contact pad surface of the interposer faces upward, the coreless substrate covers the interposer downwardly, but the interposer does not cover the coreless substrate upwardly.

The word "layer" includes patterned and unpatterned layers. For example, when the metal layer is disposed on the dielectric layer, the metal layer can be a blank unlithographic and wet-etched slab. Additionally, a "layer" may include multiple overlapping layers.

The terms "opening", "through-hole" and "perforation" mean a through-hole. For example, when the first contact pad surface of the interposer faces upward, the interposer is inserted into the through hole of the reinforcement layer, and is exposed from the reinforcement layer in the upward direction.

The term "interposition" refers to relative movement between elements. For example, "inserting the interposer into the through hole" means that the interposer moves toward the reinforcement regardless of whether the reinforcement layer is fixed; the interposer is fixed and moves from the reinforcement layer to the interposer; are close to each other. As another example, “inserting (or extending) the interposer into the via hole” includes: penetrating (into and out of) the via hole; and inserted but not penetrated (into but not out of) the via hole.

The term "alignment" refers to the relative position of elements, whether the elements are spaced apart from each other or adjacent to each other, or one element is inserted and extends into another element. For example, when an imaginary horizontal lineman wears the spacer and the interposer, the spacer is laterally aligned with the interposer, regardless of whether there are other elements between the spacer and the interposer that are penetrated by the imaginary horizontal line, and regardless of whether there is another An imaginary horizontal line that runs through the interposer but not through the spacer. Likewise, the first microhole is aligned with the second contact pad of the interposer, and the interposer and the spacer are aligned with the through hole.

The term "near" means that the width of the gap between elements does not exceed the maximum acceptable range. As is generally known in the art, when the gap between the interposer and the spacer is not narrow enough, the position error caused by the lateral displacement of the interposer in the gap may exceed the acceptable maximum error limit. Once the position of the interposer is When the error exceeds the maximum limit, it is impossible to use the laser beam to align the contact pad, resulting in an electrical connection error between the interposer and the coreless substrate. Therefore, according to the size of the contact pad of the interposer, those skilled in the art can confirm the maximum acceptable range of the gap between the interposer and the spacer through trial and error, so as to avoid the electrical connection between the interposer and the coreless substrate. mistake. Thus, the phrase "the locator is near the peripheral edge of the interposer" means that the gap between the peripheral edge of the interposer and the locator is narrow enough to prevent the interposer position error from exceeding the maximum acceptable error limit.

The term "disposed" includes both contact and non-contact with a single or multiple supporting elements. For example, the interposer is disposed on the dielectric layer, regardless of whether the interposer actually contacts the dielectric layer or is separated from the dielectric layer by an adhesive.

The term "electrically connected" means a direct or indirect electrical connection. For example, the first wire provides an electrical connection between the inner connection pad and the second contact pad, regardless of whether the first wire adjoins the inner connection pad or is electrically connected to the inner connection pad via the second wire.

The term "above" means extending upward and includes adjoining and non-adjacent elements as well as overlapping and non-overlapping elements. For example, when the first connection pad surface of the interposer faces upward, the positioning element extends above it, adjoins the dielectric layer and protrudes from the dielectric layer.

The term "beneath" means extending downward and includes adjoining and non-adjacent elements as well as overlapping and non-overlapping elements. For example, when the second connection pad surface of the interposer faces upward, the coreless substrate extends below it, adjoins the adhesive and protrudes from the adhesive toward the downward direction. Likewise, build-up circuitry may extend below the stiffener and interposer even if it is not adjacent to the stiffener or interposer.

The "first vertical direction" and "second vertical direction" do not depend on the orientation of the component, and those skilled in the art can easily understand which directions they actually point to. For example, the first contact pad of the interposer faces a first vertical direction and the second contact pad of the interposer faces a second vertical direction, regardless of whether the device is inverted. Likewise, the locators are "sideways" aligned with the interposer along a lateral plane, regardless of whether the board is inverted, rotated, or tilted. Thus, the first and second vertical directions are opposite to each other and perpendicular to the lateral direction, and the laterally aligned elements intersect in a lateral plane perpendicular to the first and second vertical directions. Moreover, when the second contact pad surface of the interposer faces upward, the first vertical direction is the downward direction, and the second vertical direction is the upward direction; when the second contact pad surface of the interposer faces downward, the first vertical direction is downward. The vertical direction is an upward direction, and the second vertical direction is a downward direction.

The semiconductor component of the present invention has several advantages. Semiconductor components are highly reliable, affordable and very suitable for mass production. The reinforcement layer provides mechanical support, dimensional stability, and overall flatness control, and the thermal expansion of the coreless substrate (such as the interposer), even if the coefficient of thermal expansion (CTE) between the interposer and the coreless substrate is different, in the thermal cycle In this case, the interposer can still be firmly connected to the coreless substrate. There is a direct electrical connection between the interposer and the coreless substrate, and its absence of solder facilitates high I/O values and high performance. In particular, the positioning member can accurately define the position of the interposer, and avoid electrical connection errors between the interposer and the coreless substrate caused by the lateral displacement of the interposer, thereby improving the yield of production.

The fabrication method of this case is highly applicable, and combines various mature electrical connection and mechanical connection technologies in a unique and progressive way. In addition, the fabrication method in this case can be implemented without expensive tools. Therefore, compared with traditional packaging techniques, this manufacturing method can greatly improve yield, yield, performance and cost-effectiveness.

The embodiments described herein are for illustration purposes, and these embodiments may simplify or omit elements or steps known in the art to avoid obscuring the characteristics of the present invention. Likewise, for clarity of the drawings, the drawings may also omit repeated or unnecessary components and component numbers.

Those skilled in the art should be able to easily conceive of various changes and modifications to the embodiments described herein. For example, the aforementioned materials, dimensions, shapes, sizes, contents of steps and sequence of steps are just examples. Changes, adjustments and equivalents may be made by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Although the invention has been described in terms of preferred implementations, it should be understood that possible modifications and variations can be made to the invention without departing from the spirit and scope of the invention as claimed.

Claims (4)

1. a semiconductor subassembly, it is characterised in that including:

One intermediary layer, it includes that multiple first engagement pad and a joint refer on a first surface, and multiple second contact Being padded on a second surface, this first surface faces one first vertical direction, and this second surface faces and this first Vertical Square To one second contrary vertical direction, wherein, at least one this first engagement pad via a conductive through holes of this intermediary layer with electrically It is connected to this second engagement pad of a correspondence；

Semiconductor element, its upside-down mounting is arranged on this first surface of this intermediary layer, and is connected to those the first engagement pads；

One enhancement Layer, it includes a through hole, and this intermediary layer extends in this through hole；

One adhesive agent, it contacts this intermediary layer and a coreless substrate, and between this intermediary layer and this coreless substrate；And

This coreless substrate, it covers this adhesive agent, this intermediary layer and this enhancement Layer, and this centreless in this second vertical direction Substrate includes a connection gasket, and this joint that this connection gasket is electrically connected to this intermediary layer via a routing refers to, and also includes one Conduction micropore, this conduction micropore is electrically connected to this second engagement pad of this intermediary layer；

Wherein, this coreless substrate also includes positioning piece, and this keeper is aligned in this through hole of this enhancement Layer, and as this intermediary The configuration guiding element of layer, and near peripheral edge and this connection gasket of this intermediary layer, and in this intermediary layer peripheral edge with should Extend laterally between connection gasket.

Semiconductor subassembly the most according to claim 1, wherein, the electric connection between this intermediary layer and this coreless substrate is not Containing solder.

Semiconductor subassembly the most according to claim 1, wherein this connection is padded on this first vertical direction from this coreless substrate Appear, and extend laterally between the sidewall of the peripheral edge of this intermediary layer and this through hole of this enhancement Layer in lateral.

Semiconductor subassembly the most according to claim 1, wherein this coreless substrate also includes a configuration guiding element, this configuration guiding element Near the peripheral edge of this enhancement Layer, and the peripheral edge of this enhancement Layer of lateral alignment, and outside the peripheral edge of this enhancement Layer Extend laterally.