CN103580677A

CN103580677A - Drive circuit

Info

Publication number: CN103580677A
Application number: CN201210258398.XA
Authority: CN
Inventors: 李秋平
Original assignee: YUANJING TECHNOLOGY CO LTD
Current assignee: YUANJING TECHNOLOGY CO LTD
Priority date: 2012-07-24
Filing date: 2012-07-24
Publication date: 2014-02-12
Anticipated expiration: 2032-07-24
Also published as: CN103580677B

Abstract

A driving circuit for driving a power metal oxide semiconductor transistor comprises: a first driving branch and a second driving branch. The first driving branch comprises: a first switch N-type metal oxide semiconductor transistor, a current source and a first clamping P-type metal oxide semiconductor transistor connected in series. The second driving branch comprises: a second switch N-type metal oxide semiconductor transistor, a current supply P-type metal oxide semiconductor transistor and a second clamping P-type metal oxide semiconductor transistor connected in series. The first and second switch gates of the first and second switch N-type metal oxide semiconductor transistors receive a switch signal and an inverted switch signal respectively. The first and second clamping gates of the first and second clamping P-type metal oxide semiconductor transistors receive a reference voltage. The second clamping source of the second clamping P-type metal oxide semiconductor transistor outputs a driving voltage to the power gate of the power metal oxide semiconductor transistor.

Description

Drive circuit

Technical field

This disclosure relates to a kind of drives technology, and is particularly related to a kind of drive circuit.

Background technology

Electronic product has become an indispensable part in modern's life.In electronic installation miscellaneous, need to can be applicable to the semiconductor subassembly in these devices.The characteristic of semiconductor subassembly is mainly to be decided by the technique of preparing this assembly.Because semiconductor subassembly is conventionally more complicated, its technique also changes more.In semiconductor subassembly, need the multiple transistor with different qualities (particularly different operating voltage).High voltage transistor is the element that can design at the environment of operation with high pressure in order to meet.

In general, the voltage that high voltage transistor can bear can be up to more than 10 volts, and 3.3 volts or 5 volts that bear from general transistor have different greatly.For the consideration in area and element speeds, part technology has been designed to high voltage transistor only source electrode can bear high pressure with drain electrode, and grid bears the voltage (as 5 volts) that general transistor can bear.Yet, under such design, merely in order to drive general low voltage transistor and simple in order to drive the drive circuit of high voltage transistor, by thus cannot drive with suitable voltage above-mentioned high-pressure crystal tube elements.

Therefore, how designing a new drive circuit, to drive above-mentioned high-pressure crystal tube elements, is an industry problem demanding prompt solution for this reason.

Summary of the invention

Therefore, an aspect of this disclosure is that a kind of drive circuit is being provided, in order to driving power metal-oxide semiconductor (MOS) (metal-oxide semiconductor; MOS) transistor, comprises: first drives branch road and second to drive branch road.First drives branch road to comprise: the first switch N-type metal oxide semiconductor transistor, current source and the first clamp (clamping) P-type mos transistor.The first switch N-type metal oxide semiconductor transistor has the first switch gate, in order to receiving key signal.The first clamp P-type mos transistor has the first clamp gates, in order to receive reference voltage, wherein transistorized the first clamp drain electrode of the first clamp P-type mos is connected in the first switch drain of the first switch N-type metal oxide semiconductor transistor, and transistorized the first clamp source electrode of the first clamp P-type mos is connected in current source.Second drives branch road to comprise: second switch N-type metal oxide semiconductor transistor, electric current supply P-type mos transistor and the second clamp P-type mos transistor.Second switch N-type metal oxide semiconductor transistor has second switch grid, in order to receive anti-phase switching signal.Electric current supply P-type mos transistor has the electric current supply source electrode that is connected in the electric current supply grid of the first clamp source electrode and is connected in the first current potential.The second clamp P-type mos transistor has the second clamp gates, in order to receive reference voltage, wherein transistorized the second clamp drain electrode of the second clamp P-type mos is connected in the second switch drain electrode of second switch N-type metal oxide semiconductor transistor, and transistorized the second clamp source electrode of the second clamp P-type mos is connected in the transistorized electric current supply drain electrode of electric current supply P-type mos.Wherein the second clamp source electrode outputting drive voltage is to the power grid of power MOS transistor.

According to this disclosure one embodiment, wherein the first current potential is positive potential.

According to another embodiment of this disclosure, wherein power MOS transistor is high voltage most (high voltage MOS; HVMOS).The voltage difference of driving voltage and the first current potential is less than specific voltage value.The minimum value of driving voltage be reference voltage and the transistorized threshold value of the second clamp P-type mos (threshold) voltage and.

According to the another embodiment of this disclosure, wherein reference voltage is the highest withstand voltage poor of the first current potential and power grid.

According to this disclosure embodiment again, when control signal is the first state, make the first switch N-type metal oxide semiconductor transistor conducting and second switch N-type metal oxide semiconductor transistor is closed, further make the second clamp P-type mos transistor turns and make driving voltage rise to close power MOS transistor.When control signal is the second state, the first switch N-type metal oxide semiconductor transistor closed and make the conducting of second switch N-type metal oxide semiconductor transistor, further making the second clamp P-type mos transistor close and this driving voltage declines with conducting power MOS transistor.

This disclosure be that a kind of drive circuit is being provided on the other hand, in order to driving power metal oxide semiconductor transistor, comprise: first drives branch road and second to drive branch road.First drives branch road to comprise: the first switch P type metal oxide semiconductor transistor, current source and the first clamp N-type metal oxide semiconductor transistor.The first switch P type metal oxide semiconductor transistor has the first switch gate, in order to receiving key signal.The first clamp N-type metal oxide semiconductor transistor has the first clamp gates, in order to receive reference voltage, wherein the first clamp drain electrode of the first clamp N-type metal oxide semiconductor transistor is connected in the first switch drain of the first switch N-type metal oxide semiconductor transistor, and the first clamp source electrode of the first clamp N-type metal oxide semiconductor transistor is connected in current source.Second drives branch road to comprise: second switch P-type mos transistor, electric current supply N-type metal oxide semiconductor transistor and the second clamp N-type metal oxide semiconductor transistor.Second switch P-type mos transistor has second switch grid, in order to receive anti-phase switching signal.Electric current supply N-type metal oxide semiconductor transistor has the electric current supply source electrode that is connected in the electric current supply grid of the first clamp source electrode and is connected in the first current potential.The second clamp N-type metal oxide semiconductor transistor has the second clamp gates, in order to receive reference voltage, wherein the second clamp drain electrode of the second clamp N-type metal oxide semiconductor transistor is connected in the transistorized second switch drain electrode of second switch P-type mos, and the second clamp source electrode of the second clamp N-type metal oxide semiconductor transistor is connected in the electric current supply drain electrode of electric current supply N-type metal oxide semiconductor transistor.Wherein the second clamp source electrode outputting drive voltage is to the power grid of power MOS transistor.

According to this disclosure one embodiment, wherein the first current potential is negative potential.

According to another embodiment of this disclosure, wherein power MOS transistor is high voltage most (high voltage MOS; HVMOS).The voltage difference of driving voltage and the first current potential is less than specific voltage value.The maximum of driving voltage is the poor of reference voltage and the transistorized threshold value of the second clamp P-type mos (threshold) voltage.

According to the another embodiment of this disclosure, wherein reference voltage be the first current potential and power grid the highest withstand voltage and.

According to this disclosure embodiment again, when control signal is the first state, make the first switch P type metal oxide semiconductor transistor turns and second switch P-type mos transistor is closed, further make the second clamp N-type metal oxide semiconductor transistor conducting and make driving voltage decline to close power MOS transistor.When control signal is the second state, make the first switch P type metal oxide semiconductor transistor close and make second switch P-type mos transistor turns, further make the second clamp N-type metal oxide semiconductor transistor close and make driving voltage increase with conducting power MOS transistor.

The advantage of applying this disclosure is the design by drive circuit, driving voltage in order to driving power metal oxide semiconductor transistor can be limited, avoid it to surpass the scope that power MOS transistor can bear, and reach easily above-mentioned object.

Accompanying drawing explanation

For above and other object, feature, advantage and the embodiment of this disclosure can be become apparent, the description of the drawings is as follows:

Fig. 1 is in this disclosure one embodiment, a kind of circuit diagram of drive circuit; And

Fig. 2 is in another embodiment of this disclosure, a kind of circuit diagram of drive circuit.

[main element symbol description]

1,2: drive circuit 10,20: the first driving branch roads

100,200: current source 12,22: the second driving branch roads

Embodiment

Please refer to Fig. 1.Fig. 1 is in this disclosure one embodiment, a kind of circuit diagram of drive circuit 1.Drive circuit 1 is in order to driving power metal-oxide semiconductor (MOS) (metal-oxide semiconductor; MOS) transistor MP0.

In the present embodiment, power MOS transistor MP0 is P type high voltage most.High voltage most (high voltage MOS; HVMOS) for can bear high-tension transistor, in one embodiment, refer to and can bear to approximately 10 volts or above high pressure, be different from general common withstand voltage (as 3.3 volts or 5 volts).In some semiconductor fabrications, can produce and there is source electrode and the drain electrode that can bear high pressure, and grid only can bear the power MOS transistor of small voltage (as 5 volts).The power MOS transistor designing in this way, can be under the less situation of area, reach power MOS transistor conducting resistance (RDS (on)) is diminished, further reach the transmission delay of power MOS transistor is reduced and rise time (rising time) and effect that fall time, (falling time) diminished.For making the power MOS transistor of the above-mentioned type, can when driving, avoid the voltage driving to surpass the voltage that grid can be loaded, need to design the drive circuit of the scope that can limit driving voltage, to meet the demand of the power MOS transistor of this type.

Drive circuit 1 comprises: first drives branch road 10 and second to drive branch road 12.First drives branch road 10 to comprise: the first switch N-type metal oxide semiconductor transistor MN1, current source 100 and the first clamp (clamping) P-type mos transistor MP1.

The first switch N-type metal oxide semiconductor transistor MN1 has the first switch gate G11, in order to receiving key signal IN.The first switch N-type metal oxide semiconductor transistor MN1 has more the first switch source S11, to be connected to the second current potential VSS.

The first clamp P-type mos transistor MP1 has the first clamp gates G12, in order to receive reference voltage Vm.Wherein, the first clamp drain D 12 of the first clamp P-type mos transistor MP1 is connected in the first switch drain D11 of the first switch N-type metal oxide semiconductor transistor MN1, and the first clamp source S 12 of the first clamp P-type mos transistor MP1 is connected in current source 100.

Second drives branch road 12 to comprise: second switch N-type metal oxide semiconductor transistor MN2, the second clamp P-type mos transistor MP2 and electric current supply P-type mos transistor MP3.Second switch N-type metal oxide semiconductor transistor MN2 has second switch grid G 21, in order to receive anti-phase switching signal

Electric current supply P-type mos transistor MP3 has the electric current supply source electrode S3 that is connected in the electric current supply grid G 3 of the first clamp source S 12 and is connected in the first current potential VGH.The second clamp P-type mos transistor MP2 has the second clamp gates G22, in order to receive reference voltage Vm.The second clamp source S 22 that wherein the second clamp drain D 22 of the second clamp P-type mos transistor MP2 is connected in second switch drain D 22, the second clamp P-type mos transistor MP2 of second switch N-type metal oxide semiconductor transistor MN2 is connected in the electric current supply drain D 3 of electric current supply P-type mos transistor MP3.Wherein, the second clamp source S 22 outputting drive voltage Vp are to the power grid G 0 of power MOS transistor MP0.

In one embodiment, the first above-mentioned current potential VGH is positive potential, and the second current potential VSS is the current potential that is less than the first current potential VGH.In one embodiment, the second current potential VSS can be earthing potential.

Therefore,, when control signal IN is high state, will makes the first switch N-type metal oxide semiconductor transistor MN1 conducting and second switch N-type metal oxide semiconductor transistor MN2 is closed.The conducting of the first switch N-type metal oxide semiconductor transistor MN1 will make to draw the electric current that current source 100 produces, and its ability of drawing electric current will be greater than the magnitude of current of current source 100 generations.Therefore, the voltage of the first clamp source S 12 of the first clamp P-type mos transistor MP1, that is the voltage of controlling the electric current supply grid G 3 of the second clamp P-type mos transistor MP3 will be dragged down thereupon, further make the second clamp P-type mos transistor MP3 conducting.

On the other hand, after second switch N-type metal oxide semiconductor transistor MN2 closes, because the second clamp P-type mos transistor MP3 conducting will provide current to electric current supply drain D 3, so the voltage of electric current supply drain D 3 will rise gradually.Because electric current is supplied the second clamp source S 22 that drain D 3 is the second clamp P-type mos transistor MP2, so the voltage of electric current supply drain D 3 will make the second clamp P-type mos transistor MP2 conducting.And the voltage of electric current supply drain D 3 is also the driving voltage Vp of the power grid G 0 of power ratio control metal oxide semiconductor transistor MP0 simultaneously, so power MOS transistor MP0 will close under the voltage rising in electric current supply drain D 3.

And when control signal IN is low state, will makes the first switch N-type metal oxide semiconductor transistor MN1 close and make second switch N-type metal oxide semiconductor transistor MN2 conducting.The first closing of switch N-type metal oxide semiconductor transistor MN1 will stop drawing current source 100, therefore the voltage of the first clamp source S 12 of the first clamp P-type mos transistor MP1 will be made, that is the voltage of controlling the electric current supply grid G 3 of the second clamp P-type mos transistor MP3 will be drawn high thereupon, further make the second clamp P-type mos transistor MP3 close.

On the other hand, after second switch N-type metal oxide semiconductor transistor MN2 conducting, because the second clamp P-type mos transistor MP3 closes, second switch N-type metal oxide semiconductor transistor MN2 is provided to the electric current of electric current supply drain D 3 by the second clamp P-type mos transistor MP3 drawing originally, so the voltage of electric current supply drain D 3 will decline gradually.Because electric current supply drain D 3 is the second clamp source S 22 of the second clamp P-type mos transistor MP2, so the voltage of ultimate current supply drain D 3 will make the second clamp P-type mos transistor MP2 conducting and closing again.

Yet should be noted, if the threshold voltage of the second clamp P-type mos transistor MP2 is Vth, the voltage of accepting due to its second clamp gates G22 is reference voltage Vm, the voltage of electric current supply drain D 3 be down to reference voltage Vm and the transistorized threshold voltage vt h of the second clamp P-type mos and when (being Vm+Vth), to make the second clamp P-type mos transistor MP2 close, and further make second switch N-type metal oxide semiconductor transistor MN2 cannot draw again electric current.Therefore, the minimum Vm+Vth that only can be down to of voltage of electric current supply drain D 3 cannot decline again.

The voltage of electric current supply drain D 3 is also the driving voltage Vp of the power grid G 0 of power ratio control metal oxide semiconductor transistor MP0 simultaneously, so power MOS transistor MP0 is by conducting under the voltage drop in electric current supply drain D 3.Because the voltage of electric current supply drain D 3 is minimum, only can be down to Vm+Vth, so the voltage difference of driving voltage Vp and the first current potential VGH will be less than a specific voltage value.In the present embodiment, this specific voltage value is VGH-(Vm+Vth).

In one embodiment, the value of reference voltage Vm can be set as the highest withstand voltage poor of the first current potential VGH and power grid G 0.If the highest withstand voltage of power grid G 0 is 5 volts, the value of reference voltage Vm can be set as VGH-5.Therefore the specific voltage value that, the voltage difference of driving voltage Vp and the first current potential VGH is less than will be VGH-(VGH-5+Vth)=5-Vth.The value of driving voltage Vp can be by the design of drive circuit 1 by below clamp to 5 volt.

Therefore, in this disclosure, in order to the drive circuit 1 of driving power metal oxide semiconductor transistor MP0, can guarantee that the value of driving voltage Vp is limited in voltage range that the power grid G 0 of power MOS transistor MP0 can bear, and make power MOS transistor MP0 can under the driving of drive circuit 1, maintain normal running.

Please refer to Fig. 2.Fig. 2 is in another embodiment of this disclosure, a kind of circuit diagram of drive circuit 2.Drive circuit 2 is in order to driving power metal oxide semiconductor transistor MN0.Similarly, in the present embodiment, power MOS transistor MN0 is N-type high voltage most.

Drive circuit 2 comprises: first drives branch road 20 and second to drive branch road 22.First drives branch road 20 to comprise: the first switch P type metal oxide semiconductor transistor MP1, current source 200 and the first clamp P-type mos transistor MN1.

The first switch P type metal oxide semiconductor transistor MP1 has the first switch gate G11, in order to receiving key signal IN.The first switch P type metal oxide semiconductor transistor MP1 has more the first switch source S11, to be connected to the second current potential VDD.

The first clamp N-type metal oxide semiconductor transistor MN1 has the first clamp gates G12, in order to receive reference voltage Vm.Wherein, the first clamp drain D 12 of the first clamp N-type metal oxide semiconductor transistor MN1 is connected in the first switch drain D11 of the first switch P type metal oxide semiconductor transistor MP1, and the first clamp source S 12 of the first clamp N-type metal oxide semiconductor transistor MN1 is connected in current source 200.

Second drives branch road 22 to comprise: second switch P-type mos transistor MP2, the second clamp N-type metal oxide semiconductor transistor MN2 and electric current supply N-type metal oxide semiconductor transistor MN3.Second switch P-type mos transistor MP2 has second switch grid G 21, in order to receive anti-phase switching signal

Electric current supply N-type metal oxide semiconductor transistor MN3 has the electric current supply source electrode S3 that is connected in the electric current supply grid G 3 of the first clamp source S 12 and is connected in the first current potential VGL.The second clamp N-type metal oxide semiconductor transistor MN2 has the second clamp gates G22, in order to receive reference voltage Vm.The second clamp source S 22 that wherein the second clamp drain D 22 of the second clamp N-type metal oxide semiconductor transistor MN2 is connected in second switch drain D 22, the second clamp N-type metal oxide semiconductor transistor MN2 of second switch P-type mos transistor MP2 is connected in the electric current supply drain D 3 of electric current supply P-type mos transistor MN3.Wherein, the second clamp source S 22 outputting drive voltage Vp are to the power grid G 0 of power MOS transistor MN0.

In one embodiment, the first above-mentioned current potential VGL is negative potential, and the second current potential VDD is the current potential that is greater than the first current potential VGL.

Therefore,, when control signal IN is low state, will makes the first switch P type metal oxide semiconductor transistor MP1 conducting and second switch P-type mos transistor MP2 is closed.The conducting of the first switch P type metal oxide semiconductor transistor MP1 will provide large electric current, and its ability that electric current is provided is by the magnitude of current that is greater than current source 200 and draws.Therefore, the voltage of the first clamp source S 12 of the first clamp N-type metal oxide semiconductor transistor MN1, that is the voltage of controlling the electric current supply grid G 3 of the second clamp N-type metal oxide semiconductor transistor MN3 will be drawn high thereupon, further make the second clamp N-type metal oxide semiconductor transistor MN3 conducting.

On the other hand, after second switch P-type mos transistor MP2 closes, because the second clamp N-type metal oxide semiconductor transistor MN3 conducting will be supplied drain D 3 to electric current and be drawn electric current, so the voltage of electric current supply drain D 3 will decline gradually.Because electric current is supplied the second clamp source S 22 that drain D 3 is the second clamp N-type metal oxide semiconductor transistor MN2, so the voltage of electric current supply drain D 3 will make the second clamp N-type metal oxide semiconductor transistor MN2 conducting.And the voltage of electric current supply drain D 3 is also the driving voltage Vp of the power grid G 0 of power ratio control metal oxide semiconductor transistor MN0 simultaneously, so power MOS transistor MN0 will close under the voltage drop in electric current supply drain D 3.

And when control signal IN is high state, will makes the first switch P type metal oxide semiconductor transistor MP1 close and make second switch P-type mos transistor MP2 conducting.The first switch P type metal oxide semiconductor transistor MP1 closes stop supplies electric current, and make current source 100 continue to draw electric current, therefore the voltage of the first clamp source S 12 of the first clamp N-type metal oxide semiconductor transistor MN1 will be made, that is the voltage of controlling the electric current supply grid G 3 of the second clamp N-type metal oxide semiconductor transistor MN3 will be dragged down thereupon, further make the second clamp N-type metal oxide semiconductor transistor MP3 close.

On the other hand, after second switch P-type mos transistor MP2 conducting, because the second clamp N-type metal oxide semiconductor transistor MN3 closes, second switch P-type mos transistor MP2 will provide current to supply drain D 3, so the voltage of electric current supply drain D 3 will rise gradually.Because electric current supply drain D 3 is the second clamp source S 22 of the second clamp N-type metal oxide semiconductor transistor MN2, so the voltage of ultimate current supply drain D 3 will make the second clamp N-type metal oxide semiconductor transistor MN2 conducting and closing again.

Yet should be noted, if the threshold voltage of the second clamp N-type metal oxide semiconductor transistor MN2 is Vth, the voltage of accepting due to its second clamp gates G22 is reference voltage Vm, the voltage of electric current supply drain D 3 is when rising to poor (being Vm-Vth) of reference voltage Vm and the transistorized threshold voltage vt h of the second clamp P-type mos, to make the second clamp P-type mos transistor MN2 close, and further make second switch N-type metal oxide semiconductor transistor MP2 cannot provide current to again electric current supply drain D 3.Therefore, the highest Vm-Vth that only can rise to of voltage of electric current supply drain D 3 cannot rise again.

The voltage of electric current supply drain D 3 is also the driving voltage Vp of the power grid G 0 of power ratio control metal oxide semiconductor transistor MN0 simultaneously, so power MOS transistor MN0 is by conducting under the voltage rising in electric current supply drain D 3.Because the voltage of electric current supply drain D 3 is the highest, only can rise to Vm-Vth, so the voltage difference of driving voltage Vp and the first current potential VGH will be less than a specific voltage value.In the present embodiment, this specific voltage value is (Vm-Vth)-VGL.

In one embodiment, the value of reference voltage Vm can be set as the first current potential VGL and power grid G 0 the highest withstand voltage and.If the highest withstand voltage of power grid G 0 is 5 volts, the value of reference voltage Vm can be set as VGL+5.Therefore the specific voltage value that, the voltage difference of driving voltage Vp and the first current potential VGH is less than will be (VGL+5-Vth)-VGL=5-Vth.The value of driving voltage Vp can be by the design of drive circuit 1 by below clamp to 5 volt.

Therefore, in this disclosure, in order to the drive circuit 2 of driving power metal oxide semiconductor transistor MN0, can guarantee that the value of driving voltage Vp is limited in voltage range that the power grid G 0 of power MOS transistor MN0 can bear, and make power MOS transistor MN0 can under the driving of drive circuit 2, maintain normal running.

Although this disclosure with execution mode openly as above; so it is not in order to limit this disclosure; those skilled in the art; within not departing from the spirit and scope of this disclosure; when being used for a variety of modifications and variations, so the protection range of this disclosure is when being as the criterion depending on the appended claims person of defining.

Claims

1. A driving circuit for driving a power metal-oxide semiconductor (MOS) transistor, comprising:

A first drive branch, comprising:

A first switch N-type metal-oxide-semiconductor transistor having a first switch gate for receiving a switch signal;

a current source; and

A first clamping (clamping) P-type metal oxide semiconductor transistor has a first clamping gate for receiving a reference voltage, wherein a first clamping of the first clamping P-type metal oxide semiconductor transistor The bit drain is connected to a first switch drain of the first switch NMOS transistor, and a first clamp source of the first clamp PMOS transistor is connected to the current source; as well as

A second drive branch, comprising:

A second switch N-type metal-oxide-semiconductor transistor, having a second switch gate, for receiving the switch signal in reverse phase;

a current supply PMOS transistor having a current supply gate connected to the first clamp source and a current supply source connected to a first potential; and

A second clamping PMOS transistor has a second clamping gate for receiving the reference voltage, wherein a second clamping drain of the second clamping PMOS transistor connected to a second switch drain of the second switch NMOS transistor, and a second clamp source of the second clamped PMOS transistor connected to the current supply PMOS transistor A current supply drain of the material semiconductor transistor;

Wherein the second clamping source outputs a driving voltage to a power gate of the power metal oxide semiconductor transistor.

2. The driving circuit as claimed in claim 1, wherein the first potential is a positive potential.

3. The driving circuit as claimed in claim 1, wherein the power metal oxide semiconductor transistor is a high voltage metal oxide semiconductor transistor (high voltage MOS; HVMOS).

4. The driving circuit as claimed in claim 3, wherein a voltage difference between the driving voltage and the first potential is smaller than a specific voltage value.

5. The driving circuit as claimed in claim 4, wherein a minimum value of the driving voltage is a sum of the reference voltage and a threshold voltage of the second clamped PMOS transistor.

6. The driving circuit as claimed in claim 5, wherein the reference voltage is the difference between the first potential and a maximum withstand voltage of the power gate.

7. The driving circuit as claimed in claim 1, wherein when the control signal is in a first state, the first switch NMOS transistor is turned on and the second switch NMOS transistor is turned on. turn off, further turn on the second clamping PMOS transistor and increase the driving voltage to turn off the power MOS transistor.

8. The drive circuit according to claim 7, wherein when the control signal is in a second state, the first switch NMOS transistor is turned off and the second switch NMOS transistor is turned on turn on, further turn off the second clamping PMOS transistor and lower the driving voltage to turn on the power MOS transistor.

9. A driving circuit for driving a power metal oxide semiconductor transistor, comprising:

A first drive branch, comprising:

A first switch PMOS transistor, having a first switch gate, for receiving a switch signal;

a current source; and

A first clamping N-type metal oxide semiconductor transistor has a first clamping gate for receiving a reference voltage, wherein a first clamping drain of the first clamping N-type metal oxide semiconductor transistor connected to a first switch drain of the first switch NMOS transistor, a first clamp source of the first clamp NMOS transistor connected to the current source; and

A second drive branch, comprising:

A second switch P-type metal oxide semiconductor transistor, having a second switch gate, for receiving the switch signal in reverse phase;

a current supply NMOS transistor having a current supply gate connected to the first clamp source and a current supply source connected to a first potential; and

A second clamping NMOS transistor has a second clamping gate for receiving the reference voltage, wherein a second clamping drain of the second clamping NMOS transistor connected to a second switch drain of the second switch PMOS transistor, a second clamp source of the second clamp NMOS transistor connected to the current supply NMOS A current supply drain of the material semiconductor transistor;

10. The driving circuit as claimed in claim 9, wherein the first potential is a negative potential.

11. The driving circuit as claimed in claim 9, wherein the power MOS transistor is a high voltage MOS transistor.

12. The driving circuit as claimed in claim 11, wherein a voltage difference between the driving voltage and the first potential is smaller than a specific voltage value.

13. The driving circuit as claimed in claim 12, wherein a maximum value of the driving voltage is a difference between the reference voltage and a threshold voltage of the second clamped NMOS transistor.

14. The driving circuit as claimed in claim 13, wherein the reference voltage is a sum of the first potential and a maximum withstand voltage of the power gate.

15. The driving circuit as claimed in claim 9, wherein when the control signal is in a first state, the first switch PMOS transistor is turned on and the second switch PMOS transistor is turned on. turn off, further turn on the second clamping NMOS transistor and lower the driving voltage to turn off the power MOS transistor.

16. The drive circuit according to claim 15, wherein when the control signal is in a second state, the first switch PMOS transistor is turned off and the second switch PMOS transistor is turned on turn on, further turn off the second clamping NMOS transistor and increase the driving voltage to turn on the power MOS transistor.