CN103579373B - A kind of Trench-structure charge compensation Schottky semiconductor device and its manufacture method - Google Patents
A kind of Trench-structure charge compensation Schottky semiconductor device and its manufacture method Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 120
- 238000000034 method Methods 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 66
- 239000002184 metal Substances 0.000 claims description 33
- 229910052751 metal Inorganic materials 0.000 claims description 33
- 230000004888 barrier function Effects 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 8
- 239000011810 insulating material Substances 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 238000001465 metallisation Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 2
- 239000012774 insulation material Substances 0.000 claims 4
- 238000000137 annealing Methods 0.000 claims 1
- 238000005260 corrosion Methods 0.000 claims 1
- 230000007797 corrosion Effects 0.000 claims 1
- 230000003628 erosive effect Effects 0.000 claims 1
- 238000001459 lithography Methods 0.000 claims 1
- 230000000903 blocking effect Effects 0.000 abstract description 2
- 239000002210 silicon-based material Substances 0.000 description 19
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 125000004437 phosphorous atom Chemical group 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 238000005245 sintering Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/60—Schottky-barrier diodes
- H10D8/605—Schottky-barrier diodes of the trench conductor-insulator-semiconductor barrier type, e.g. trench MOS barrier Schottky rectifiers [TMBS]
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- H—ELECTRICITY
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- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/109—Reduced surface field [RESURF] PN junction structures
- H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
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Abstract
Description
技术领域technical field
本发明涉及到一种沟槽结构电荷补偿肖特基半导体装置，本发明还涉及一种沟槽结构电荷补偿肖特基半导体装置的制造方法。本发明的半导体装置是制造功率整流器件的基本结构。The invention relates to a charge compensation Schottky semiconductor device with a trench structure, and also relates to a method for manufacturing the charge compensation Schottky semiconductor device with a trench structure. The semiconductor device of the present invention is a basic structure for manufacturing power rectifying devices.
背景技术Background technique
功率半导体器件被大量使用在电源管理和电源应用上，特别涉及到肖特基结的半导体器件已成为器件发展的重要趋势，肖特基器件具有正向开启电压低开启关断速度快等优点，同时肖特基器件也具有反向漏电流大，不能被应用于高压环境等缺点。Power semiconductor devices are widely used in power management and power applications, especially semiconductor devices involving Schottky junctions have become an important trend in device development. Schottky devices have the advantages of low forward turn-on voltage and fast turn-on and turn-off speed. At the same time, Schottky devices also have disadvantages such as large reverse leakage current and cannot be used in high-voltage environments.
肖特基二极管可以通过多种不同的布局技术制造，最常用的为平面布局，传统的平面肖特基二极管在漂移区具有突变的电场分布曲线，影响了器件的反向击穿特性，同时传统的平面肖特基二极管具有较高的导通电阻。Schottky diodes can be manufactured through a variety of different layout techniques, the most commonly used is planar layout, the traditional planar Schottky diode has a sudden electric field distribution curve in the drift region, which affects the reverse breakdown characteristics of the device, while the traditional The planar Schottky diode has a high on-resistance.
发明内容Contents of the invention
本发明针对上述问题提出，提供一种沟槽结构电荷补偿肖特基半导体装置及其制造方法。In view of the above problems, the present invention provides a charge compensation Schottky semiconductor device with a trench structure and a manufacturing method thereof.
一种沟槽结构电荷补偿肖特基半导体装置，其特征在于：包括：衬底层，为半导体材料构成；漂移层，为第一导电半导体材料构成，位于衬底层之上；多个沟槽结构，沟槽位于漂移层中，漂移层中临靠沟槽内壁区域设置有第二导电半导体材料，沟槽内壁表面设置有绝缘材料，沟槽内填充半导体材料；肖特基势垒结，位于漂移层第一导电半导体材料上表面。A charge compensation Schottky semiconductor device with a trench structure, characterized in that it includes: a substrate layer made of a semiconductor material; a drift layer made of a first conductive semiconductor material and located on the substrate layer; a plurality of trench structures, The trench is located in the drift layer, a second conductive semiconductor material is provided in the drift layer adjacent to the inner wall of the trench, an insulating material is provided on the inner wall surface of the trench, and the semiconductor material is filled in the trench; the Schottky barrier junction is located in the drift layer The upper surface of the first conductive semiconductor material.
一种沟槽结构电荷补偿肖特基半导体装置的制造方法，其特征在于：包括如下步骤：在衬底层表面形成第一导电半导体材料层，然后表面形成绝缘材料层；进行光刻腐蚀工艺去除表面部分绝缘材料层，然后刻蚀去除部分裸露半导体材料形成沟槽；在沟槽内进行第二导电杂质扩散；在沟槽内壁表面形成绝缘材料，淀积多晶半导体材料，反刻蚀多晶半导体材料，去除表面绝缘材料；淀积势垒金属，进行烧结形成肖特基势垒结。A method for manufacturing a charge compensation Schottky semiconductor device with a trench structure, characterized in that it includes the following steps: forming a first conductive semiconductor material layer on the surface of a substrate layer, and then forming an insulating material layer on the surface; performing a photolithographic etching process to remove the surface Part of the insulating material layer, and then etch to remove part of the exposed semiconductor material to form a trench; perform second conductive impurity diffusion in the trench; form insulating material on the inner wall surface of the trench, deposit polycrystalline semiconductor material, and reverse-etch the polycrystalline semiconductor Material, remove surface insulating material; deposit barrier metal, sinter to form Schottky barrier junction.
当半导体装置接一定的反向偏压时，第一导电半导体材料与第二导电半导体材料和沟槽内的多晶半导体材料可以形成电荷补偿，提高了器件的反向击穿电压，或者提高了漂移区的杂质掺杂浓度降低器件的正向导通电阻。When the semiconductor device is connected to a certain reverse bias voltage, the first conductive semiconductor material and the second conductive semiconductor material and the polycrystalline semiconductor material in the trench can form charge compensation, which improves the reverse breakdown voltage of the device, or improves the The impurity doping concentration in the drift region reduces the forward conduction resistance of the device.
通过沟槽上部引入高浓度掺杂的多晶半导体材料或电极金属，可以改变肖特基表面电场分布，降低半导体装置接反向偏压时肖特基结表面的峰值电场强度，从而进一步提高器件的反向阻断特性。The introduction of highly doped polycrystalline semiconductor materials or electrode metals through the upper part of the trench can change the electric field distribution on the Schottky surface and reduce the peak electric field intensity on the surface of the Schottky junction when the semiconductor device is connected to reverse bias, thereby further improving the device. reverse blocking properties.
附图说明Description of drawings
图1为本发明一种沟槽结构电荷补偿肖特基半导体装置剖面示意图；1 is a schematic cross-sectional view of a trench structure charge compensation Schottky semiconductor device of the present invention;
图2为本发明一种沟槽结构电荷补偿肖特基半导体装置剖面示意图；2 is a schematic cross-sectional view of a trench structure charge compensation Schottky semiconductor device of the present invention;
图3为本发明一种沟槽结构电荷补偿肖特基半导体装置剖面示意图。3 is a schematic cross-sectional view of a charge compensation Schottky semiconductor device with a trench structure according to the present invention.
其中，1、衬底层；2、二氧化硅；3、第一导电半导体材料；4、第二导电半导体材料；5、肖特基势垒结；6、多晶第二导电半导体材料；7、高浓度杂质掺杂的多晶第二导电半导体材料；10、上表面金属层；11、下表面金属层。Among them, 1. Substrate layer; 2. Silicon dioxide; 3. First conductive semiconductor material; 4. Second conductive semiconductor material; 5. Schottky barrier junction; 6. Polycrystalline second conductive semiconductor material; 7. Polycrystalline second conductive semiconductor material doped with high-concentration impurities; 10. The upper surface metal layer; 11. The lower surface metal layer.
具体实施方式detailed description
实施例1Example 1
图1为本发明的一种沟槽结构电荷补偿肖特基半导体装置剖面图，下面结合图1详细说明本发明的半导体装置。FIG. 1 is a cross-sectional view of a charge compensation Schottky semiconductor device with a trench structure of the present invention. The semiconductor device of the present invention will be described in detail below with reference to FIG. 1 .
一种肖特基半导体装置，包括：衬底层1，为N导电类型半导体硅材料，磷原子的掺杂浓度为1E19/CM3，在衬底层1下表面，通过下表面金属层11引出电极；第一导电半导体材料3，位于衬底层1之上，为N传导类型的半导体硅材料，磷原子的掺杂浓度为1E16/CM3；第二导电半导体材料4，位于沟槽内壁附近，为P传导类型的半导体硅材料，硼原子的掺杂浓度为1E16/CM3；多晶第二导电半导体材料6，为硼掺杂的多晶半导体硅材料，位于沟槽内，硼原子的掺杂浓度为1E16/CM3；肖特基势垒结5，位于第一导电半导体材料3的表面，为半导体硅材料与势垒金属形成的硅化物；二氧化硅2，位于沟槽内壁；器件上表面附有上表面金属层10，为器件引出另一电极。A Schottky semiconductor device, comprising: a substrate layer 1, which is a semiconductor silicon material of N conductivity type, and the doping concentration of phosphorus atoms is 1E19/CM 3 , on the lower surface of the substrate layer 1, electrodes are drawn out through the lower surface metal layer 11; The first conductive semiconductor material 3, located on the substrate layer 1, is a semiconductor silicon material of N conductivity type, and the doping concentration of phosphorus atoms is 1E16/CM 3 ; the second conductive semiconductor material 4, located near the inner wall of the trench, is P The conduction type semiconductor silicon material, the doping concentration of boron atoms is 1E16/CM 3 ; the polycrystalline second conductive semiconductor material 6 is boron-doped polycrystalline semiconductor silicon material, located in the trench, the doping concentration of boron atoms is 1E16/CM 3 ; Schottky barrier junction 5, located on the surface of the first conductive semiconductor material 3, is a silicide formed of semiconductor silicon material and barrier metal; silicon dioxide 2, located on the inner wall of the trench; the upper surface of the device A metal layer 10 on the upper surface is attached to lead out another electrode for the device.
其制作工艺包括如下步骤：Its manufacturing process includes the following steps:
第一步，在衬底层1表面外延形成第一导电半导体材料层3，淀积形成氮化硅层；In the first step, a first conductive semiconductor material layer 3 is epitaxially formed on the surface of the substrate layer 1, and a silicon nitride layer is formed by deposition;
第二步，进行光刻腐蚀工艺，半导体材料表面去除部分氮化硅，然后刻蚀去除部分裸露半导体硅材料形成沟槽；The second step is to perform a photolithographic etching process, remove part of the silicon nitride on the surface of the semiconductor material, and then etch and remove part of the exposed semiconductor silicon material to form a trench;
第三步，在沟槽内进行硼杂质扩散；The third step is to diffuse boron impurities in the trench;
第四步，在沟槽内热氧化形成二氧化硅2，淀积多晶第二导电半导体材料6，反刻多晶第二导电半导体材料6，腐蚀去除氮化硅层；The fourth step is to thermally oxidize the silicon dioxide 2 in the trench, deposit the polycrystalline second conductive semiconductor material 6, etch the polycrystalline second conductive semiconductor material 6, and remove the silicon nitride layer by etching;
第五步，在半导体材料表面淀积势垒金属，进行烧结形成肖特基势垒结5，然后在表面淀积金属形成上表面金属层10；The fifth step is to deposit a barrier metal on the surface of the semiconductor material, perform sintering to form a Schottky barrier junction 5, and then deposit metal on the surface to form an upper surface metal layer 10;
第六步，进行背面金属化工艺，在背面形成下表面金属层11，如图1所示。In the sixth step, a backside metallization process is performed to form a lower surface metal layer 11 on the backside, as shown in FIG. 1 .
实施例2Example 2
图2为本发明的一种沟槽结构电荷补偿肖特基半导体装置剖面图，下面结合图2详细说明本发明的半导体装置。FIG. 2 is a cross-sectional view of a charge compensation Schottky semiconductor device with a trench structure of the present invention. The semiconductor device of the present invention will be described in detail below with reference to FIG. 2 .
一种肖特基半导体装置，包括：衬底层1，为N导电类型半导体硅材料，磷原子的掺杂浓度为1E19/CM3，在衬底层1下表面，通过下表面金属层11引出电极；第一导电半导体材料3，位于衬底层1之上，为N传导类型的半导体硅材料，磷原子的掺杂浓度为1E16/CM3；第二导电半导体材料4，位于沟槽内壁附近，为P传导类型的半导体硅材料，硼原子的掺杂浓度为1E16/CM3；多晶第二导电半导体材料6，为硼掺杂的多晶半导体硅材料，位于沟槽内，硼原子的掺杂浓度为1E16/CM3；肖特基势垒结5，位于第一导电半导体材料3的表面，为半导体硅材料与势垒金属形成的硅化物；二氧化硅2，位于沟槽内壁；器件上表面和沟槽内上部附有上表面金属层10，为器件引出另一电极。A Schottky semiconductor device, comprising: a substrate layer 1, which is a semiconductor silicon material of N conductivity type, and the doping concentration of phosphorus atoms is 1E19/CM 3 , on the lower surface of the substrate layer 1, electrodes are drawn out through the lower surface metal layer 11; The first conductive semiconductor material 3, located on the substrate layer 1, is a semiconductor silicon material of N conductivity type, and the doping concentration of phosphorus atoms is 1E16/CM 3 ; the second conductive semiconductor material 4, located near the inner wall of the trench, is P The conduction type semiconductor silicon material, the doping concentration of boron atoms is 1E16/CM 3 ; the polycrystalline second conductive semiconductor material 6 is boron-doped polycrystalline semiconductor silicon material, located in the trench, the doping concentration of boron atoms is 1E16/CM 3 ; Schottky barrier junction 5, located on the surface of the first conductive semiconductor material 3, is a silicide formed of semiconductor silicon material and barrier metal; silicon dioxide 2, located on the inner wall of the trench; the upper surface of the device The upper surface metal layer 10 is attached to the inner upper part of the groove, and another electrode is drawn out for the device.
其制作工艺包括如下步骤：Its manufacturing process includes the following steps:
第一步，在衬底层1表面外延形成第一导电半导体材料层3，淀积形成氮化硅层；In the first step, a first conductive semiconductor material layer 3 is epitaxially formed on the surface of the substrate layer 1, and a silicon nitride layer is formed by deposition;
第二步，进行光刻腐蚀工艺，半导体材料表面去除部分氮化硅，然后刻蚀去除部分裸露半导体硅材料形成沟槽；The second step is to perform a photolithographic etching process, remove part of the silicon nitride on the surface of the semiconductor material, and then etch and remove part of the exposed semiconductor silicon material to form a trench;
第三步，在沟槽内进行硼杂质扩散；The third step is to diffuse boron impurities in the trench;
第四步，在沟槽内热氧化形成二氧化硅2，淀积多晶第二导电半导体材料6，反刻多晶第二导电半导体材料6形成沟槽，腐蚀去除氮化硅层；The fourth step is to thermally oxidize the silicon dioxide 2 in the trench, deposit the polycrystalline second conductive semiconductor material 6, etch the polycrystalline second conductive semiconductor material 6 to form a trench, and remove the silicon nitride layer by etching;
第五步，在半导体材料表面淀积势垒金属，进行烧结形成肖特基势垒结5，然后在表面淀积金属形成上表面金属层10；The fifth step is to deposit a barrier metal on the surface of the semiconductor material, perform sintering to form a Schottky barrier junction 5, and then deposit metal on the surface to form an upper surface metal layer 10;
第六步，进行背面金属化工艺，在背面形成下表面金属层11，如图2所示。In the sixth step, a back metallization process is performed to form a lower surface metal layer 11 on the back, as shown in FIG. 2 .
实施例3Example 3
图3为本发明的一种沟槽结构电荷补偿肖特基半导体装置剖面图，下面结合图3详细说明本发明的半导体装置。FIG. 3 is a cross-sectional view of a charge compensation Schottky semiconductor device with a trench structure according to the present invention. The semiconductor device of the present invention will be described in detail below with reference to FIG. 3 .
一种肖特基半导体装置，包括：衬底层1，为N导电类型半导体硅材料，磷原子的掺杂浓度为1E19/CM3，在衬底层1下表面，通过下表面金属层11引出电极；第一导电半导体材料3，位于衬底层1之上，为N传导类型的半导体硅材料，磷原子的掺杂浓度为1E16/CM3；第二导电半导体材料4，位于沟槽内壁附近，为P传导类型的半导体硅材料，硼原子的掺杂浓度为1E16/CM3；多晶第二导电半导体材料6，为硼掺杂的多晶半导体硅材料，位于沟槽内下部，硼原子的掺杂浓度为1E16/CM3；高浓度杂质掺杂的多晶第二导电半导体材料7，为硼掺杂的多晶半导体硅材料，位于沟槽内上部，硼原子的掺杂浓度为1E18/CM3；肖特基势垒结5，位于第一导电半导体材料3的表面，为半导体硅材料与势垒金属形成的硅化物；二氧化硅2，位于沟槽内壁；器件上表面附有上表面金属层10，为器件引出另一电极。A Schottky semiconductor device, comprising: a substrate layer 1, which is a semiconductor silicon material of N conductivity type, and the doping concentration of phosphorus atoms is 1E19/CM 3 , on the lower surface of the substrate layer 1, electrodes are drawn out through the lower surface metal layer 11; The first conductive semiconductor material 3, located on the substrate layer 1, is a semiconductor silicon material of N conductivity type, and the doping concentration of phosphorus atoms is 1E16/CM 3 ; the second conductive semiconductor material 4, located near the inner wall of the trench, is P The conduction type semiconductor silicon material, the doping concentration of boron atoms is 1E16/CM 3 ; the polycrystalline second conductive semiconductor material 6 is a boron-doped polycrystalline semiconductor silicon material, which is located in the lower part of the trench, and the doping concentration of boron atoms is The concentration is 1E16/CM 3 ; the polycrystalline second conductive semiconductor material 7 doped with high-concentration impurities is boron-doped polycrystalline semiconductor silicon material, located in the upper part of the trench, and the doping concentration of boron atoms is 1E18/CM 3 ; Schottky barrier junction 5, located on the surface of the first conductive semiconductor material 3, is a silicide formed by semiconductor silicon material and barrier metal; silicon dioxide 2, located on the inner wall of the trench; the upper surface of the device is attached with an upper surface metal Layer 10 leads to another electrode for the device.
其制作工艺包括如下步骤：Its manufacturing process includes the following steps:
第一步，在衬底层1表面外延形成第一导电半导体材料层3，淀积形成氮化硅层；In the first step, a first conductive semiconductor material layer 3 is epitaxially formed on the surface of the substrate layer 1, and a silicon nitride layer is formed by deposition;
第二步，进行光刻腐蚀工艺，半导体材料表面去除部分氮化硅，然后刻蚀去除部分裸露半导体硅材料形成沟槽；The second step is to perform a photolithographic etching process, remove part of the silicon nitride on the surface of the semiconductor material, and then etch and remove part of the exposed semiconductor silicon material to form a trench;
第三步，在沟槽内进行硼杂质扩散；The third step is to diffuse boron impurities in the trench;
第四步，在沟槽内热氧化形成二氧化硅2，淀积多晶第二导电半导体材料6，注入硼杂质退火，反刻多晶第二导电半导体材料，腐蚀去除氮化硅层；The fourth step is to thermally oxidize the silicon dioxide 2 in the trench, deposit the polycrystalline second conductive semiconductor material 6, implant boron impurities and anneal, etch back the polycrystalline second conductive semiconductor material, and remove the silicon nitride layer by etching;
第五步，在半导体材料表面淀积势垒金属，进行烧结形成肖特基势垒结5，然后在表面淀积金属形成上表面金属层10；The fifth step is to deposit a barrier metal on the surface of the semiconductor material, perform sintering to form a Schottky barrier junction 5, and then deposit metal on the surface to form an upper surface metal layer 10;
第六步，进行背面金属化工艺，在背面形成下表面金属层11，如图3所示。In the sixth step, a back metallization process is performed to form a lower surface metal layer 11 on the back, as shown in FIG. 3 .
通过上述实例阐述了本发明，同时也可以采用其它实例实现本发明，本发明不局限于上述具体实例，因此本发明由所附权利要求范围限定。The present invention is illustrated by the above examples, and other examples can also be used to realize the present invention. The present invention is not limited to the above specific examples, so the present invention is defined by the scope of the appended claims.
Claims (6)
- A kind of 1. Trench-structure charge compensation Schottky semiconductor device, it is characterised in that：Including：Substrate layer, formed for high concentration impurities doped semiconductor materials；Drift layer, formed for the first conducting semiconductor material, on substrate layer；It is multipleGroove structure, groove are located in drift layer, and trench wall region is abutted against in drift layer and is provided with the second conductive semiconductor material Material, trench wall surface are provided with insulating materials, under-filled second conductive polycrystalline semi-conducting material in groove, groove internal upper part Fill the polycrystalline semiconductor material of high concentration impurities doping；Abut against the conducting semiconductor material of trenched side-wall second, the second conductive polycrystalline semi-conducting material under-filled in groove and drift Move the conducting semiconductor material of layer first and form charge compensation structure；Schottky barrier junction, positioned at the first conducting semiconductor material of drift layer upper surface；Upper and lower surface metal level, upper surface metal level connection schottky barrier junction, the second conducting semiconductor material upper surface and ditch Polycrystalline semiconductor material upper surface in groove, lower surface metal layer are located at the substrate layer back side.
- 2. semiconductor device as claimed in claim 1, it is characterised in that：The insulating materials on described trench wall surface is two Silica.
- 3. semiconductor device as claimed in claim 1, it is characterised in that：In described the second conducting semiconductor material and groove Filling semiconductor material is isolated by trench wall surface insulation material.
- 4. semiconductor device as claimed in claim 1, it is characterised in that：Described Schottky barrier becomes barrier metal and The barrier junction that one conducting semiconductor material is formed.
- 5. semiconductor device as claimed in claim 1, it is characterised in that：Described abuts against the conductive semiconductor of trenched side-wall second Material surface forms schottky barrier junction.
- 6. a kind of manufacture method of Trench-structure charge compensation Schottky semiconductor device as claimed in claim 1, its feature It is：Comprise the following steps：1) the first conducting semiconductor material layer is formed in substrate layer surface, is then formed in the first conducting semiconductor material layer surface Insulation material layer；2) carry out lithography corrosion process and remove surface portion insulation material layer, then etching removes partial denudation semi-conducting material shape Into groove；3) the second conductive impurity diffusion is carried out in groove；4) insulating materials is formed on trench wall surface, deposits the second conductive polycrystalline semi-conducting material, inject the second conductive impurity Annealing, erosion polycrystalline semiconductor material is anti-carved, remove surface insulation material；5) barrier metal is deposited, is sintered to form schottky barrier junction；6) metal is deposited in upper surface, forms upper surface metal level, connection schottky barrier junction, on the second conducting semiconductor material Polycrystalline semiconductor material upper surface in surface and groove, back side metallization technology is carried out, overleaf forms lower surface metal layer.
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| CN101510557A (en) * | 2008-01-11 | 2009-08-19 | 艾斯莫斯技术有限公司 | Superjunction device having a dielectric termination and methods for manufacturing the device |
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