CN103579361A - Metal-oxide semiconductor thin film transistor and manufacturing method thereof - Google Patents

Abstract

The metal oxide semiconductor thin film transistor includes a substrate, a gate, a gate insulating layer, a source electrode, a drain electrode and a metal oxide semiconductor layer. The gate insulation layer is on the base and covers the gate on the base. The source and the drain are separately located on the gate insulating layer, and respectively have a first overlapping area and a second overlapping area with the gate. The metal oxide semiconductor layer covers the source and the drain and is in contact with the source and the drain, and the metal oxide semiconductor layer and the source and the drain respectively have a third overlapping region and a fourth overlapping region, and the area of the third overlapping region The area of the fourth overlapping area is larger than the area of the first overlapping area, and the area of the fourth overlapping area is larger than the area of the second overlapping area. The metal oxide semiconductor thin film transistor can effectively solve the problem of peeling off the metal oxide semiconductor layer and the source and drain, and can also avoid damage to the metal oxide semiconductor layer during the process of forming the passivation protection layer. The invention also relates to a method for manufacturing the metal oxide semiconductor thin film transistor.

Description

Metal oxide semiconductor thin film transistor and its manufacturing method

technical field

The invention relates to the technical field of semiconductors, and in particular to a metal oxide semiconductor thin film transistor and a manufacturing method thereof.

Background technique

At present, the semiconductor channel layer material of thin film transistor (TFT) used in flat panel display is mainly silicon material, including amorphous silicon (a-Si: H), polycrystalline silicon, microcrystalline silicon, etc. However, amorphous silicon thin film transistors have the disadvantages of light sensitivity, low mobility and poor stability; although polysilicon thin film transistors have high mobility, their electrical uniformity is poor due to the influence of grain boundaries, and the preparation temperature of polysilicon is high and the cost is high. High and difficult to crystallize in a large area, which limits its application in flat panel displays; the preparation of microcrystalline silicon is difficult, the grain control technology is difficult, and it is not easy to achieve large-scale mass production.

It is currently known that certain metal oxides have semiconductor properties, such as tungsten oxide, tin oxide, indium oxide, zinc oxide, indium gallium zinc oxide (IGZO), etc., and transparent semiconductors formed using such metal oxides layer as the channel layer material to form metal oxide semiconductor thin film transistors, compared with silicon-containing thin film transistors, metal oxide semiconductor thin film transistors have the advantages of higher electron mobility, low preparation temperature, and transparency to visible light, so the more More and more attention has been paid to it, and there is a development trend of replacing thin film transistors prepared by traditional silicon technology. In particular, in recent years, due to the advantages of high electron mobility, good stability, and simple preparation process, IGZO TFT has become a hot spot in the research and development of metal oxide semiconductor thin film transistors.

The structure of IGZO TFT mainly includes three types: back channel etch type, etch stop type and coplanar type. The back channel etching type IGZO TFT process is simple, but because the IGZO layer lacks a protective layer, it is easy to damage the IGZO layer when forming the source and drain, thus affecting the performance of the IGZO TFT, so this structure is seldom used at present. The etch barrier layer on the IGZO layer of the etch barrier IGZO TFT can protect the IGZO layer from being damaged when the source and drain are formed, thereby improving the performance of the IGZO TFT. However, the production of etch barrier type IGZO TFT requires an additional photolithography process to form an etch barrier layer, which increases the complexity of the fabrication process of IGZO TFTs, and since the material of the etch barrier layer is generally SiNx or SiOx, plasma enhanced In the process of forming the etching barrier layer by plasma enhanced chemical vapor deposition (PECVD), the plasma is easy to damage the IGZO layer, thereby affecting the performance of the IGZOTFT. The coplanar IGZO TFT is the current mainstream structure. Compared with the back-channel etched IGZO TFT, the coplanar IGZO TFT can avoid the IGZO layer in the process of forming the source and drain because the IGZO layer is above the source and drain. At the same time, compared with the etching barrier IGZO TFT, there is one less photolithography process, and it is compatible with the current mainstream equipment for preparing amorphous silicon (a-Si) TFT, which can reduce equipment investment and production costs.

However, the disadvantage of the coplanar IGZO TFT is that the IGZO layer is prone to peeling (peeling) where the IGZO layer contacts the source and drain electrodes, and in the subsequent process of forming a passivation protection layer, the IGZO layer on the source and drain electrodes is Damage and destruction, thus affecting the performance of IGZO TFT. Figure 1 is a schematic diagram of the layout structure of the existing coplanar IGZO TFT. FIG. 2 is a schematic cross-sectional structure diagram of the coplanar IGZOTFT shown in FIG. 1 along line II-II. Please refer to FIG. 1 and FIG. 2 together. The gate 110 of the coplanar IGZOTFT 100 is formed on the substrate 101, the gate insulating layer 120 is formed on the substrate 101 and covers the gate 110, and the source 132 and the drain 134 are separately formed. On the gate insulating layer 120 , an IGZO layer 140 is formed on the source 132 and the drain 134 , connected between the source 132 and the drain 134 and located above the gate 110 . Since the thickness of the IGZO layer 140 is relatively thin and the area of the contact regions 105a, 150b between the IGZO layer 140 and the source electrode 132 and the drain electrode 134 is relatively small, the adhesion between the IGZO layer 140 and the source electrode 132 and the drain electrode 134 is relatively poor. In the process of forming the IGZO layer 140 through a photomask process, the IGZO layer 140 is easily peeled off from the source-drain electrodes 132 and the drain electrodes 134 when the photoresist is removed. On the other hand, since the IGZO layer 140 is formed on the source electrode 132 and the drain electrode 134, the passivation protection layer 150 will be formed on the IGZO layer 140 by plasma enhanced chemical vapor deposition, in order to facilitate the display of the metal oxide semiconductor thin film transistor 100 The structure of the passivation protection layer 150 is not drawn in FIG. 1 , but is only drawn in FIG. 2 . During the process of forming the passivation protection layer 150 , the plasma will react with the oxygen in the IGZO layer 140 , causing damage and damage to the IGZO layer 140 , thereby affecting the semiconductor performance of the IGZO layer 140 . Whether it is the peeling off of the IGZO layer 140 or the damage and destruction of the IGZO layer 140 will seriously affect the performance of the coplanar IGZO TFT 100 .

Contents of the invention

The object of the present invention is to provide a metal oxide semiconductor thin film transistor to effectively solve the problem of peeling off the metal oxide semiconductor layer from the source and drain electrodes, and to effectively avoid the oxidation of the metal during the formation of the passivation protection layer. damage to the semiconductor layer.

The present invention also provides a manufacturing method for manufacturing the metal oxide semiconductor thin film transistor.

The present invention solves the technical problem by adopting the following technical solutions.

A metal oxide semiconductor thin film transistor comprises a substrate, a gate, a gate insulating layer, a source electrode, a drain electrode and a metal oxide semiconductor layer. The gate is on the substrate. The gate insulating layer is located on the base and covers the gate. The source and the drain are separately located on the gate insulating layer, the source and the gate have a first overlapping area, and the drain and the gate have a second overlapping area. The metal oxide semiconductor layer covers the source and the drain and is in contact with the source and the drain, and the metal oxide semiconductor layer and the source have a third overlapping region, and the metal oxide semiconductor layer and the drain have a fourth overlapping region. The area of the three overlapping areas is greater than that of the first overlapping area, and the area of the fourth overlapping area is greater than that of the second overlapping area.

In a preferred embodiment of the present invention, the length direction of the source and the drain is perpendicular to the gate, and the long side extending along the length direction of the gate crosses and overlaps with the gate. The metal oxide semiconductor layer includes a first part, a second part and a third part, and the second part is connected between the first part and the third part. The first part completely covers the first overlapping region and extends beyond the long side of the gate along the length direction of the source, and the third part completely covers the second overlapping region and extends beyond the long side of the gate along the length direction of the drain .

In a preferred embodiment of the present invention, the aforementioned metal oxide semiconductor layer includes a first metal oxide semiconductor layer and a second metal oxide semiconductor layer. The first metal oxide semiconductor layer is on and in contact with the source and the drain. The second metal oxide semiconductor layer is on the first metal oxide semiconductor layer.

In a preferred embodiment of the present invention, the oxygen content of the second metal oxide semiconductor layer is greater than the oxygen content of the first metal oxide semiconductor layer.

In a preferred embodiment of the present invention, the metal oxide semiconductor thin film transistor further includes a passivation protection layer, and the passivation protection layer covers the second metal oxide semiconductor layer.

A method for manufacturing a metal oxide semiconductor thin film transistor includes the following steps. First, a gate is formed on a substrate. Then, a gate insulating layer is formed on the base to cover the gate. Afterwards, a source and a drain are formed on the gate insulating layer, the source and the drain are separated from each other, and respectively have a first overlapping region and a second overlapping region with the gate. Next, a metal oxide semiconductor layer is formed on the source electrode and the drain electrode, the metal oxide semiconductor layer is in contact with the source electrode and the drain electrode, and has a third overlapping region and a fourth overlapping region with the source electrode and the drain electrode, and the third The area of the overlapping area is larger than that of the first overlapping area, and the area of the fourth overlapping area is larger than that of the second overlapping area.

In a preferred embodiment of the present invention, the length direction of the source and the drain is perpendicular to the gate, and the long side extending along the length direction of the gate crosses and overlaps with the gate. The metal oxide semiconductor layer includes a first part, a second part and a third part, and the second part is connected between the first part and the third part. The first part completely covers the first overlapping region and extends beyond the long side of the gate along the length direction of the source, and the third part completely covers the second overlapping region and extends beyond the long side of the gate along the length direction of the drain .

In a preferred embodiment of the present invention, a metal oxide semiconductor layer is formed on the source and drain, first a first metal oxide semiconductor layer is formed on the source and drain, the first metal oxide semiconductor layer and The source and drain are electrically connected. Then, a second metal oxide semiconductor layer is formed on the first metal oxide semiconductor layer.

In a preferred embodiment of the present invention, the oxygen content of the second metal oxide semiconductor layer is greater than the oxygen content of the first metal oxide semiconductor layer.

In a preferred embodiment of the present invention, the above-mentioned manufacturing method further includes forming a passivation protection layer on the second metal oxide semiconductor layer by using a plasma-enhanced chemical vapor deposition method.

In the metal oxide semiconductor thin film transistor of the present invention, the metal oxide semiconductor is formed on the source electrode and the drain electrode, which can avoid damage and damage to the metal oxide semiconductor layer when the source electrode and the drain electrode are formed. In addition, the source and the drain have a first overlapping region and a second overlapping region with the gate respectively, the metal oxide semiconductor layer has a third overlapping region and a fourth overlapping region with the source and the drain respectively, and the third overlapping region The area of the fourth overlapping area is larger than that of the first overlapping area, and the area of the fourth overlapping area is larger than that of the second overlapping area. The third overlapping region and the fourth overlapping region of the metal oxide semiconductor layer and the source and drain have larger areas, so that the contact area between the thinner metal oxide semiconductor layer and the source and drain increases, so the metal oxide The material semiconductor layer is not easy to peel off from the source electrode and the drain electrode, thereby effectively solving the peeling problem of the metal oxide semiconductor layer, and obtaining a metal oxide semiconductor thin film transistor with good performance.

In addition, the metal oxide semiconductor layer of the metal oxide semiconductor thin film transistor of the present invention may include a first metal oxide semiconductor layer and a second metal oxide semiconductor layer, and the oxygen content of the second metal oxide semiconductor layer is greater than that of the first metal oxide semiconductor layer. Oxygen content of the oxide semiconductor layer, because the oxygen content of the second metal oxide semiconductor layer is abundant, in the process of forming a passivation protective layer on the metal oxide semiconductor layer by plasma enhanced chemical vapor deposition, the second metal oxide The semiconductor layer can prevent damage and damage caused by plasma to the first metal oxide semiconductor layer, so as to obtain a metal oxide semiconductor thin film transistor with good performance.

The above description is only an overview of the technical solution of the present invention. In order to make the above technical solution and other objectives, features and advantages of the present invention more obvious and easy to understand, the preferred embodiments are specifically cited below, together with the accompanying drawings, for a detailed description as follows.

Description of drawings

Figure 1 is a schematic diagram of the layout structure of the existing coplanar IGZO TFT.

Fig. 2 is a schematic cross-sectional structure diagram of the coplanar IGZO TFT shown in Fig. 1 along the line II-II.

FIG. 3 is a schematic diagram of the layout structure of the metal oxide semiconductor thin film transistor according to the first embodiment of the present invention.

FIG. 4 is a schematic cross-sectional structure view along line IV-IV of the metal-oxide-semiconductor thin film transistor according to the first embodiment of the present invention shown in FIG. 3 .

FIG. 5 is a schematic diagram of a layout structure of a metal-oxide-semiconductor thin film transistor according to a second embodiment of the present invention.

FIG. 6 is a schematic cross-sectional structure diagram along line VI-VI of the metal-oxide-semiconductor thin film transistor according to the second embodiment of the present invention shown in FIG. 5 .

Detailed ways

In order to further elaborate the technical means and effects that the present invention adopts for reaching the intended invention purpose, below in conjunction with the accompanying drawings and preferred embodiments, the specific implementation, structure, features and effects according to the present invention are described in detail as follows:

The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the drawings. Through the description of specific implementation methods, the technical means and effects of the present invention to achieve the intended purpose can be understood more deeply and specifically, but the attached drawings are only for reference and description, and are not used to explain the present invention limit.

FIG. 3 is a schematic diagram of the layout structure of the metal oxide semiconductor thin film transistor according to the first embodiment of the present invention. FIG. 4 is a schematic cross-sectional structure view along line IV-IV of the metal-oxide-semiconductor thin film transistor according to the first embodiment of the present invention shown in FIG. 3 . Please refer to FIG. 3 and FIG. 4 together. In this embodiment, the metal oxide semiconductor thin film transistor 200 is a coplanar structure, which mainly includes a substrate 210, a gate 220, a gate insulating layer 230, a source 242 and a drain. 244 and metal oxide semiconductor layer 250.

In this embodiment, the gate 220 is located on the substrate 210 , that is, disposed on the surface of the substrate 210 . The gate 220 is substantially strip-shaped and has opposite long sides 220 a , 220 b extending along the length direction of the gate. The gate insulating layer 230 is located on the substrate 210 , that is, disposed on the surface of the substrate 210 and covering the gate 220 . In this embodiment, the gate insulating layer 230 has a double-layer structure, including a silicon nitride layer 232 and a silicon oxide layer 234 on the silicon nitride layer 232, but it is not limited thereto. It can be understood that in other In an embodiment, the gate insulating layer 230 may also be a single-layer structure or other multi-layer structures.

The source 242 and the drain 244 are separately disposed on the gate insulating layer 230 and located above the gate 220 . The length extension direction of the source 242 and the drain 244 is approximately perpendicular to the long sides 220a, 220b extending along the length direction of the gate 220 of the gate 220, so that the source 242 and the drain 244 are perpendicular to the gate 220 respectively. Overlap settings. Therefore, in this embodiment, the gate 220 overlaps with the source 242 to form a first overlap region 201 a , and the gate 220 overlaps with the drain 244 to form a second overlap region 201 b.

The metal oxide semiconductor layer 250 is, for example, an indium gallium zinc oxide (IGZO) layer. The metal oxide semiconductor layer 250 covers the source electrode 242 , the drain electrode 244 and the gate insulating layer 230 . The metal oxide semiconductor layer 250 is connected between the source 242 and the drain 244 , is located above the gate 220 between the source 242 and the drain 244 , and directly overlaps and contacts the source 242 and the drain 244 . The metal oxide semiconductor layer 250 located between the source electrode 242 and the drain electrode 244 is in contact with the portion of the gate insulating layer 230 exposed between the source electrode 242 and the drain electrode 244 .

In this embodiment, the metal oxide semiconductor layer 250 includes a first portion 251 , a second portion 252 and a third portion 253 . The second part 252 is connected between the first part 251 and the third part 253 . The first portion 251 of the metal oxide semiconductor layer 250 is located above the source electrode 242, completely covers the first overlapping region 201a, and extends along the length direction of the source electrode 242 beyond the long side of the gate electrode 220 extending along the length direction of the gate electrode 220. 220 a and 220 b cover most of the source electrode 242 along the length direction of the source electrode 242 , thereby forming a third overlapping region 202 a between the metal oxide semiconductor layer 250 and the source electrode 242 . The third portion 253 of the metal oxide semiconductor layer 250 is located above the drain 244, completely covers the second overlapping region 201b, and extends along the length of the drain 244 beyond the long side of the gate 220 extending along the length of the gate 220. The sides 220 a and 220 b cover most of the drain 244 along the length direction of the drain 244 , thereby forming a fourth overlapping region 202 b between the metal oxide semiconductor layer 250 and the drain 244 . In addition, the second portion 252 of the metal oxide semiconductor layer 250 is the channel region 203 between the source 242 and the drain 244 above the gate 220, and is connected to the gate exposed between the source 242 and the drain 244. The insulating layer 230 contacts. In this embodiment, the area of the third overlapping region 202a is larger than that of the first overlapping region 201a, and the area of the fourth overlapping region 202b is larger than that of the second overlapping region 201b. Since the third overlapping region 202a and the fourth overlapping region 202b of the metal oxide semiconductor layer 250 and the source electrode 242 and the drain electrode 244 have larger areas, the thinner metal oxide semiconductor layer 250 and the source electrode 242 and the drain electrode 244 have a larger area. The contact area of 244 increases, and the adhesion between the metal oxide semiconductor layer 250 and the source electrode 242 and the drain electrode 244 is better. In the subsequent manufacturing process, it is not easy to cause the metal oxide semiconductor layer 250 to peel off from the source electrode 242 and the drain electrode 244. . Therefore, the metal oxide semiconductor layer 250 is not easily peeled off from the source electrode 242 and the drain electrode 244 , so that the metal oxide semiconductor thin film transistor 200 has good performance. In addition, the lateral width of the first portion 251 of the metal oxide semiconductor layer 250 is preferably larger than the lateral width of the source electrode 242, and the lateral width of the third portion 253 of the metal oxide semiconductor layer 250 is preferably larger than that of the drain electrode 244. Horizontal width.

In addition, in this embodiment, the metal oxide semiconductor thin film transistor 200 further includes a passivation protection layer 260 . In order to facilitate the display of the structure of the metal oxide semiconductor thin film transistor 200 , the passivation protection layer 260 is not drawn in FIG. 3 , but is only drawn in FIG. 4 . The passivation protection layer 260 may be, for example, a silicon nitride layer or a silicon oxide layer. The passivation protection layer 260 is located on the metal oxide semiconductor layer 250 and covers the metal oxide semiconductor layer 250 for protecting the metal oxide semiconductor layer 250 .

The manufacturing method of the metal oxide semiconductor thin film transistor 200 will be specifically described below. The gate 220 , the source 242 , the drain 244 , and the metal oxide semiconductor layer 250 can all be realized by well-known processes such as film deposition and etching patterning. The manufacturing method of the metal oxide semiconductor thin film transistor 200 includes the following steps.

First, the gate 220 is formed on the substrate 210 .

Then, a gate insulating layer 230 is formed on the substrate 210 and covers the gate 220 .

Afterwards, a source 242 and a drain 244 are formed on the gate insulating layer 230, the source 242 and the drain 244 are separated from each other, and the length direction of the source 242 and the drain 244 is approximately the same as the long sides 220a, 220b of the gate 220. vertically, so that the source 242 and the drain 244 are vertically crossed and overlapped with the gate 220 respectively. Therefore, the source 242 and the gate 220 have a first overlapping region 201a, and the drain 244 and the gate 220 have a second overlapping region 201b.

Next, a metal oxide material layer is formed on the source electrode 242 and the drain electrode 244 and patterned to form a metal oxide semiconductor layer 250 . The metal oxide semiconductor layer 250 is located above the gate 220 and connected between the source 242 and the drain 244 and in contact with the source 242 and the drain 244 . The metal oxide semiconductor layer 250 includes a first portion 251 , a second portion 252 and a third portion 253 . The second part 252 is connected between the first part 251 and the third part 253 . The first portion 251 of the metal oxide semiconductor layer 250 is located above the source 242, completely covers the first overlapping region 201a, and extends along the length direction of the source 242 beyond the long sides 220a, 220b of the gate 220 to extend along the source 242. The lengthwise direction of the MOS layer covers most of the source electrode 242 , thereby forming a third overlapping region 202 a between the metal oxide semiconductor layer 250 and the source electrode 242 . The third portion 253 of the metal oxide semiconductor layer 250 is located above the drain 244, completely covers the second overlapping region 201b, and extends along the length of the drain 244 beyond the long side of the gate 220 extending along the length of the gate 220. The sides 220 a and 220 b are along the length direction of the drain 244 and cover most of the drain 244 , thereby forming a fourth overlapping region 202 b between the metal oxide semiconductor layer 250 and the drain 244 . In addition, the second portion 252 of the metal oxide semiconductor layer 250 is the channel region 203 between the source 242 and the drain 244 above the gate 220, and is connected to the gate insulating layer exposed from the source 242 and the drain 244. 230 contacts. In this embodiment, the area of the third overlapping region 202a is larger than that of the first overlapping region 201a, and the area of the fourth overlapping region 202b is larger than that of the second overlapping region 201b. Since the third overlapping region 202a and the fourth overlapping region 202b of the metal oxide semiconductor layer 250 and the source electrode 242 and the drain electrode 244 have larger areas, the thinner metal oxide semiconductor layer 250 and the source electrode 242 and the drain electrode 244 have a larger area. The contact area of 244 is increased, so the metal oxide semiconductor layer 250 is not easily peeled off from the source electrode 242 and the drain electrode 244 , so that the metal oxide semiconductor thin film transistor 200 has good performance. In addition, the lateral width of the first portion 251 of the metal oxide semiconductor layer 250 is preferably larger than the lateral width of the source electrode 242, and the lateral width of the third portion 253 of the metal oxide semiconductor layer 250 is preferably larger than that of the drain electrode 244. Horizontal width.

In addition, the manufacturing method of the metal oxide semiconductor thin film transistor 200 further includes forming a passivation protection layer 260 on the metal oxide semiconductor layer 250 by using a plasma enhanced chemical vapor deposition method.

FIG. 5 is a schematic diagram of a layout structure of a metal-oxide-semiconductor thin film transistor according to a second embodiment of the present invention. FIG. 6 is a schematic cross-sectional structure diagram along line VI-VI of the metal-oxide-semiconductor thin film transistor according to the second embodiment of the present invention shown in FIG. 5 . Please refer to FIG. 5 and FIG. 6 together. In this embodiment, the metal oxide semiconductor thin film transistor 300 also has a coplanar structure, which is roughly the same as the metal oxide semiconductor thin film transistor 200. The difference between the two is that the metal oxide semiconductor thin film The metal oxide semiconductor layer 350 of the semiconductor thin film transistor 300 has a two-layer structure, that is, the metal oxide semiconductor layer 350 includes a first metal oxide semiconductor layer 352 and a second metal oxide semiconductor layer 354 . Except for the metal oxide semiconductor layer 350 , other structures of the metal oxide semiconductor thin film transistor 300 are the same as the corresponding structures of the metal oxide semiconductor thin film transistor 200 and use the same reference numerals, and will not be repeated here.

In this embodiment, both the first metal oxide semiconductor layer 352 and the second oxide semiconductor layer 354 are, for example, indium gallium zinc oxide (IGZO) layers, but the oxygen content of the second metal oxide semiconductor layer 354 is greater than that of the first metal oxide semiconductor layer. The oxygen content of the oxide semiconductor layer 352. The oxygen content refers to the number of moles of oxygen atoms per mole of IGZO in the metal oxide semiconductor layer 350 . For example, the second metal oxide semiconductor layer 354 is defined as the number of moles of oxygen atoms per mole of IGZO in IGZOx is x, and the first metal oxide semiconductor layer 352 is defined as the number of moles of oxygen atoms per mole of IGZO in IGZOy is y, Among them, 0<y<x. In this way, when the passivation protection layer 260 covering the metal oxide semiconductor layer 350 is formed by plasma enhanced chemical vapor deposition, since the oxygen content of the second metal oxide semiconductor layer 354 is greater than that of the first metal oxide semiconductor layer The oxygen content of the layer 352, or because the oxygen content of the second metal oxide semiconductor layer 354 is surplus, the surplus oxygen in the second metal oxide semiconductor layer 354 can be used to react with the plasma, and at the same time prevent the plasma from affecting the first metal Damage and destruction of the oxide semiconductor layer 352 .

The manufacturing method of the metal oxide semiconductor thin film transistor 300 will be specifically described below. The gate 220 , the source 242 , the drain 244 , and the metal oxide semiconductor layer 350 can all be realized by well-known processes such as film deposition and etching patterning. The manufacturing method of the metal oxide semiconductor thin film transistor 300 includes the following steps.

First, the gate 220 is formed on the substrate 210 .

Then, a gate insulating layer 230 is formed on the substrate 210 and covers the gate 220 .

Afterwards, a source 242 and a drain 244 are formed on the gate insulating layer 230, the source 242 and the drain 244 are separated from each other, and the length direction of the source 242 and the drain 244 is approximately the same as the long sides 220a, 220b of the gate 220. vertically, so that the source 242 and the drain 244 are vertically crossed and overlapped with the gate 220 respectively. Therefore, the source 242 and the gate 220 have a first overlapping region 201a, and the drain 244 and the gate 220 have a second overlapping region 201b.

Next, a first metal oxide material layer and a second metal oxide material layer are sequentially formed on the source electrode 242 and the drain electrode 244 and patterned to form a metal oxide semiconductor layer 350 . The metal oxide semiconductor layer 350 is located above the gate 220 and electrically connected between the source 242 and the drain 244 . The formed metal oxide semiconductor layer 350 includes a first metal oxide semiconductor layer 352 and a second metal oxide semiconductor layer 354 on the first metal oxide semiconductor layer 352 . The oxygen content of the second metal oxide semiconductor layer 354 is greater than that of the first metal oxide semiconductor layer 352 . Likewise, the patterned metal oxide semiconductor layer 350 includes a first portion 350a, a second portion 350b and a third portion 350c. The second portion 350b is connected between the first portion 350a and the third portion 350c. The first portion 350a of the metal oxide semiconductor layer 350 is located above the source electrode 242, completely covers the first overlapping region 201a, and extends along the length direction of the source electrode 242 beyond the long side of the gate electrode 220 extending along the length direction of the gate electrode 220. 220a, 220b, so as to cover most of the source electrode 242 along the length direction of the source electrode 242, thereby forming the third overlapping region 302a. The third portion 350c of the metal oxide semiconductor layer 350 is located above the drain 244, completely covers the second overlapping region 201b, and extends along the length of the drain 244 beyond the long side of the gate 220 extending along the length of the gate 220. The sides 220a, 220b cover most of the drain 242 along the length direction of the drain 244, thereby forming a fourth overlapping region 302b. In addition, the second portion 350b of the metal oxide semiconductor layer 350 is the channel region 203 between the source 242 and the drain 244 above the gate 220, and is connected to the gate insulating layer exposed from the source 242 and the drain 244. 230 contacts. In this embodiment, the area of the third overlapping region 302a is larger than that of the first overlapping region 201a, and the area of the fourth overlapping region 302b is larger than that of the second overlapping region 201b. Since the third overlapping region 302a and the fourth overlapping region 302b of the metal oxide semiconductor layer 350 and the source electrode 242 and the drain electrode 244 have larger areas, the thinner metal oxide semiconductor layer 350 and the source electrode 242 and the drain electrode 244 have a larger area. The contact area of 244 is increased, so the metal oxide semiconductor layer 350 is not easily peeled off from the source electrode 242 and the drain electrode 244 , so that the metal oxide semiconductor thin film transistor 300 has good performance. In addition, the lateral width of the first portion 350a of the metal oxide semiconductor layer 350 is preferably larger than the lateral width of the source electrode 242, and the lateral width of the third portion 350c of the metal oxide semiconductor layer 350 is preferably larger than the lateral width of the drain electrode 244. width.

In addition, the manufacturing method of the metal oxide semiconductor thin film transistor 300 further includes forming a passivation protection layer 260 on the metal oxide semiconductor layer 250 by using a plasma enhanced chemical vapor deposition method. Since the oxygen content of the second metal oxide semiconductor layer 354 is greater than the oxygen content of the first metal oxide semiconductor layer 352, or because the oxygen content of the second metal oxide semiconductor layer 354 is abundant, the plasma-enhanced chemical vapor deposition method In the process of forming the passivation protection layer 260 on the metal oxide semiconductor layer 350, the surplus oxygen in the second metal oxide semiconductor layer 354 can be used to react with the plasma while preventing the plasma from affecting the first metal oxide semiconductor layer. 352 damage and destruction. After the passivation protection layer 260 is formed, the remaining oxygen in the second metal oxide semiconductor layer 354 can still maintain the semiconductor performance of the second metal oxide semiconductor layer 354, and further, through subsequent processes, the second metal oxide semiconductor Oxygen in the semiconductor layer 354 and the first metal oxide semiconductor layer 352 is balanced, so that the metal oxide semiconductor layer 350 maintains good semiconductor performance. Therefore, the second metal-oxide-semiconductor layer 354 can prevent plasma damage and damage to the metal-oxide-semiconductor layer 350 , so that the metal-oxide-semiconductor thin film transistor 200 has good performance.

The above description is only an embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with the embodiment, it is not intended to limit the present invention. Without departing from the scope of the technical solution of the present invention, when the technical content disclosed above can be used to make some changes or be modified into equivalent embodiments with equivalent changes, but if it does not deviate from the technical solution of the present invention, the technical essence of the present invention can be used for the above Any simple modifications, equivalent changes and modifications made in the embodiments still fall within the scope of the technical solution of the present invention.

Claims (10)

1. A metal oxide semiconductor thin film transistor, characterized in that it comprises: base; a grid on the substrate; a gate insulating layer located on the substrate and covering the gate; a source and a drain are separated on the gate insulating layer, the source and the gate have a first overlapping region, and the drain and the gate have a second overlapping region; and a metal oxide semiconductor layer covering and in contact with the source and the drain, and the metal oxide semiconductor layer and the source have a third overlapping region, the metal oxide semiconductor layer and the The drain has a fourth overlapping area, the area of the third overlapping area is larger than that of the first overlapping area, and the area of the fourth overlapping area is larger than that of the second overlapping area. 2. The metal-oxide-semiconductor thin film transistor according to claim 1, wherein the source and the drain are perpendicular to the long side of the gate extending along the length direction of the gate and overlap with the gate, The metal oxide semiconductor layer includes a first part, a second part and a third part, the second part is connected between the first part and the third part, the first part completely covers the first overlapping region and extends along the source The length direction of the drain electrode extends beyond the long side of the gate, and the third portion completely covers the second overlapping region and extends along the length direction of the drain beyond the long side of the gate. 3. The metal oxide semiconductor thin film transistor according to claim 1, wherein the metal oxide semiconductor layer comprises: a first metal oxide semiconductor layer on and in contact with the source and the drain; and The second metal oxide semiconductor layer is located on the first metal oxide semiconductor layer. 4. The metal oxide semiconductor thin film transistor according to claim 3, wherein the oxygen content of the second metal oxide semiconductor layer is greater than the oxygen content of the first metal oxide semiconductor layer. 5. The metal oxide semiconductor thin film transistor according to claim 4, characterized in that the metal oxide semiconductor thin film transistor further comprises a passivation protection layer covering the second metal oxide semiconductor layer. 6. A method for manufacturing a metal oxide semiconductor thin film transistor, characterized in that it comprises: forming a gate on the substrate; forming a gate insulating layer on the substrate and covering the gate; A source and a drain are formed on the gate insulating layer, the source and the drain are separated from each other, the source and the gate have a first overlapping region, and the drain and the gate have a second overlapping region ;as well as A metal oxide semiconductor layer is formed on the source and the drain, the metal oxide semiconductor layer is in contact with the source and the drain, has a third overlapping region with the source, and has a fourth overlap with the drain. In the overlapping area, the area of the third overlapping area is larger than that of the first overlapping area, and the area of the fourth overlapping area is larger than that of the second overlapping area. 7. The manufacturing method according to claim 6, wherein the source and the drain are perpendicular to the long side of the gate extending along the gate length direction and overlap with the gate to form the gate On the insulating layer, the formed metal oxide semiconductor layer includes a first part, a second part and a third part connected between the first part and the second part, the first part completely covers the first overlapping region and along The length direction of the source extends beyond the long side of the gate, the third portion completely covers the second overlapping region and extends along the length of the drain beyond the long side of the gate. 8. The manufacturing method according to claim 6, wherein forming the metal oxide semiconductor layer on the source and the drain comprises: forming the first metal oxide semiconductor layer on the source and the drain, the first metal oxide semiconductor layer being electrically connected to the source and the drain; and A second metal oxide semiconductor layer is formed on the first metal oxide semiconductor layer. 9. The manufacturing method according to claim 8, wherein the oxygen content of the second metal oxide semiconductor layer is greater than that of the first metal oxide semiconductor layer. 10 . The manufacturing method according to claim 9 , further comprising forming a passivation protection layer on the second metal oxide semiconductor layer by using a plasma-enhanced chemical vapor deposition method. 11 .

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