CN103579337A - Semiconductor device and method for forming the same - Google Patents

Abstract

The invention discloses a semiconductor element and a forming method thereof. The semiconductor structure is formed on the substrate and comprises a first type metal oxide semiconductor field effect transistor and a second type metal oxide semiconductor field effect transistor. The first type metal oxide semiconductor field effect transistor is provided with a first grid structure, a first source region and a first drain region which are formed on the substrate. The second first type metal oxide semiconductor field effect transistor is provided with a second grid structure, a second source region and a second drain region which are formed on the substrate. The first pocket implantation is performed on the first type MOSFET with a first mask, the second pocket implantation is performed on the second first type MOSFET with a second mask, and the direction of the second gate structure is different from that of the first gate structure. The invention can alleviate the problem of non-matching of elements.

Description

Semiconductor element and method of forming the same

technical field

The present invention relates to a semiconductor element and its forming method; in particular, the present invention relates to a semiconductor element related to pocket implant or halo implant technology and its forming method.

Background technique

With the evolution of semiconductor process technology, semiconductor devices have been gradually developed towards the direction of small size and high density. When the size of the semiconductor element becomes smaller, it will face the problem of short channel effect (short channel effect).

Pocket implant or halo implant technology is a common method to improve the short channel effect. FIG. 1A depicts a top view of a known semiconductor device 1 , and FIG. 1B depicts a schematic cross-sectional view of the known semiconductor device 1 at the reference dotted line 14 . The semiconductor device 1 includes a substrate 10 , a gate structure 11 , a source region 12 and a drain region 13 , and the gate structure 11 includes a dielectric layer 11 a and a gate electrode 11 b. The well-known pocket-type implantation technology performs pocket-type implantation on the semiconductor element 1 from four directions 10a, 10b, 10c, and 10d. First, set the ion implantation conditions and fix the angle of ion implantation, and then use the same mask to start from one of the four directions 10a, 10b, 10c, and 10d (for example: direction 10a) For pocket-type implantation, the base plate 10 is rotated 90 degrees horizontally, and then pocket-type implantation is performed in the next direction (for example: direction 10c), and so on, until all four directions are implanted. In this way, pocket implantation is performed on the gate electrode 11b of the semiconductor element 1 in the directions 10c and 10d, and pockets are implanted in the gate electrode (not shown) of another semiconductor element perpendicular to the gate electrode 11b in the directions 10a and 10b. type implantation.

It can be seen from FIG. 1B that after the pocket implantation in the directions 10c and 10d is performed on the semiconductor device 1, the pocket implantation regions 15 and 16 are formed on the inner edges of the source region 12 and the drain region 13 respectively. The pocket implant regions 15 and 16 can respectively reduce the lateral electric field between the source region 12 and the substrate 10 and the lateral electric field between the drain region 13 and the substrate 10 , thereby improving the short channel effect.

However, when the semiconductor process technology enters the nano-scale era (that is, the era below 100 nanometers), the problem of device mismatch derived from pocket-type implantation of semiconductor elements becomes more and more serious. Usually, by adjusting ion implant concentration (ion implant dose), ion implant energy (ion implant energy), thermal process (thermal process) or using common implant (co-implant), etc., the short channel effect and balance between component mismatches. However, as the technology continues to shrink (eg below 40 nanometers), the above-mentioned methods can achieve limited effects.

In view of this, how to strike a balance between the short-channel effect and device mismatch under the continuous shrinkage of the technology (such as below 40 nanometers) is still an urgent problem to be solved in this field.

The disadvantage of the prior art is that pocket implantation is performed on the gate electrode 11b of the semiconductor element 1 to form the pocket implantation regions 15, 16, wherein the pocket implantation in the directions 10c, 10d will affect the direction 10c, 10d. The gate electrode of another semiconductor element causes non-matching or other adverse effects on its element; similarly, pocket-type implants in directions 10a and 10b will also negatively affect the element characteristics of the gate electrode 11b (semiconductor element 1) Impact.

Contents of the invention

Aiming at the problems existing in the prior art, the present invention proposes to use a mask to perform pocket-type implantation on a gate electrode parallel to a gate electrode of a semiconductor element (such as a first-type metal-oxide-semiconductor field-effect transistor) ( Such as directions 10c, 10d); however, this will only allow the gate electrodes to be placed in a parallel direction, which is not conducive to the layout area and the utilization rate of the wafer. Therefore, the present invention proposes to use another mask to perform pocket-type implantation (such as directions 10a, 10b) on the gate electrode of the semiconductor element in a direction different from (such as perpendicular to) the gate electrode, so as to further solve the problem of the known technology. with the above problem.

Therefore, the present invention provides a method of forming a semiconductor device and a semiconductor device.

The semiconductor element provided by the present invention is formed on a substrate and includes a first first-type MOSFET and a second first-type MOSFET. The first first-type MOSFET has a first gate structure, a first source region, and a first drain region formed on the substrate. The second first type MOSFET has a second gate structure, a second source region, and a second drain region formed on the substrate. A first pocket implant is performed on the first first type metal oxide semiconductor field effect transistor with a first mask, and a second pocket implant is performed on the second first type metal oxide semiconductor field effect transistor with a second mask. The pockets are implanted, and the direction of the second gate structure is different from that of the first gate structure.

The method for forming a semiconductor element on a substrate provided by the present invention includes the following steps: forming a first first-type metal-oxide-semiconductor field-effect transistor, the first first-type metal-oxide-semiconductor field-effect transistor having a A first gate structure, a first source region and a first drain region on the substrate; form a second first type metal oxide semiconductor field effect transistor, the second first type metal oxide semiconductor The field effect transistor has a second gate structure, a second source region and a second drain region formed on the substrate; performing a first pocket implantation on the transistor; and performing a second pocket implantation on the second MOS field effect transistor with a second mask. Wherein, the direction of the second gate structure is different from that of the first gate structure.

The beneficial effect of the present invention is that the method for forming a semiconductor element provided by the present invention can form two gate structures with different directions on the substrate, which are respectively placed on both sides of each gate structure through two different masks. Pocket implantation is applied to form pocket implantation regions at the edges of the source region and the drain region. Since the pocket implant procedure is only applied to two sides of the gate structure, the problem of device mismatch can be alleviated. In addition, since the directions of the gate structures do not need to be the same, the overall layout area can be reduced and the utilization rate of the wafer can be improved.

Description of drawings

FIG. 1A depicts a top view of a known semiconductor device;

FIG. 1B depicts a schematic cross-sectional view of a known semiconductor device at reference dotted line 14;

FIG. 2A depicts a top view of the semiconductor element of the first embodiment;

FIG. 2B depicts a schematic cross-sectional view of the semiconductor device of the first embodiment at the reference dotted line 214;

FIG. 2C depicts a schematic cross-sectional view of the semiconductor device of the first embodiment at the reference dotted line 224;

Figure 3 depicts an exemplary wafer 3 of a second embodiment of the invention; and

4A, 4B and 4C depict a flowchart of a third embodiment of the present invention.

Wherein, the reference signs are explained as follows:

1 semiconductor components

10a direction

10b direction

10c direction

10d direction

11 Gate structure

11a Dielectric layer

11b Gate electrode

12 source region

13 Drain region

14 reference dotted line

15 Pocket planting area

16 Pocket planting area

2 semiconductor components

210 Substrate

210a Direction

210b direction

211a first dielectric layer

211b first grid electrode

212 The first source region

213 The first drain region

214 reference dotted line

215 First pocket planting area

216 First pocket planting area

217a First side wall

217b First side wall

218 reference dotted line

219a The first light planting area

219b The first light planting area

220a Direction

220b direction

221a second dielectric layer

221b second grid electrode

222 second source region

223 The second drain region

224 reference dotted line

225 Second Pocket Implantation Area

226 second pocket implantation area

227a second side wall

227b second side wall

229a The second light planting area

229b The second light planting area

3 wafers

30 Substrate

31 The first N-type gate structure

32 The second N-type gate structure

33 The first P-type gate structure

34 The second P-type gate structure

36a area

36b area

36c area

36d area

Detailed ways

The semiconductor element provided by the present invention and its forming method will be explained through the following examples. However, the embodiments of the present invention are not intended to limit the present invention to be implemented in any environment, application or manner as described in the embodiments. Therefore, the descriptions about the embodiments are only for the purpose of illustrating the present invention, rather than directly limiting the present invention. It should be noted that in the following embodiments and drawings, components and procedures not directly related to the present invention may be omitted and not shown.

The first embodiment of the present invention is a semiconductor device 2 , please refer to FIG. 2A , FIG. 2B and FIG. 2C . FIG. 2A depicts a top view of the semiconductor device 2 , FIG. 2B depicts a schematic cross-sectional view of the semiconductor device 2 at the reference dotted line 214 , and FIG. 2C depicts a schematic cross-sectional view of the semiconductor device 2 at the reference dotted line 224 .

The semiconductor element 2 includes a substrate 210, a first gate structure, first sidewalls 217a, 217b, a first source region 212, a first drain region 213, a first light implant region 219a, 219b, a first pocket cloth Planting regions 215, 216, second gate structure, second sidewalls 227a, 227b, second source region 222, second drain region 223, second light implantation regions 229a, 229b and second pocket implantation Districts 225, 226. Wherein, the first gate structure, the first source region 212, and the first drain region 213 form the body of a first first-type metal-oxide-semiconductor field effect transistor, and the second gate structure, the second source The region 222 and the second drain region 223 form the body of a second MOSFET.

The first gate structure and the second gate structure are respectively formed on the first region and the second region on the substrate 210 . In FIG. 2A , above the reference dotted line 218 is the first area, and below the reference dotted line 218 is the second area. The first gate structure includes a first dielectric layer 211a and a first gate electrode 211b, and the second gate structure includes a second dielectric layer 221a and a second gate electrode 221b. It should be noted that the directions of the first gate structure and the second gate structure are different (that is, on the substrate 210, the arrangement direction of the first gate electrode 211b is different from the arrangement direction of the second gate electrode 221b) . In a preferred embodiment, the arrangement direction of the first gate structure on the substrate 210 is 90 degrees to the arrangement direction of the second gate structure on the substrate 210, as shown in the first gate electrode 211b of FIG. 2A and the second gate electrode 221b.

Next, a first masking is performed on the first first-type metal-oxide-semiconductor field effect transistor with a first mask. Specifically, a first mask (not shown) is used to cover the second area (ie, below the reference dotted line 218 ) and other non-related areas. Afterwards, the first embodiment successively adopts a light-doped drain (LDD) program and a pocket implant or halo implant program, and performs light-doped drain and pocket implant from two directions 210a and 210b . Through this light implantation process, it is convenient to form the first light implant regions 219a and 219b on both sides of the substrate 210 under the first gate structure respectively. Furthermore, through the pocket implantation process, it is convenient to form the first pocket implantation areas 215 , 216 on the inner edges of the first light implantation areas 219 a , 219 b in the substrate 210 .

In detail, in the pocket implant procedure described in the previous paragraph, the pocket implant can be performed from the direction 210a, and then the substrate 210 is rotated horizontally by 180 degrees, and then the pocket implant can be performed from the direction 210b. The first pocket implant areas 215 and 216 are formed. It should be noted that in other implementations, the pocket-shaped implantation can be performed from the direction 210b first, and then the pocket-shaped implantation can be performed from the direction 210a.

Next, a second masking process is performed on the second first-type MOSFET by using the second mask. Specifically, a second mask (not shown) is used to cover the first region (ie, above the reference dotted line 218 ) and other non-related regions. Afterwards, the light implantation program and the pocket implantation program are adopted to perform light implantation and pocket implantation from two directions 220a and 220b. Through this light implantation procedure, it is convenient to form the second light implant regions 229 a and 229 b on both sides of the substrate 210 below the second gate structure. Moreover, through the pocket implanting process, it is convenient to form the second pocket implanting areas 225 , 226 on the inner edges of the second light implanting areas 229 a , 229 b in the substrate 210 .

In detail, in the pocket implant procedure described in the previous paragraph, the pocket implant can be performed from the direction 220a, and then the substrate 210 is rotated horizontally by 180 degrees, and then the pocket implant can be performed from the direction 220b. The second pocket implant regions 225 and 226 are formed. It should be noted that in other implementations, the pocket-type implantation can be performed from the direction 220b first, and then the pocket-type implantation can be performed from the direction 220a.

Next, first spacers 217 a and 217 b are respectively formed on both sides of the first gate structure on the substrate 210 , and second spacers 217 a and 217 b are respectively formed on both sides of the second gate structure on the substrate 210 . 227a, 227b. Afterwards, the first source region 212 and the first drain region 213 are respectively formed in the substrate 210 outside the first light implantation regions 219a and 219b through the source region and drain implantation procedures. Similarly, the second source region 222 and the second drain region 223 are respectively formed in the substrate 210 outside the first lightly implanted regions 229a and 229b through the implantation process of the source region and the drain region.

In one embodiment, the angle applied to the pocket implant using the first mask is substantially ninety degrees from the angle applied to the second pocket implant using the second mask. In addition, in one embodiment, the first gate structure and the second gate structure are doped with the same type of ions. Specifically, if the first gate structure, the first source region 212, the first drain region 213, the first lightly implanted regions 219a, 219b, the second gate structure, the second source region 222, the second The drain region 223 and the second lightly implanted regions 229a, 229b are formed by doping the first type ions, and the first pocket implanted regions 215, 216 and the second pocket implanted regions 225, 226 are doped by the second type ions. miscellaneous. Wherein, the first-type ions can be any one of P-type ions or N-type ions, and the second-type ions are the other one of P-type ions or N-type ions.

It can be seen from the above description that two gate structures (ie, the first gate structure and the second gate structure) with different directions are formed on the semiconductor element 2 of the first embodiment. Since the arrangement directions of the first gate structure and the second gate structure are different, the overall layout area can be reduced. In addition, the pocket implantation process is applied to both sides of the first gate structure and the second gate structure (or the first trench formed by the first gate structure and the first source region 212 and the first drain region 213 Both ends of the channel, and both ends of the second channel formed by the second gate structure, the second source region 222 and the second drain region 223 ), so the non-matching problem of the semiconductor element 2 can be reduced.

A second embodiment of the present invention is an exemplary wafer 3 , the top view of which is depicted in FIG. 3 . First, a plurality of first N-type gate structures 31, a plurality of second N-type gate structures 32, a plurality of first P-type gate structures 33 and A plurality of second P-type gate structures 34 . The direction of the N-type gate structure 31 and the N-type gate structure 32 is 90 degrees, and the direction of the P-type gate structure 33 and the P-type gate structure 34 is 90 degrees.

Next, a mask is used to cover the regions 36b, 36c, and 36d, and light implantation regions (not shown) of N-type ions are respectively formed on both sides of the substrate 30 below the first N-type gate structure 31 by a light implantation procedure. shown), and pocket implantation regions (not shown) for P-type ions are respectively formed on the inner edge of the aforementioned light implantation region by the pocket implantation procedure.

Similarly, cover regions 36a, 36c, 36d and other non-related regions with a mask, and then form N-type ions on both sides of the substrate 30 below the second N-type gate structure 32 by a light implantation procedure. The light implantation region (not shown), and pocket implantation regions (not shown) of P-type ions are respectively formed on the inner edge of the aforementioned light implantation region by the pocket implantation procedure.

Afterwards, a mask is used to cover the regions 36a, 36b, 36d and other non-related regions, and light implantation of P-type ions is respectively formed on both sides of the substrate 30 under the first P-type gate structure 33 by light implantation procedures. Implantation regions (not shown), and pocket implantation regions (not shown) for N-type ions are respectively formed on the inner edge of the light implantation region by the pocket implantation procedure.

Similarly, the regions 36b, 36c, and 36d are covered with a mask, and lightly implanted regions ( not shown), and pocket implantation regions (not shown) for N-type ions are respectively formed on the inner edge of the aforementioned light implantation region by the pocket implantation procedure.

Then, on the substrate 30, on both sides of each first N-type gate structure 31, on both sides of each second N-type gate structure 32, on both sides of each first P-type gate structure 33, and on each second P-type gate structure. Sidewalls are respectively formed on both sides of the type gate structure. Afterwards, a mask is used to cover the regions 36c, 36d to form a source region and a drain region outside the lightly implanted regions of the first N-type gate structure 31 and the second N-type gate structure 32 in the substrate 30 . Similarly, a mask is used to cover the regions 36a, 36b to form source regions and drains outside the lightly implanted regions of the first P-type gate structure 33 and the second P-type gate structure 34 in the substrate 30 district.

Through the above procedures, N-Type Metal-Oxide-Semiconductor Field-Effect Transistors (N-Type Metal-Oxide-Semiconductor Field-Effect Transistor, NMOS) in different directions and P transistors in different directions are formed on the exemplary wafer 3 of the second embodiment. Type Metal-Oxide-Semiconductor Field-Effect Transistor (P-Type Metal-Oxide-Semiconductor Field-Effect Transistor, PMOS), so the overall layout area can be reduced and the space of the wafer 3 can be effectively used. If a wafer or a small-area layout area can only place gate structures in one direction, the utilization rate of the wafer or area will be limited. If gate structures in different directions can be placed with different masks below 40 nm The pole structure will greatly improve the utilization rate of wafer or area.

A third embodiment of the present invention is a method for forming a semiconductor device, the flow chart of which is depicted in FIG. 4A , FIG. 4B and FIG. 4C .

Firstly, the method executes step S401, forming a first gate structure and a second gate structure on a first region and a second region on the substrate respectively. It should be noted that the direction of the first gate structure is different from that of the second gate structure. In a preferred situation, the direction of the first gate structure and the direction of the second gate structure are 90 degrees.

Next, step S403 is executed to cover the second area and other non-related areas with the first mask. In step S405 , a first light implantation region is formed on both sides of the substrate below the first gate structure by light implantation procedure. Afterwards, in step S407 , first pocket implantation regions are formed on the inner edges of the first light implantation regions by the pocket implantation procedure.

Furthermore, step S407 can be achieved by steps S407a, S407b and S407c. In step S407a, the method forms a first pocket implantation region on the inner edge of one of the first light implantation regions by a pocket implantation procedure. Next, in step S407b, the substrate is rotated horizontally by 180 degrees. Subsequently, in step S407c, the method forms another first pocket implantation region on the inner edge of another one of the first light implantation regions by a pocket implantation procedure.

Afterwards, step S409 is executed to cover the first area and other non-related areas with the second mask. After the second mask is formed, the method executes step S411 to respectively form a second light implantation region on both sides of the substrate below the second gate structure by light implantation process. Next, step S413 is executed again to form a second pocket implantation area on the inner edge of each second light implantation area through the pocket implantation procedure. In a preferred embodiment, the angle applied by the pocket implanting procedure in step S413 and the angle applied by the pocket implanting in step S407 are substantially 90 degrees.

Furthermore, step S413 can be achieved by steps S413a, S413b and S413c. In step S413a, the method forms a second pocket implantation region on the inner edge of one of the second light implantation regions by a pocket implantation procedure. Next, in step S413b, the substrate is rotated horizontally by 180 degrees. Subsequently, in step S413c, the method forms another second pocket implantation region on the inner edge of the other one of the second light implantation regions by a pocket implantation procedure.

Afterwards, in step S415 , first sidewalls are respectively formed on both sides of the first gate structure on the substrate, and second sidewalls are respectively formed on both sides of the second gate structure on the substrate. Next, in step S417, a first source region and a first drain region are formed outside the first light implantation region in the substrate by a source region and drain implantation procedure, and A second source region and a second drain region are formed in the substrate outside the second lightly implanted region.

It should be noted that the first gate structure, the first source region and the first drain region form the main body of a first first type metal oxide semiconductor field effect transistor, and the second gate structure, the second source The region and the second drain region form the body of a second MOSFET. The aforementioned step S407 can be regarded as performing the first pocket implantation on the first first-type MOSFET by using the first mask. In addition, the first pocket implant is applied to both ends of the first channel formed by the first gate structure and the first source region and the first drain region. Similarly, the aforementioned step S413 can be regarded as performing the second pocket implantation on the second Type 1 MOSFET by using the second mask. In addition, the second pocket implant is applied to both ends of the second channel formed by the second gate structure and the second source region and the second drain region.

In addition, in one embodiment, the first gate structure and the second gate structure are doped with the same type of ions. Specifically, if the first gate structure, the first lightly implanted region, the first source region, the first drain region, the second gate structure, the second lightly implanted region, the second source region and the first The second drain region is doped by the first-type ions, and the first pocket implantation region and the second pocket implantation region are doped by the second-type ions. Wherein, the first-type ions can be any one of P-type ions or N-type ions, and the second-type ions are the other one of P-type ions or N-type ions.

Through the method for forming a semiconductor element provided by the present invention, two gate structures with different directions can be formed on the substrate, and then pocket-type implants are respectively applied to both sides of each gate structure through two masks, so that A pocket implant region is formed under the source region and the drain region. Since the pocket-type implantation procedure is only applied to both sides of the gate structure (or both ends of the channel), the problem of device mismatch can be alleviated. In addition, since the directions of the gate structures do not need to be the same, the overall layout area can be reduced and the utilization rate of the wafer can be improved.

Since the semiconductor process may exceed hundreds of procedures, the above-mentioned embodiments are only used to illustrate the implementation of the present invention and explain the technical features of the present invention, and are not intended to limit the scope of protection of the present invention. Any changes or equivalent arrangements that can be easily accomplished by those skilled in the art belong to the scope of the present invention, and the protection scope of the present invention should be determined by the claims.

Claims (10)

1. a semiconductor element, is formed on a substrate, comprises:

One the one the first type metal oxide semiconductor field-effect transistor, has the first grid structure, one first source area and one first drain region that are formed on this substrate; And

One the two the first type metal oxide semiconductor field-effect transistor, has the second grid structure, one second source area and one second drain region that are formed on this substrate;

Wherein, the the one the first type metal oxide semiconductor field-effect transistors carry out a first bagging with one first mask and plant, the the two the first type metal oxide semiconductor field-effect transistors carry out one second sack cloth with one second mask plants, and the direction of this second grid structure is different from the direction of this first grid structure.

2. semiconductor element as claimed in claim 1, wherein the direction of the direction of this first grid structure and this second grid structure is in fact 90 degree.

3. semiconductor element as claimed in claim 1, wherein this first bagging is planted and is put on formed the first raceway groove two ends of this first grid structure and this first source area and this first drain region.

4. semiconductor element as claimed in claim 3, wherein this second sack cloth is planted and is put on formed the second raceway groove two ends of this second grid structure and this second source area and this second drain region

5. semiconductor element as claimed in claim 4, this first bagging wherein carrying out with this first mask is planted the angle being applied and is planted with this second sack cloth carrying out with this second mask the angle applying and be in fact 90 degree.

6. on a substrate, form a method for semiconductor element, comprise the following step:

On this substrate, form one the one the first type metal oxide semiconductor field-effect transistor, the one the first type metal oxide semiconductor field-effect transistors have a first grid structure, one first source area and one first drain region;

On this substrate, form one the two the first type metal oxide semiconductor field-effect transistor, the two the first type metal oxide semiconductor field-effect transistors have a second grid structure, one second source area and one second drain region;

With one first mask, the one the first type metal oxide semiconductor field-effect transistors being carried out to a first bagging plants; And

With one second mask, the two the first type metal oxide semiconductor field-effect transistors being carried out to one second sack cloth plants;

Wherein, the direction of this second grid structure is different from the direction of this first grid structure.

7. method as claimed in claim 6, wherein the direction of the direction of this first grid structure and this second grid structure is in fact 90 degree.

8. method as claimed in claim 6, wherein this first bagging is planted and is put on the formed one first raceway groove two ends of this first grid structure and this first source area and this first drain region.

9. method as claimed in claim 8, wherein this second sack cloth is planted and is put on the formed one second raceway groove two ends of this second grid structure and this second source area and this second drain region

10. method as claimed in claim 9, this first bagging wherein carrying out with this first mask is planted the angle being applied and is planted with this second sack cloth carrying out with this second mask the angle applying and be in fact 90 degree.

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