CN103579149B - Semiconductor structure and manufacturing process thereof - Google Patents

Abstract

The invention relates to a semiconductor structure and a manufacturing process thereof, wherein the manufacturing process comprises the steps of providing a carrier; forming a first photoresist layer; forming a plurality of cores; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of bonding portions, each bonding portion including a first bonding layer and a second bonding layer, each bonding portion connecting each core portion to form a hybrid bump, wherein each first bonding layer has a base portion, a protruding portion and an accommodating space, each base portion has an upper surface, each protruding portion protrudes from the upper surface, each protruding portion is located above each core portion, each accommodating space is located outside each protruding portion, and the second bonding layer covers the protruding portions and the upper surfaces and is filled in the accommodating space; and removing the second photoresist layer to expose the hybrid bump.

Description

Semiconductor structure and its manufacturing process

technical field

The invention relates to a semiconductor structure and its manufacturing process, in particular to a semiconductor structure capable of improving packaging reliability and its manufacturing process.

Background technique

Please refer to FIG. 6, the existing conventional semiconductor package structure 200 includes a substrate 210, a chip 220 and a plurality of solders 230, the substrate 210 has a plurality of connection pads 211, the chip 220 has a plurality of bumps 221, the solder 230 is spot-coated on the bumps 221 and pressed against the substrate 210 and the chip 220 to electrically connect the bumps 221 and the connection pads 211 through the solder 230. However, due to the increasing volume of electronic products, Therefore, the distance between the bumps 221 and the connection pads 211 is relatively smaller. In this case, the solder 230 is likely to overflow to the adjacent bumps or adjacent connection pads during reflow to cause a short circuit. situation, leading to poor product yield.

In view of the above existing defects in the semiconductor structure and its manufacturing process, the inventor, based on his rich practical experience and professional knowledge in the design and manufacture of such products for many years, and in conjunction with the application of academic theory, actively researched and innovated, in order to create a The semiconductor with the new structure and its manufacturing process can improve the general existing semiconductor and make it more practical. Through continuous research, design, and after repeated trial samples and improvements, the present invention with practical value is finally created.

Contents of the invention

The purpose of the present invention is to overcome the defects existing in the existing semiconductor structure and provide a semiconductor structure with a new structure. The technical problem to be solved is to prevent short circuit caused by solder overflowing to adjacent bumps, thereby improving product yield. more practical.

Another object of the present invention is to overcome the defects in the existing semiconductor structure manufacturing process and provide a new semiconductor structure manufacturing process. , improve product yield and be more suitable for practical semiconductor structures.

The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. According to the semiconductor structure proposed by the present invention, it at least includes: a carrier having a surface and a plurality of UBM layers formed on the surface; and a plurality of hybrid bumps formed on the UBM layer. Each of the hybrid bumps has a core and a bonding portion, the core has a top surface, the bonding portion includes a first bonding layer and a second bonding layer, the first bonding layer is formed on the top of the core surface and the UBM layer, wherein the first bonding layer has a base portion, a protruding portion and an accommodating space, the base portion has an upper surface, the protruding portion protrudes from the upper surface, and the protruding The part is located above the core part, the accommodating space is located outside the protruding part, and the second bonding layer covers the protruding part and the upper surface and fills in the accommodating space.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

In the aforementioned semiconductor structure, each of the base portions has sidewalls, and the second bonding layer covers the sidewalls.

The aforementioned semiconductor structure, wherein each of the cores has a first core layer and a second core layer, the first core layer has a first thickness, the second core layer has a second thickness, and the first thickness is greater than the second thickness .

In the aforementioned semiconductor structure, each of the base portions has a first height, each of the second bonding layers has a second height, and each of the first heights is not smaller than each of the second heights.

In the aforementioned semiconductor structure, the material of the UBM layer is selected from titanium/copper or titanium-tungsten/copper.

In the aforementioned semiconductor structure, the material of the first core layer is copper, and the material of the second core layer is nickel.

In the aforementioned semiconductor structure, the material of the first bonding layer is selected from copper or gold.

In the aforementioned semiconductor structure, the material of the second bonding layer is solder.

The purpose of the present invention and the solution to its technical problem also adopt the following technical solutions to achieve. According to the manufacturing process of the semiconductor structure proposed by the present invention, it at least includes the following steps: providing a carrier, the carrier has a surface and a metal layer formed on the surface, the metal layer has a plurality of first regions and a plurality of A second area outside the first area; forming a first photoresist layer on the metal layer, the first photoresist layer has a plurality of first openings; forming a plurality of cores in the first openings; removing the A first photoresist layer to expose the cores, each of which has a top surface; a second photoresist layer is formed on the metal layer, the second photoresist layer has a plurality of second openings and the The second opening exposes the top surface of the core; forming a plurality of joints in the second opening, each of the joints includes a first joint layer and a second joint layer, and each of the first joint layers formed on the top surface of each of the cores and the metal layer, so that each of the joints connects each of the cores to form a hybrid bump, wherein each of the first joint layers has a base portion, a protruding portion, and an accommodating space , each of the base parts has an upper surface, each of the protrusions protrudes from the upper surface, and each of the protrusions is located above each of the cores, each of the accommodating spaces is located outside each of the protrusions, and the first a second bonding layer covering the protruding portion and the upper surface and filling in the accommodating space; removing the second photoresist layer to reveal the mixed bump; and removing all the metal layer The second region is formed so that the first region of the metal layer forms a plurality of UBM layers.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

The manufacturing process of the aforementioned semiconductor structure further includes a step of reflowing the second bonding layer, and each of the base portions has sidewalls, and the second bonding layer covers the sidewalls.

The manufacturing process of the aforementioned semiconductor structure, wherein each of the cores has a first core layer and a second core layer, the first core layer has a first thickness, the second core layer has a second thickness, and the first thickness is greater than the second thickness.

In the manufacturing process of the aforementioned semiconductor structure, each of the base portions has a first height, each of the second bonding layers has a second height, and each of the first heights is not smaller than each of the second heights.

In the aforementioned manufacturing process of the semiconductor structure, the material of the UBM layer is selected from titanium/copper or titanium-tungsten/copper.

In the manufacturing process of the aforementioned semiconductor structure, the material of the first core layer is copper, and the material of the second core layer is nickel.

In the manufacturing process of the aforementioned semiconductor structure, the material of the first bonding layer is selected from copper or gold.

In the manufacturing process of the aforementioned semiconductor structure, the material of the second bonding layer is solder.

Compared with the prior art, the present invention has obvious advantages and beneficial effects. With the above technical solution, the semiconductor structure and its manufacturing process of the present invention can achieve considerable technical advancement and practicability, and have wide industrial application value, which at least can prevent the second bonding layer from overflowing to the adjacent hybrid Bumps cause short circuits, improving product yield and other advantages.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited, and in conjunction with the accompanying drawings, the detailed description is as follows.

Description of drawings

Fig. 1: According to the first embodiment of the semiconductor structure and its manufacturing process of the present invention, a flow chart of a semiconductor manufacturing process.

2A-2I are cross-sectional views of the semiconductor structure according to the first embodiment of the semiconductor structure and its manufacturing process of the present invention.

Fig. 3: A perspective view of the semiconductor structure according to the first embodiment of the semiconductor structure and its manufacturing process of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor structure according to the second embodiment of the semiconductor structure and its manufacturing process of the present invention.

FIG. 5 is a cross-sectional view of a semiconductor structure according to the third embodiment of the semiconductor structure and its manufacturing process of the present invention.

Fig. 6: A schematic diagram of a conventional semiconductor package structure.

10: Provide a carrier, the carrier has a surface and a metal layer formed on the surface

11: Form the first photoresist layer

12: Forming multiple cores

13: remove the first photoresist layer

14: Form the second photoresist layer

15: Forming a plurality of junctions, each of which includes a first junction layer and a second junction layer

16: Remove the second photoresist layer

17: Remove the metal layer

18: Reflow the second bonding layer

100: Semiconductor Structures

110: carrier 111: surface

112: UBM layer

120: hybrid bump 121: core

121a: top surface 121b: first core layer

121c: second core layer 122: junction

122a: first bonding layer 122b: second bonding layer

122c: Base part 122d: Protrusion part

122e: accommodation space 122f: upper surface

122g: side wall

200: Semiconductor package structure

210: substrate 211: connection pad

220: chip 221: bump

230: Solder

H1: first height H2: second height

M: metal layer M1: first area

M2: second area

O1: first opening O2: second opening

P1: first photoresist layer P2: second photoresist layer

S: curved surface

T1: first thickness T2: second thickness

detailed description

In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, the specific implementation methods, structures, characteristics and details of the semiconductor manufacturing process and its semiconductor structure proposed according to the present invention will be described below in conjunction with the accompanying drawings and preferred embodiments. Its effect is described in detail below.

Please refer to Fig. 1, Fig. 2A-Fig. 2I, it is the first embodiment of the present invention, a kind of semiconductor manufacturing process comprises the following steps: first, please refer to step 10 of Fig. 1 and Fig. 2A, provide carrier 110, this carrier 110 There is a surface 111 and a metal layer M formed on the surface 111, the metal layer M has a plurality of first regions M1 and a plurality of second regions M2 outside the first regions M1; then, please refer to the steps in FIG. 1 11 and FIG. 2B, forming a first photoresist layer P1 on the metal layer M, the first photoresist layer P1 has a plurality of first openings O1; after that, please refer to step 12 of FIG. 1 and FIG. 2C to form A plurality of cores 121 are in the first opening O1; then, please refer to step 13 of FIG. 1 and FIG. 2D, remove the first photoresist layer P1 to expose the cores 121, each of the cores 121 has a top surface 121a; then, referring to step 14 of FIG. 1 and FIG. 2E, a second photoresist layer P2 is formed on the metal layer M, the second photoresist layer P2 has a plurality of second openings O2 and The second opening O2 exposes the top surface 121a of the core portion 121; then, please refer to step 15 of FIG. 1 and FIG. The part 122 includes a first bonding layer 122a and a second bonding layer 122b, and each of the first bonding layers 122a is formed on the top surface 121a of each of the core parts 121 and the metal layer M, so that each of the bonding parts 122 connects each The core portion 121 forms a hybrid bump 120, wherein each of the first bonding layers 122a has a base portion 122c, a protruding portion 122d, and an accommodating space 122e, each of the base portions 122c has an upper surface 122f, and each of the protruding portions 122d protrudes from the upper surface 122f, and each of the protruding parts 122d is located above each of the core parts 121, and each of the accommodating spaces 122e is located outside each of the protruding parts 122d, and the second bonding layer 122b covers the protruding parts. The portion 122d and the upper surface 122f are filled in the accommodating space 122e. In this embodiment, each of the base portions 122c has a first height H1, and each of the second bonding layers 122b has a second height H2. The first height H1 is not smaller than each of the second heights H2, and the material of the first bonding layer 122a is selected from copper or gold, and the material of the second bonding layer 122b is solder.

After that, please refer to step 16 of FIG. 1 and FIG. 2G, remove the second photoresist layer P2 to reveal the hybrid bump 120; then, please refer to step 17 of FIG. 1 and FIG. 2H, remove the metal The second region M2 of the layer M, so that the first region M1 of the metal layer M forms a plurality of UBM layers 112, and the material of the UBM layers 112 is selected from titanium/copper or Titanium Tungsten/Copper. Finally, referring to step 18 of FIG. 1 and FIG. 2I, the second bonding layer 122b is reflowed so that the second bonding layer 122b is formed with an arc-shaped surface S and covers the protruding portion 122d and the upper surface 122f And fill in the accommodating space 122e, and form the semiconductor structure 100, because the bonding portion 122 of the hybrid bump 120 has the first bonding layer 122a and the second bonding layer 122b, and the The first bonding layer 122a has the base portion 122c, the protruding portion 122d formed above the core portion 121 and the accommodating space 122e, so when the semiconductor structure 100 is thermally bonded to the substrate (not shown in the figure) When out), the second bonding layer 122b will move outward under pressure and fill in the accommodating space 122e, thus preventing the second bonding layer 122b from overflowing to the adjacent hybrid bump 120 and causing a short circuit. Situation happens.

Next, please refer to FIG. 2I and FIG. 3, which is a semiconductor structure 100 according to the first embodiment of the present invention, which at least includes a carrier 110 and a plurality of mixed bumps 120, and the carrier 110 has a surface 111 and a plurality of The UBM layer 112 formed on the surface 111, the material of the UBM layer 112 is selected from titanium/copper or titanium-tungsten/copper, the hybrid bump 120 is formed on the UBM On the layer 112, each of the hybrid bumps 120 has a core 121 and a bonding portion 122, the core 121 has a top surface 121a, the bonding portion 122 includes a first bonding layer 122a and a second bonding layer 122b, the first The material of a bonding layer 122a is selected from copper or gold, the material of the second bonding layer 122b is solder, and the first bonding layer 122a is formed on the top surface 121a of the core 121 (as shown in FIG. 2E ). And on the UBM layer 112, wherein the first bonding layer 122a has a base portion 122c, a protruding portion 122d, and an accommodating space 122e, the base portion 122c has an upper surface 122f and a first height H1, the protruding portion 122d protrudes from the upper surface 122f, and the protruding portion 122d is located above the core 121, the accommodating space 122e is located outside the protruding portion 122d, and the second bonding layer 122b covers the protruding portion 122d and the upper surface. The surface 122f is filled in the accommodating space 122e, the second bonding layer 122b has a second height H2, and each of the first heights H1 is not less than each of the second heights H2.

Or, please refer to FIG. 4, which is a second embodiment of the present invention, a semiconductor structure 100, which at least includes a carrier 110 and a plurality of mixed bumps 120, the carrier 110 has a surface 111 and a plurality of bumps formed on the The UBM layer 112 on the surface 111, the hybrid bumps 120 are formed on the UBM layer 112, each of the hybrid bumps 120 has a core portion 121 and a bonding portion 122, wherein the first embodiment The difference from the second embodiment is that each of the cores 121 of the second embodiment has a first core layer 121b and a second core layer 121c, and each of the second core layers 121c is located on each of the first core layers 121b Between each of the first bonding layers 122a (as shown in FIG. 2I ), the first core layer 121b has a first thickness T1, the second core layer 121c has a second thickness T2, and the first thickness T1 is greater than the first thickness T1. Two thickness T2, the material of the first core layer 121b is copper, the material of the second core layer 121c is nickel, when the material of the first bonding layer 122a is selected from gold, and the material of the core 121 When the first core layer 121b is copper, since the second core layer 121c of the core portion 121 is nickel, the bonding strength between the first bonding layer 122a and the first core layer 121b can be increased.

Preferably, please refer to FIG. 5, which is a third embodiment of the present invention, a semiconductor structure 100, which at least includes a carrier 110 and a plurality of mixed bumps 120, the carrier 110 has a surface 111 and a plurality of formed On the UBM layer 112 on the surface 111, the hybrid bumps 120 are formed on the UBM layer 112, each of the hybrid bumps 120 has a core portion 121 and a joint portion 122, and the core portion 121 Having a top surface 121a, the bonding portion 122 includes a first bonding layer 122a and a second bonding layer 122b, the first bonding layer 122a is formed on the top surface 121a of the core portion 121 and the UBM layer 112, Wherein the first bonding layer 122a has a base portion 122c, a protruding portion 122d and an accommodating space 122e. In this embodiment, the third embodiment differs from the first embodiment in that the third embodiment The base portion 122c has sidewalls 122g. In the step of reflowing the second bonding layer 122b, the second bonding layer 122b also covers the sidewalls 122g, so that the semiconductor structure 100 and the substrate (not shown) The hybrid bump 120 of the semiconductor structure 100 is not easy to peel off from the substrate during packaging.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, can use the technical content disclosed above to make some changes or modify them into equivalent embodiments with equivalent changes, but any content that does not depart from the technical solution of the present invention, according to the present invention Any simple modifications, equivalent changes and modifications made to the above embodiments by the technical essence still belong to the scope of the technical solutions of the present invention.

Claims (17)

1. a semiconductor structure, it is characterised in that it includes at least:

One carrier, it has a surface and multiple Underbump metallization layer being formed on this surface；And

Multiple blend together projection, it is formed on described Underbump metallization layer, respectively this blendes together projection and has core and junction surface, this core has end face, this junction surface includes the first bonding layer and the second bonding layer, this first bonding layer is formed on this end face and this Underbump metallization layer of this core, wherein this first bonding layer has basilar part, protuberance and accommodation space, this basilar part has the first height and upper surface, this first height is more than the height of this core, this protuberance protrudes from this upper surface, and this protruding parts is above this core, this accommodation space is positioned at outside this protuberance, this second bonding layer covers this protuberance and this upper surface and is filled in this accommodation space.

Semiconductor structure the most according to claim 1, it is characterised in that respectively this basilar part has sidewall, described second bonding layer covers described sidewall.

Semiconductor structure the most according to claim 1, it is characterised in that respectively this core has the first sandwich layer and the second sandwich layer, this first sandwich layer has the first thickness, and this second sandwich layer has the second thickness, and this first thickness is more than this second thickness.

Semiconductor structure the most according to claim 1, it is characterised in that respectively this second bonding layer has the second height, and respectively the first height of this basilar part is not less than respectively this second height.

Semiconductor structure the most according to claim 1, it is characterised in that the material of described Underbump metallization layer is selected from titanium/copper or titanium tungsten/copper.

6., according to the semiconductor structure that claim 3 is described, it is characterised in that the material of this first sandwich layer is copper, the material of this second sandwich layer is nickel.

Semiconductor structure the most according to claim 1, it is characterised in that the material of the first described bonding layer is selected from copper or gold.

Semiconductor structure the most according to claim 1, it is characterised in that the material of the second described bonding layer is solder.

9. a semiconductor structure, it is characterised in that it includes at least:

One carrier, it has a surface and multiple Underbump metallization layer being formed on this surface；And

Multiple blend together projection, it is formed on described Underbump metallization layer, respectively this blendes together projection and has core and junction surface, this core has end face, this junction surface includes the first bonding layer and the second bonding layer, this first bonding layer is formed on this end face and this Underbump metallization layer of this core, wherein this first bonding layer has basilar part, protuberance and accommodation space, this basilar part has the first height and upper surface, this protuberance protrudes from this upper surface, and this protruding parts is above this core, this accommodation space is positioned at outside this protuberance, this second bonding layer covers this protuberance and this upper surface and is filled in this accommodation space, this second bonding layer has the second height, first height of this basilar part is not less than the second height of this second bonding layer, and the material of this second bonding layer is solder.

10. the manufacturing process of semiconductor structure as described in claim 1 to 9 any claim, it is characterised in that it is including at least following steps:

Thering is provided carrier, this carrier has a surface and is formed at the metal level on this surface, and this metal level has multiple firstth district and multiple the secondth district being positioned at outside this firstth district；

Forming the first photoresist layer in this metal level, this first photoresist layer has multiple first opening；

Form multiple core in described first opening；

Removing this first photoresist layer to manifest described core, respectively this core has end face；

Forming the second photoresist layer on this metal level, this second photoresist layer has multiple second opening and described second opening appears the described end face of described core；

Form multiple junction surface in described second opening, respectively this junction surface includes the first bonding layer and the second bonding layer, respectively this first bonding layer is formed on this end face and this metal level of respectively this core, make respectively this junction surface connect respectively this core and blend together projection to be formed, respectively this first bonding layer has basilar part, protuberance and accommodation space, respectively this basilar part has upper surface, respectively this protuberance protrudes from this upper surface, and respectively this protruding parts above respectively this core, respectively this accommodation space is positioned at respectively outside this protuberance, described second bonding layer covers described protuberance and described upper surface and is filled in described accommodation space；

Remove this second photoresist layer and blend together projection described in manifesting；And

Remove described secondth district of this metal level, so that described firstth district of this metal level forms multiple Underbump metallization floor.

The manufacturing process of 11. semiconductor structures according to claim 10, it is characterised in that it also includes the step of the second bonding layer described in reflow, and respectively this basilar part has sidewall, and described second bonding layer covers described sidewall.

The manufacturing process of 12. semiconductor structures according to claim 10, it is characterised in that respectively this core has the first sandwich layer and the second sandwich layer, this first sandwich layer has the first thickness, and this second sandwich layer has the second thickness, and this first thickness is more than this second thickness.

The manufacturing process of 13. semiconductor structures according to claim 10, it is characterised in that respectively this basilar part has the first height, and respectively this second bonding layer has the second height, and respectively this first height is not less than respectively this second height.

The manufacturing process of 14. semiconductor structures according to claim 10, it is characterised in that the material of described Underbump metallization layer is selected from titanium/copper or titanium tungsten/copper.

The manufacturing process of 15. semiconductor structures according to claim 12, it is characterised in that the material of this first sandwich layer is copper, the material of this second sandwich layer is nickel.

The manufacturing process of 16. semiconductor structures according to claim 10, it is characterised in that the material of described first bonding layer is selected from copper or gold.

The manufacturing process of 17. semiconductor structures according to claim 10, it is characterised in that the material of described second bonding layer is solder.