CN103546152B - Pipeline Architecture Analog-to-Digital Converter and Its Offset Voltage Effect Correction Method - Google Patents

Abstract

A pipeline architecture analog-to-digital converter and an offset voltage influence correction method thereof, the method generates a first-level code and a first output voltage according to a first input voltage; generates a second-level code according to the first output voltage; generates a confirmation code according to the output voltage; determines a first correction code by referring to the first-level code and the confirmation code; and corrects the first-level code with the first correction code when the first-level code is different from the first correction code.

Description

Pipeline Architecture Analog-to-Digital Converter and Its Offset Voltage Effect Correction Method

technical field

The invention relates to an analog-to-digital conversion circuit, and in particular to an analog-to-digital conversion circuit including multiple digital-to-analog converters.

Background technique

Analog digital converter (Analog digital converter; ADC), as the name suggests, converts analog data signals into digital codes, and the action of this conversion is to digitize and quantize analog signals. Analog-to-digital converters are an essential part of mixed-signal integrated circuits. Once the analog signal is converted to the digital domain, those complex signal processing processes can be implemented in a simpler way, and the immunity to noise will be improved. In some cases, implementing the ADC in a deep sub-micron process will reduce power consumption.

Analog-to-digital converters use a variety of functional architectures, such as integration, successive approximation, flash, and delta-sigma architectures. Recently, pipeline-based analog-to-digital converters have become the mainstream of analog-to-digital converters, which can be used in high-speed applications, such as charge-coupled device image processing (CCD imaging), ultrasonic medical photography, digital imaging, and communication technologies such as Cable modem, and high-speed Ethernet. Due to the characteristics of high accuracy, high output rate, and low power loss, the analog-to-digital converter with pipeline architecture has been widely used in various circuit systems. In addition, pipeline architectures typically provide better performance and smaller area for a given power compared to other types of ADC architectures.

With the digital error correction function, the analog-to-digital converter of the pipeline architecture can tolerate a large comparator voltage offset. However, due to the decrease of the supply voltage VDD in the advanced process, it is difficult to achieve a sufficient operating range of the reference voltage, resulting in reduced tolerance of the voltage offset of the comparator.

FIG. 1 and FIG. 2 show traditional pipeline architecture ADCs with and without sample and hold amplifiers. A traditional pipeline architecture analog-to-digital converter generally adopts a stage circuit 101 and a sample and hold amplifier (sample and hold amplifier; SHA) 113, wherein the stage circuit 101 usually includes an analog-to-digital converter 111 and a stage-type digital-to-analog converter (multiplying digital to analog converter (MDAC) 103, the cascaded digital to analog converter 103 has a sample and hold (sample and hold circuit; S/H) circuit 105, a digital to analog converter 107, and an amplifier 109. In order to provide a stable synchronous signal to the cascaded digital-to-analog converter 103 and the analog-to-digital converter 111 in the cascade circuit 101 for sampling, a sample-and-hold amplifier 113 is required. However, the sample-and-hold amplifier 113 will increase power consumption and noise interference. Therefore, the sample-and-hold amplifier 113 is usually not used in low-power pipeline architecture analog-to-digital converters, making the architecture of omitting the sample-and-hold amplifier in FIG. 2 become the mainstream.

However, there is usually an unavoidable timing difference between the sample-and-hold circuit 105 and the DAC 107 due to sampling mismatches, resulting in signal-dependent offsets that increase with fan-in/fan-out (fin) Increase. In this way, the tolerable offset of the comparator will be reduced, and the bandwidth of the input signal of the analog-to-digital converter will also be limited.

FIG. 3 and FIG. 4 are schematic diagrams illustrating output voltage waveforms of the stage circuits in the pipeline architecture ADC. In FIG. 3 and FIG. 4 , points A and B represent the situation where the offset of the comparator exceeds the normal operating range. Since the offset of the comparator will be amplified by subsequent circuits, this will lead to the generation of wrong codes and other serious errors.

Contents of the invention

Therefore, the object of the present invention is to provide a method for correcting the influence of the offset voltage, which can correct the error code and the out-of-range output voltage caused by the offset voltage of the comparator, so as to avoid errors in the operation of the overall circuit.

According to the embodiment of the present invention, the method for correcting the influence of the offset voltage of the pipeline architecture analog-to-digital converter generates the first level code and the first output voltage according to the first input voltage; generates the second level code according to the first output voltage; and generates the second level code according to the first output voltage. An output voltage generates a confirmation code; referring to the first level code and the confirmation code, the first correction code is determined; when the first level code is different from the first correction code, the first level code is used to correct the first level code.

Another object of the present invention is to provide a pipeline architecture analog-to-digital converter, which can self-correct error codes caused by comparator offset voltages and out-of-range output voltages, so as to avoid errors in the operation of the overall circuit.

According to another embodiment of the present invention, a pipeline architecture ADC includes an acknowledgment code generator, a code correction circuit, and an offset voltage correction circuit. The confirmation code generator generates the confirmation code according to the first output voltage output by the first-stage circuit of the analog-to-digital converter of the pipeline structure; Generated first-level codes, second-level codes, and confirmation codes, the code correction circuit also refers to the confirmation codes, first-level codes, and second-level codes to correct the wrong first-level codes and second-level codes; offset The voltage correction circuit adjusts the output voltage of the second stage circuit according to the second stage code and the confirmation code.

The method for correcting the influence of the offset voltage and the analog-to-digital converter of the pipeline structure in the above embodiments can correct the error code and the out-of-range output voltage caused by the offset voltage of the comparator, and avoid errors in the operation of the overall circuit.

Description of drawings

In order to make the above and other objects, features, advantages and embodiments of the present invention more comprehensible, the accompanying drawings are described as follows:

Figures 1 and 2 illustrate conventional pipeline architecture ADCs with and without sample-and-hold amplifiers.

FIG. 3 and FIG. 4 are schematic diagrams illustrating output voltage waveforms of the stage circuits in the pipeline architecture ADC.

FIG. 5 is a block diagram illustrating a pipeline architecture ADC according to an embodiment of the present invention.

FIG. 6 is a schematic circuit diagram illustrating a confirmation code generator according to an embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating a first stage circuit according to an embodiment of the present invention.

FIG. 8 is a circuit diagram illustrating a second stage circuit according to an embodiment of the present invention.

FIG. 9 is a flow chart illustrating a method for calibrating the influence of an offset voltage of an analog-to-digital converter with a pipeline architecture according to an embodiment of the present invention.

FIG. 10 is a truth table illustrating codes of an analog-to-digital converter with a pipeline architecture according to an embodiment of the present invention.

FIG. 11 is a diagram illustrating the conversion characteristic curves of the input signal and the output signal of the analog-to-digital converter of the pipeline architecture according to the embodiment of the present invention.

FIG. 12 is a diagram illustrating a truth table representing pipeline architecture ADC code according to an embodiment of the present invention.

FIG. 13 is a schematic diagram of the waveform of the output voltage of the stage circuit in the embodiment of the present invention.

detailed description

The offset voltage influence correction method and the pipeline structure analog-to-digital converter of the following embodiments can correct the error code and the out-of-range output voltage caused by the offset voltage of the comparator, so as to avoid errors in the operation of the whole circuit.

Please refer to FIG. 5 , which shows a block diagram of a pipeline architecture analog-to-digital converter according to an embodiment of the present invention. The pipeline architecture analog-to-digital converter 500 includes several stages of circuits, that is, a first stage circuit 503 , a second stage circuit 505 , a third stage circuit 507 , and up to an Nth stage circuit. The pipeline architecture ADC 500 further includes an acknowledgment code generator 511 , an offset voltage correction circuit 513 , and a code correction circuit 501 , wherein the code correction circuit 501 has a correction code generator 521 and a built-in decoding logic circuit 519 .

The first stage circuit 503 receives the input voltage Vin, and generates the first stage codes C11, C12 and the first output voltage Vout1 according to the input voltage Vin; the second stage circuit 505 generates the second stage codes C22, C23 according to the first output voltage Vout1. The confirmation code generator 511 generates confirmation codes C21 and C24 according to the first output voltage Vout1 .

The code correction circuit 501 receives the first-stage codes C11, C12, and the second-stage codes C22, C23 generated by the first-stage circuit 503, the second-stage circuit 505, and the confirmation code generator 511 of the pipeline architecture analog-to-digital converter, respectively. , and confirmation codes C21, C24. The code correction circuit 501 corrects the erroneous first level codes C11, C12 and second level codes C22, C23 with reference to the confirmation codes C21, C24 and first level codes C11, C12. Further, the correction code generation circuit 521 of the code correction circuit 501 will refer to the first-level codes C11, C12, second-level codes C22, C23, and confirmation codes C21, C24 to generate correction codes, and then deliver the correction codes to The decoding logic circuit 519 of the code correction circuit 501 . Finally, the code correction circuit 501 outputs the digital code accordingly.

In addition, the offset voltage correction circuit 513 adjusts the output voltage Vout2 of the second stage circuit 505 according to the second stage codes C22, C23 and confirmation codes C21, C24.

Please refer to FIG. 6 , which shows a schematic circuit diagram of a verification code generator according to an embodiment of the present invention. As shown in FIG. 6 , the first comparator 601 and the second comparator 607 are set in the confirmation code generator, and the third comparator 603 and the fourth comparator 605 are set in the second stage circuit. In addition, the fifth comparator 609 and the sixth comparator 611 are disposed in the first stage circuit.

The first comparator 601 has a first input terminal and a second input terminal, the first input terminal is connected to the input port to receive the input voltage Vin, and the second input terminal is connected to the positive reference voltage input terminal to receive the positive reference voltage Vref. The second comparator 607 has a third input terminal and a fourth input terminal, the third input terminal is connected to the input port to receive the input voltage Vin, and the fourth input terminal is connected to the negative reference voltage terminal to receive the negative reference voltage -Vref.

The first comparator 601 and the second comparator 607 compare the input voltage Vin, the positive reference voltage Vref and the negative reference voltage −Vref, and then output confirmation codes C21 and C24 accordingly.

Please refer to FIG. 7 , which shows a circuit diagram of the first stage circuit according to the embodiment of the present invention. The first-stage circuit is a part of a cascaded digital-to-analog converter (MDAC). The first-stage circuit mainly includes an operational amplifier 701, a first switch sw1, a second switch sw2, a third switch sw3, a fourth switch sw4, a Five switches sw5, a first capacitor cs1 and a second capacitor cs2. The operational amplifier 701 has a positive input terminal +, a negative input terminal −, and an output terminal, wherein the positive input terminal + is connected to ground.

The first switch sw1 is connected between the negative input terminal − and the ground terminal; the second switch sw2 and the third switch sw3 have a plurality of first terminals connected to the voltage input terminal to receive the input voltage Vin. The terminals of the first capacitor cs1 and the second capacitor cs2 are connected to the negative input terminal − of the operational amplifier 701, and the other terminals of the first capacitor cs1 and the second capacitor cs2 are connected to the second terminal of the second switch sw2 and the third switch sw3. terminal; the fourth switch sw4 is connected to the second terminal of the second switch sw2 and the output terminal of the operational amplifier 701 . One terminal of the fifth switch sw5 is connected to the second terminal of the third switch sw3, and the other terminal of the fifth switch sw5 is connected to the reference voltage input terminal Vdac.

The second switch sw2 and the third switch sw3 are controlled by the first clock signal ck1 , the fourth switch sw4 and the fifth switch sw5 are controlled by the third clock signal ck3 , and the first switch sw1 is controlled by the second clock signal ck2 . The rising edges of the first clock signal ck1 and the second clock signal ck2 are aligned, and the falling edges of the third clock signal ck3 are aligned with the rising edges of the first clock signal ck1 and the second clock signal ck2 . Further, the high level period of the first clock signal ck1 is longer than the high level period of the second clock signal ck2 .

Through such a structure and clock signal timing, when the first-level code is equal to 2’b00 or 2’b11, the output voltage Vout1 from the first-level circuit will directly add or subtract the reference voltage.

Please refer to FIG. 8 , which shows a circuit diagram of the second stage circuit according to the embodiment of the present invention. The second-stage circuit mainly includes an operational amplifier 801, a first switch sw1, a second switch sw2, a third switch sw3, a fourth switch sw4, a fifth switch sw5, a sixth switch sw6, a seventh switch sw7, and a first capacitor cs1 , the second capacitor cs2 and the third capacitor cs3. The operational amplifier 801 has a positive input terminal +, a negative input terminal −, and an output terminal, wherein the positive input terminal + is connected to the ground terminal, and the third capacitor cs3 is connected between the negative input terminal − and the output terminal of the operational amplifier 801 .

The first switch sw1 is connected between the negative input terminal − and the ground terminal; the second switch sw2 and the third switch sw3 have a plurality of first terminals connected to the voltage input terminal to receive the input voltage Vout1 . One terminal of the first capacitor cs1 and the second capacitor cs2 is connected to the negative input terminal − of the operational amplifier 801, and the other terminal of the first capacitor cs1 and the second capacitor cs2 is connected to the second switch sw2 and the third switch sw3. Two terminals; the fourth switch sw4 is connected to the second terminal of the second switch sw2 and the first reference voltage terminal Vdac1. One terminal of the fifth switch sw5 is connected to the second terminal of the third switch sw3, and the other terminal of the fifth switch sw5 is connected to the second reference voltage input terminal Vdac2.

The second switch sw2 and the third switch sw3 are controlled by the first clock signal ck1, the fourth switch sw4, the fifth switch sw5, and the seventh switch sw7 are controlled by the third clock signal ck3, the first switch sw1 and the sixth The switch is controlled by the second clock signal ck2. The rising edges of the first clock signal ck1 and the second clock signal ck2 are aligned, and the falling edges of the third clock signal ck3 are aligned with the rising edges of the first clock signal ck1 and the second clock signal ck2 . Further, the high level period of the first clock signal ck1 is longer than the high level period of the second clock signal ck2 .

With such a structure and clock signal timing, when the combination of the second level code and the confirmation code (C21, C22, C23, C24) is equal to 4'b0000, 4'b1000, 4'b1110, or 4'b1111, from the second The output voltage Vout2 from the stage circuit will directly add or subtract the reference voltage.

Please refer to FIG. 9 , which shows a flow chart of a method for correcting the offset voltage of an analog-to-digital converter with pipeline architecture according to an embodiment of the present invention. The method first generates a first-level code and a first output voltage according to a first input voltage (step 901 ), and generates a second-level code according to the first output voltage (step 903 ). Next, a confirmation code is generated according to the first output voltage (step 905 ), and a first calibration code is determined by referring to the first level code and the confirmation code (step 907 ).

Then, it will be confirmed whether the first level code is different from the first correction code (step 909), and when the first level code is different from the first correction code, the first level code is corrected with the first correction code (step 911 ), and use the positive reference voltage (+Vref) or the negative reference voltage (-Vref) to adjust the second output voltage of the second stage circuit. For example, if the second output voltage is too high, the reference voltage is subtracted from the second output voltage to reduce the second output voltage.

Specifically, the generation of the confirmation code is to compare the first output voltage with the positive reference voltage (+Vref) and the negative reference voltage (-Vref), as shown in the table of FIG. 10 and the waveform of FIG. 11 , when the first When the output voltage is lower than -Vref and exceeds the operating range (that is, point A in FIG. 11 ), if the class code and the output voltage are not corrected immediately, a missing code will occur. In order to avoid the occurrence of wrong codes, a confirmation code (c21, c24) equal to 2’b00 and a first correction code (MSB1LSB1) equal to 2’b00 or 2’b01 will be generated to replace the wrong first-level code.

In other embodiments, when the first output voltage exceeds +Vref and is out of range (point B in Figure 11), a confirmation code (c21c24) equal to 2'b11 and a confirmation code (c21c24) equal to 2'b01 or 2'b10 will be generated. First correction code (MSB1LSB1).

FIG. 12 shows a truth table representing normal and error states of a pipeline architecture ADC according to an embodiment of the present invention, and FIG. 13 shows a schematic waveform diagram of output voltages of stage circuits according to an embodiment of the present invention. In the embodiment shown in Figures 12 and 13, it is further considered that the input voltage is inherently higher than the positive reference voltage or lower than the negative reference voltage. offset voltage of the device. In Figure 13, points A, D, E, and H are out of range because the original input voltage itself is very high, and the voltage of these points does not need special correction.

Therefore, when the combination of the first stage code, confirmation code, and second stage code equals 6'b001111, 6'b100000, 6'b101111, and 6'b110000, the first correction code (MSB2LSB2) equal to 2'b01 will Used to fix first class codes (c11c12).

On the other hand, if it is found in step 909 that the first-level code is identical to the first corrected code, then the first-level code will remain the same (step 913). Further, the second correction code can also be determined by referring to the first level code, the second level code and the correction code, and when the second level code is different from the second correction code, the second correction code is used to correct the second correction code code.

According to the above embodiments, the error class code and the out-of-range output voltage caused by the offset voltage of the comparator can be pre-corrected, so that the occurrence of error codes can be prevented, and the output voltage out of range can be avoided, reducing the analog-to-digital conversion of the pipeline architecture The probability of error in the operation of the device.

Although the present invention has been disclosed above in terms of implementation, it is not intended to limit the present invention. Any person skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope is to be determined by the appended claims.

Claims (14)

1. an offset voltage influence correction method for pipeline architecture analog digital converter, described method Comprise:

According to the first input voltage, produce first class's code and the first output voltage；

Second class's code is produced according to described first output voltage；

Produce according to described first output voltage and confirm code；

With reference to described first class's code and described confirmation code, determine the first correction code；And

When described first class's code is different from described first correction code, with described first correction generation Described first class's code is corrected by code.

2. the offset voltage influence correction of pipeline architecture analog digital converter as claimed in claim 1 Method, also comprises:

When described first class's code is different from described first correction code, with reference voltage or negative Reference voltage, adjusts the second output voltage of second class's circuit.

3. the offset voltage influence correction of pipeline architecture analog digital converter as claimed in claim 1 Method, wherein enters described first output voltage and the first reference voltage and the first negative reference voltage Row compares, and produces described confirmation code.

4. the offset voltage influence correction of pipeline architecture analog digital converter as claimed in claim 3 Method, described first class's code that wherein reference look-up tables is stored and described confirmation code, with Determine described first correction code.

5. the offset voltage influence correction of pipeline architecture analog digital converter as claimed in claim 1 Method, wherein when the combination of described first class's code and described confirmation code is corresponding to 4 ' b1000 Time, correct described first class's code with the described first correction code equal to 2 ' b00.

6. the offset voltage influence correction of pipeline architecture analog digital converter as claimed in claim 1 Method, wherein when the combination of described first class's code and described confirmation code is corresponding to 4 ' b0011 Time, correct described first class's code with the described first correction code equal to 2 ' b01.

7. the offset voltage influence correction of pipeline architecture analog digital converter as claimed in claim 1 Method, wherein when the combination of described first class's code and described confirmation code is corresponding to 4 ' b1011 Time, correct described first class's code with the described first correction code equal to 2 ' b10.

8. the offset voltage influence correction of pipeline architecture analog digital converter as claimed in claim 1 Method, also comprises:

With reference to described first class's code, described second class's code, and described confirmation code, certainly Fixed second correction code；And

When described second class's code is different from described second correction code, with described second correction generation Code corrects described second class's code.

9. a pipeline architecture analog digital converter, comprises:

Confirm code generator, with first class's electricity according to described pipeline architecture analog digital converter The first output voltage that road is exported, produces and confirms code；

Code correcting circuit, to receive respectively by described first class's circuit, second class's circuit, with And first class's code, second class's code produced by described confirmation code generator, and described Confirm code, described code correcting circuit also with reference to described confirmation code, described first class's code, And described second class's code corrects described first class's code of mistake and described second class Code；And

Offset voltage correction circuit, according to described second class's code and described confirmation code, to adjust The size of the output voltage of described second class's circuit.

10. pipeline architecture analog digital converter as claimed in claim 9, wherein said confirmation generation Code generator comprises:

First comparator, has first input end and the second input, and described first input end connects Input port receives input voltage, and described second input is then connected to reference voltage input Receive reference voltage；And

Second comparator, has the 3rd input and four-input terminal, and described 3rd input connects Receiving described input voltage to described input port, described four-input terminal is then connected to negative with reference to electricity Pressure side receives negative reference voltage.

11. pipeline architecture analog digital converter as claimed in claim 9, wherein said first rank Level circuit comprises:

Operational amplifier, has positive input terminal, negative input end, and outfan, wherein said the most defeated Enter end and be connected to earth terminal；

First switch, is connected between described negative input end and described earth terminal；

Second switch and the 3rd switch, have multiple first end points, and the plurality of first end points connects Input voltage is received to voltage input end；

First electric capacity and the second electric capacity, the end point of described first electric capacity and described second electric capacity is even It is connected to the described negative input end of described operational amplifier, described first electric capacity and described second electric capacity Another end points is then connected to multiple second end points of described second switch and described 3rd switch；

4th switch, is connected to described second end of described second switch and described operational amplifier Described outfan；And

5th switch, one end of described 5th switch is connected to described second end of described 3rd switch, The other end of described 5th switch is then connected to reference voltage input terminal.

12. pipeline architecture analog digital converter as claimed in claim 11, wherein said second opens Close and controlled by the first clock signal with described 3rd switch, described 4th switch and described 5th switch Being controlled by the 3rd clock signal, described first switch is then controlled by second clock signal.

13. pipeline architecture analog digital converter as claimed in claim 12, when wherein said first Clock signal aligns consistent with the rising edge of described second clock signal, the decline of described 3rd clock signal Edge then aligns described first clock signal and the plurality of rising edge of described second clock signal.

14. pipeline architecture analog digital converter as claimed in claim 13, when wherein said first The high levle cycle of the high levle cycle more described second clock signal of clock signal is for long.