CN103544331B - A kind of dummy comprehensive optimization method based on CMP simulation model - Google Patents

Abstract

The invention belongs to the field of semiconductor manufacturability design, aims at the technology of copper interconnection dummy metal filling, and in particular relates to a dummy comprehensive optimization method based on a CMP simulation model. The method of the present invention obtains the chip surface height profile after CMP polishing through full-chip CMP simulation, and obtains an effective hot spot area with a sharp change in height; iteratively performs step-by-step dummy filling and local area fast CMP simulation to gradually eliminate the effective hot spot area Hotspots; until no valid hotspots are determined through full-chip CMP simulation. Compared with the rule-based dummy synthesis method, the invention can ensure that the height deviation of the CMP-polished layout after dummy filling is within a given deviation threshold, and the amount of dummy filling is less. Experiments show that under the same filling amount, the average square error of the height profile obtained by the two dummy filling methods SMDF and FMF of the present invention is about 58% smaller on average than the density-driven dummy filling method, which has obvious advantages.

Description

A Dummy Synthesis Optimization Method Based on CMP Simulation Model

technical field

The invention belongs to the technology for copper interconnect dummy metal filling in the field of semiconductor manufacturability design, and in particular relates to a dummy comprehensive optimization method based on a CMP simulation model.

Background technique

The development of the integrated circuit industry is an important driving force to promote the progress of social informatization. As the integrated circuit manufacturing process enters the nanometer scale, the increasingly serious process deviation seriously affects the performance and yield of the chip. Manufacturing deviations in processes such as chemical mechanical polishing (CMP: Chemical Mechanical Planarization) and photolithography clearly show the dependence on layout graphics (Pattern Dependent). The CMP process will produce dishing (Disshing) and erosion (Erosion) defects on the surface of the silicon wafer [1][2]. On the one hand, it will affect the focus and imaging quality of the next photolithography process, which will cause the deviation of the lateral dimension of the interconnection line. The occurrence of dishing and erosion defects mainly depends on the density, line width and line spacing of the layout pattern.

Dummy fill is one of the important techniques to solve design-for-manufacturability problems related to layout patterns. Dummy filling adds units without electrical functions to the original design layout to change the density distribution of graphics on the layout, thereby improving the flatness of the chip surface after CMP polishing, as shown in Figure 1. The dummy unit can be a simple rectangle, or it can be a carefully designed pattern after considering chemical mechanical polishing, photolithography or other process factors [3][4][5]. According to different requirements for parasitic capacitance and circuit stability, the dummy unit can be connected to a fixed potential or floating [6]. Since dummy filling has a good improvement effect on processes such as chemical mechanical polishing and photolithography, and does not significantly increase process steps and manufacturing costs, it is widely used. Without affecting the circuit performance, how to add an appropriate amount of dummy elements to the appropriate position in the layout to reduce manufacturing deviation and improve chip yield has become a new generation of circuit design methods centered on improving manufacturability and yield. one of the key issues in learning.

The dummy filling process generally includes three basic steps: density analysis, dummy synthesis, and dummy assignment. First, the density analysis divides the chip layout into uniform grids (Tile) and windows (Window), counts the characteristic parameters such as the density and perimeter of the layout graphics in each grid, and calculates the blank area that can be used to fill dummy cells , called the filling margin (Slack); secondly, dummy synthesis calculates the number of dummy cells that should be filled in each grid according to different constraints and optimization objectives; finally, dummy assignment selects the appropriate dummy cells According to the number of dummy cells that should be inserted in each grid obtained by the synthesis of dummy cells, insert the dummy cells into the specific positions of the layout. Among them, the core of dummy filling technology is dummy synthesis.

There have been a lot of research work on dummy synthesis considering layout density and density gradient. Kahng[7] and Tian[8] respectively proposed a linear programming (LP: Linear Programming) method to minimize the density deviation and minimize the number of dummy insertions. The linear programming method can give the optimal solution to this problem, but its time complexity is O(n ³ ) where n is the number of variables, that is, the number of grids divided on the full-chip layout. For large-scale problems, linear programming methods are computationally expensive. In order to solve large-scale problems, some heuristic methods [9][10] have been developed based on the Monte-Carlo method and the greedy algorithm. The heuristic method has fast solution speed, but poor solution accuracy, which often leads to excessive dummy insertion. Literature [11] proposes an efficient algorithm for minimizing the number of dummy insertions based on CLP (Covering Linear Programming) and its fast approximation algorithm, which reduces the time complexity of the solution to O(n ² logn), and theoretically guarantee the solution accuracy. Considering the dummy filling of the density gradient, literature [12] proposed a dummy synthesis method for the density gradient, but this method imposes density gradient constraints on the grid, which greatly simplifies the dummy filling problem, but Part of the physical connotation is lost; literature [13] proposes a dummy synthesis method similar to the gradient constraint, which is similar to Lipchitz-like constraints, but still uses the traditional linear programming method to solve, and the calculation speed is slow; literature [14 ] proposed an iterative method based on covering linear programming (CLP) to solve the dummy synthesis problem with density gradient constraints, which achieved a good balance between the speed and effect of filling.

It can be seen that most of the existing dummy filling methods rely on rule-based dummy synthesis methods such as density and density gradient uniformity, but in fact, since CMP polishing is a complex physical and chemical process, CMP The surface morphology of the chip obtained after polishing is not only related to density, but also has a complex nonlinear relationship with various factors such as line width, line spacing, perimeter, and polishing fluid selection ratio [15][16]. Figure 2 shows an example of the density distribution of a test layout and the corresponding height distribution of the chip surface topography after CMP polishing. It can be seen from the figure that in the area with the same density, the perimeter will have a huge difference in the chip surface topography after CMP polishing.

Therefore, even if the dummy element filling method based on the density rule obtains the optimal solution, it cannot guarantee the smoothness of the surface topography of the chip after CMP polishing. With the reduction of manufacturing process nodes and the improvement of manufacturing requirements, especially after the manufacturing process enters the 45nm/32nm process node, the traditional density rule-based dummy filling strategy is facing great challenges, and the rule-based dummy filling method is no longer suitable for new technologies. According to the requirements of manufacturability design under the process node, the new dummy filling method needs to consider the influence of graphic feature parameters and process. The filling method based on accurate process simulation model is the future development direction of dummy filling technology[ 17].

In terms of dummy filling technology based on the process model, literature [18] proposes a dummy filling method that considers the Electro-Chemical Plating (ECP: Electro-Chemical Plating) model and the graph perimeter parameters. As a pre-process of CMP, the result of ECP will have a certain impact on the surface morphology of the chip after CMP polishing, but it cannot determine the final shape and flatness of the chip after CMP polishing, and the literature [18] has no direct application The result after CMP polishing is used as the optimization goal, but the traditional minimization of density deviation is still used as the optimization goal, so the flatness of the chip surface after CMP polishing cannot be guaranteed. Literature [19] and literature [20] respectively propose a dummy filling decision based on Design of Experiment (DoE: Design of Experiment). It designs a series of test patterns in the parameter space such as density and perimeter, and obtains the dummy filling method of different parameter areas according to the actual tape-out results, and extends it to the dummy filling of the whole chip. This method is not simply filling based on density rules, and has some characteristics of model-based dummy filling technology, but this method does not introduce an accurate full-chip CMP simulation model, lacks precise control of the number of dummy fillings, and the chip after filling Flatness is difficult to guarantee. At present, there is no technology to realize dummy filling by using the full-chip CMP simulation model.

In the copper interconnect CMP process, the ultimate goal of filling dummy elements is to use the least amount of dummy element filling to obtain the optimal flatness of the chip surface after CMP polishing. There is a “gap” between the traditional dummy filling method driven by density rules and the ultimate goal, that is, the uniform distribution of parameters such as density and density gradient does not necessarily lead to the conclusion that the surface morphology of the chip after CMP polishing is smooth. This dummy filling method based on density rules has two drawbacks: first, the effect of the final dummy filling cannot be guaranteed; second, in order to ensure the flatness of the chip surface, the filling constraints used are often too conservative, resulting in The quantity is substantially greater than actually necessary. The CMP simulation tool is a bridge connecting the chip layout and the chip surface topography. The present invention will propose a dummy filling synthesis method based on the CMP simulation model.

References relevant to the present invention are:

[1]B.Stine,D.Ouma and R.Divecha.A closed-form analytical model for ILDthickness variation in CMP processes.CMP Multilevel Interconnect Conference,1997,pp.266-273.

[2] T. Park, T. Tugbawa, D. Boning, J. Chung, R. Muralidhar, S. Hymes, Y. Gotkis, S. Amalgir, R. Walesa, L. Shumway, G. Wu, F. Zhang , R. Kistler, and J. Hawkins. Pattern and process dependencies in copper damascene chemical mechanical polishing processes. IEEE VLSI Multilevel Interconnect Conference, 1998, pp.437-442.

[3] L.He, A.B.Kahng, K.H.Tam, and J.Xiong. Variability-driven considerations in the design of integrated circuit global interconnects. International VLSI Multilevel Interconnection Conference, 2004, pp.214-221.

[4]M.M.Nelson.Optimized pattern fill process for improved CMP uniformity and interconnect capacitance.Univ./Government/Ind.Microelectronic Symposium,2003,pp.374–375.

[5]P.J.M.van Adrichem,D.L.Goinard.Method and apparatus for performing dummy-fill by using a set of dummy fill cells.United States Patent,Publication Number US2009/0089732A1,2009.

[6] B. E. Stine, D. S. Boning, J. E. Chung, L. Camilletti, F. Kruppa, E. R. Equi, W. Loh, S. Prasad, M. Muthukrishnan, D. Towery, M. Berman, and A. Kapoor. The physical and Electrical effects of metal-fill patterning practices for oxide chemical–mechanical polishing processes. IEEE Trans. Electron Devices, vol.45, no.3, pp.665-679, 1998.

[7] A.B.Kahng, G.Robins, A.Singh, and A.Zelikovsky.Filling algorithms and analyzes for layout density control.IEEE Transactions on Computer Aided Design,18(4):445-462,1999.

[8] R. Tian, D. F. Wong and R. Boone. Model-based dummy feature placement foroxide chemical mechanical polishing manufacturability. IEEE Design Automation Conference, 2000, pp.667-670.

[9]Y.Chen,A.B.Kahng,G.Robins,A.Zelikovsky.Monte-Carlo algorithms for layout density control.Asia and South Pacific Design Automation Conference,2000,pp.523-528.

[10] Y.Chen, A.B.Kahng, G.Robins, A.Zelikovsky. Practical iterated fillsynthesis for CMP uniformity. IEEE Design Automation Conference, 2000, pp.671-674.

[11] C.Feng, H.Zhou, C.Yan, J.Tao and X.Zeng. Provably Good and Practically Efficient Algorithms for CMP Dummy Fill. IEEED esign Automation Conference, 2009, pp.534-539.

[12] H.Y.Chen, S.J.Chou, and Y.W.Chang. Density gradient minimization with coupling-constrained dummy fill for CMP control. ACM/IEEE International Symposium on Physical Design, 2010, pp.105-111.

[13] Y.Chen and A.B.Kahng and G.Robins and A.Zelikovsky. Closing the smoothness and uniformity gap in area fill synthesis. IEEE/ACM International Symposium on Physical Design, 2002, pp.137-142.

[14]Peng Wu, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng. An Efficient Method for Gradient-Aware Dummy Fill Synthesis. Integration, the Journal of VLSI, 2012. (Accepted)

[15]B.Stine,D.Ouma and R.Divecha.A closed-form analytic model for ILDthickness variation in CMP processes.CMP Multilevel Interconnect Conference,1997,pp.266-273.

[16] T. Park, T. Tugbawa, D. Boning, J. Chung, R. Muralidhar, S. Hymes, Y. Gotkis, S. Amalgir, R. Walesa, L. Shumway, G. Wu, F. Zhang , R. Kistler, and J. Hawkins. Pattern and process dependencies in copper damascene chemical mechanical polishing processes. IEEE VLSI Multilevel Interconnect Conference, 1998, pp.437-442.

[17]A.B.Kahng.CMP Fill Synthesis:A Survey of Recent Studies.IEEE Transactions on Computer-Aided Design of Circuits and Systems,28(1):3-19,2008.

[18] N. Megiddo. On the complexity of linear programming, in Advance economic theory: Fifth world congress, T. Bewley, ed. Cambridge University Press, pp.225-268, 1987.

[19] T. Yoshida. Pattern and process dependencies in copper damascene chemical mechanical polishing processes. European Cetacean Society conference, 1999, pp.437-442.

[20] I.Nitta, Y.Kanazawa, D.Fukuda, T.Shibuya, N.Idani, M.Ito, O.Yamasaki, N.Harada, T.Hiramoto. "Condition-based" Dummy Fill Insertion Method Based on ECP and CMP Predictive Models. International Symposium on Quality Electronic Design, 2010, pp.198-204.

[21] H. Cai. Modeling of pattern dependencies of the fabrication of Multi-level copper metallization. PHD thesis, MIT, 2007.

[22]H.Melznera,N.Cui,S.Postnikov.Navigating in the Density Plane-Achieving Flat Wafer Surface and Uniform Metal Thickness in CMP Processes.Advanced Semiconductor Manufacturing Conference,2010,pp.189-195.

[23]T.Tugbawa.Chip-Scale Modeling of Pattern Dependencies in Copper Chemical Mechanical Polishing Processes.PHD thesis,Massachusetts Institute of Technology,2002.

Contents of the invention

In order to overcome the shortcomings of the traditional density-driven dummy filling method, the present invention proposes a dummy synthesis optimization method based on dual CMP simulation models, specifically involving two different levels of simulation models based on high-precision full-chip CMP simulation and local area fast CMP simulation The dummy synthesis method of , in particular, relates to a dummy filling strategy extracted from accurate CMP simulation models.

The flow chart of the dummy synthesis method based on the dual CMP simulation model proposed in this paper is shown in Figure 3. The process includes two different levels of simulation processes, high-precision full-chip CMP simulation and local area fast CMP simulation, as well as steps such as chip surface topography statistics and hot spot inspection.

Input parameters include the following four categories:

1. Layout parameters, including layout to be filled and layer number;

2. Grid parameters, including the number of full-chip grid divisions m×n, effective density influence distance r, and effective density weight function f _w ;

3. Dual CMP emulators, including high-precision full-chip CMP emulators, local area fast CMP emulators;

4. Control parameters, including chip surface height deviation threshold λ _tol , dummy incremental fill factor δ.

The model-based dummy synthesis process of the present invention is an iterative solution process, and the specific steps include:

Step 1: High-precision full-chip CMP simulation, using a full-chip CMP accurate simulator to simulate a specific layer in the layout to be filled to obtain the height profile after CMP polishing;

Step 2: Calculate the height profile of the full chip and calculate the effective hot spots;

Step 3: Determine whether there is a valid hot spot, if there is a valid hot spot, then jump to step 4; otherwise, the dummy synthesis process ends;

Step 4: Carry out step-by-step dummy filling to the grid of the effective hotspot area. The present invention proposes two filling strategies: (4-A) select the worst effective hotspot area for step-by-step dummy filling, (4-B ) to perform step-by-step dummy filling on all effective hotspot areas;

Step 5: Use the local area fast CMP simulator to perform local fast simulation on the filled effective hot spot area, and update the local surface height profile;

Step 6: In the local area, calculate the effective hot spot;

Step 7: In the local area, judge whether there is an effective hotspot, if there is a local effective hotspot, return to step 4; otherwise, return to step 1.

Specifically, the main solution steps of the method of the present invention include:

Step 1 High-precision full-chip CMP simulation

To realize the dummy filling process based on the CMP simulation model shown in Figure 3, a high-precision full-chip CMP simulator that meets the accuracy requirements should be selected. Literature [21] and Literature [22] proposed a full-chip CMP simulation model based on the DSH (Density-Step-Height) model and contact mechanics principles. The model first divides the surface of the chip into m×n grids, and uses the principle of contact mechanics to solve the actual pressure on each grid, and then distributes the pressure on the medium and copper interconnection lines in the grid, and finally according to the principle of tribology Calculate the removal of different materials and obtain the height topography of the chip surface. The model considers the physical mechanism of elastic contact in CMP polishing process, and has good simulation accuracy after being calibrated by experimental data. The present invention selects a full-chip CMP simulator independently developed by Fudan University based on a contact mechanics model to carry out full-chip accurate simulation. In fact, the present invention does not need to limit the principle and manufacturer of the full-chip CMP simulator, and any full-chip CMP simulator that has been verified by silicon chip data and whose simulation accuracy meets the requirements of the chip manufacturer can be selected. After full-chip accurate CMP simulation, the height h(i, j) of each grid on the chip can be obtained, 1≤i≤m, 1≤j≤n.

Step 2 Full chip morphology statistics and effective hot spot calculation

First, calculate the average height h _mean within the entire chip, and the calculation formula is:

Then, the deviation between the height of each grid and the average height is calculated within the whole chip as:

According to the actual process requirements of the chip manufacturing plant, given a height deviation threshold λ _tol (such as 30%), the grid points with |λ(i,j)|>λ _tol are defined as height deviation hotspots. In particular, hotspots with λ(i,j)>λ _tol are called positive bias hotspots, and hot spots with λ(i,j)<-λ _tol are called negative bias hotspots.

The grid density D _t (i, j) is defined as the ratio of the total area of all graphics in the grid to the grid area, that is:

Among them, S _g is the area of the geometric figure g in the grid T _i,j , S _T is the area of the grid T _i,j , and i,j are the indexes of the row and column of the grid T _i,j on the chip, respectively , the elements in matrix D _t (i,j) are the density of grid T _i,j .

The effective density ρ(i,j) of the grid is defined as:

Among them, f _w is the effective density weight function of the surrounding grids to the grid (i, j), and r is the effective density influence distance.

Then the average effective density of positive deviation hotspots can be calculated separately and the average effective density of negative bias hotspots They are:

Among them, N ₊ is the number of positive deviation hotspot grids, and N _- is the number of negative deviation hotspot grids.

Under a specific process, the surface height topography of the chip after CMP polishing usually has a monotonous variation trend with the effective density. Figure 4 shows the change trend of a chip manufacturer under the 65nm process. It can be seen that as the effective density increases, the height profile of the chip surface after polishing will decrease, and the corresponding reduction rate of graphics with different line widths and line spacings different. Generally speaking, the reason for this change is that the polishing fluid (slurry) has different selection ratios for different materials during the polishing process. For example: if the polishing rate of a certain polishing liquid on the medium is low and the polishing rate on copper is high, the chip height profile will show a downward trend with the increase of the copper wire density; if the selectivity ratio of the polishing liquid to the material is opposite, the shape height The trend of change is also opposite.

Therefore, in order to determine how to correct for altitude bias hotspots, define the hotspots that should be filled as:

(1) If Then define the negative deviation hot spot as the hot spot that should be filled;

(2) If Then define a positive deviation hotspot as a hotspot that should be filled.

Since dummy filling can only fill grids with a filling margin greater than zero, the hotspots that should be filled with a filling margin greater than zero are defined as valid hotspots. Dummy padding can only be done on meshes with active hotspots.

Step 3: In the scope of the whole chip, determine whether there is an effective hot spot

In the scope of the whole chip, judge whether there is a valid hot spot, if there is a valid hot spot, then jump to step 4; otherwise, the dummy synthesis process ends;

Step 4 Perform step-by-step dummy filling on the effective hotspot grid

In the present invention, two step-by-step dummy filling strategies are proposed. Step 4-A only performs step-by-step dummy filling on the worst effective hotspot grid each time, and step 4-B performs one-time filling on all effective hotspot grids. Stepped dummy padding.

Step 4-A Step-by-step dummy filling of the worst effective hotspot grid

In each iteration, only the effective hotspot grid with the largest |λ(i,j)| is found, and the stepwise dummy filling is performed. The filling amount of a step-by-step filling is:

Δδ(i,j)=δ·s(i,j) (6)

Among them, δ is the incremental filling coefficient, and s(i,j) is the filling margin of the effective hotspot grid.

Step 4-B Stepwise dummy filling of all valid hotspot grids

If the control of the dummy filling amount is not very strict during the dummy synthesis process, an appropriate relaxation method can be used to speed up the filling speed, that is, step-by-step filling is performed on all effective hotspot grids at one time, and the step-by-step dummy filling The filling amount is still determined by formula (6). Step-by-step filling of all effective hotspot grids can greatly reduce the number of calls to the local fast CMP simulation algorithm and greatly increase the speed of dummy synthesis.

Step 5 Local fast CMP simulation

In the full-chip accurate CMP simulator based on the contact mechanics model, the heights of all grids are solved by coupling, that is, to obtain the height h(i, j) of a certain grid, it is necessary to use the layout information of all grids including line Calculate the width, line spacing and density, use the contact mechanics model to solve the actual pressure on each grid, and then distribute the pressure on the medium and copper interconnection lines in the grid, and finally calculate the removal amount of material according to the principle of tribology to get High profile, the amount of calculation is very huge.

In order to balance the calculation efficiency and calculation accuracy, the DSH model is more suitable for the CMP simulation model of local dummy filling [23]. The DSH model does not use complex mathematical methods to solve the pressure distribution problem of the chip-polishing pad elastic contact, but introduces the effective density for fast calculation. The calculation formula of the effective density is shown in formula (4). Effective Density simplifies CMP simulation into a direct mapping process from local pattern features to local height topography with fast computation speed. The formula for calculating grid height is:

h(i,j)= _fDSH (W(i,j),S(i,j),ρ(i,j)), (7)

Among them, f _DSH represents the simulation function of the DSH model, W(i,j) is the average line width, and S(i,j) is the average line spacing, and their definitions are consistent with those in the literature [23].

The DSH model uses "step height" to examine the local bending effect of the polishing pad. The DSH model believes that for an interconnect groove, the polishing pressure is distributed to the upper and lower surfaces of the groove, and the polishing pressure at the bottom is smaller than the polishing pressure at the top, as shown in Figure 5(a). The final surface morphology of the chip plays a decisive role. At the same time, the “rounding effect” is used in the DSH model to describe the fact that the contact pressure at the protruding corners is higher. The rounding effect leads to a higher polishing rate on the upper surface of the groove, as shown in Figure 5(b). f All model parameters in the _DSH function need to be obtained by fitting silicon data. For details of the specific DSH model, please refer to literature [23].

The invention adopts the DSH model to carry out local CMP simulation, and updates the height of the effective hotspot area after the step-by-step dummy elements are filled.

Step 6 local effective hotspot detection

Use the formula (2) to update the height profile deviation at the effective hotspot. If the hotspot grid still belongs to the effective hotspot, it means that the hotspot is still not eliminated, and dummy filling needs to be continued; otherwise, it means that the hotspot has been eliminated.

Step 7: In a local area, determine whether there is an effective hotspot

In the local area, judge whether there is an effective hotspot, if there is a local effective hotspot, return to step 4; otherwise, return to step 1.

The advantage of the inventive method has:

1. The traditional dummy filling method based on density rules cannot guarantee the flatness of the chip surface after final CMP polishing even if the optimal solution is obtained. However, the dummy filling method based on the CMP simulation model proposed by the method of the present invention uses an accurate CMP simulator, which can ensure that the chip surface height difference of the dummy filled layout is within a given error range after CMP polishing.

2. In order to ensure the filling effect in the traditional dummy filling method, the filling constraints are often too conservative, and the number of dummy insertions is generally more than actually required. However, the method of the present invention controls dummy filling directly according to the topography height of the chip, so the total filling amount is generally less than that of the traditional rule-based dummy filling method.

Description of drawings

Figure 1 Example of dummy filling process.

Figure 2(a) layout density distribution.

Fig. 2(b) Chip surface height distribution after CMP polishing.

Figure 3 is a flow chart of dummy synthesis based on the CMP simulation model.

Figure 4 shows the change trend of the chip height profile with the effective density after CMP polishing under the 65nm process.

Figure 5(a) Schematic diagram of the step effect.

Figure 5(b) Schematic diagram of rounded corner effect.

Figure 6. Comparison of different dummy filling methods in terms of filling amount and filling effect.

Fig. 7 Comparison of CPU time of different dummy filling methods on dummy filling problems of different sizes.

detailed description

In order to make the above features and advantages of the present invention more obvious and comprehensible, the present invention will be further described below through some specific examples.

Embodiment 1 Comparison between the method of the present invention and the traditional rule-based dummy synthesis method on the CMP height topography results

The purpose of introducing CMP model simulation in the dummy filling process is to obtain a smoother chip surface after CMP polishing the filled layout. We use a full-chip CMP simulator to simulate the layout obtained by different dummy filling methods, calculate the mean square error of the chip surface height profile, and use this value to measure the filling quality of different dummy filling methods. The smaller the mean square error, the better the flatness of the chip surface, and the better the effect of dummy filling. The formula for calculating the mean square error is:

Among them, h _mean has the same definition as formula (1).

In order to compare the filling effects of different dummy filling methods under the same filling amount, we changed the height deviation threshold from 30% to 60%. Figure 6 shows the results of the normalized filling amount and height profile mean square error of different filling methods, where Min-Fill LP refers to the dummy synthesis method based on the density rule and adopts the linear programming algorithm, and SMDF is the worst effective hot spot A step-by-step dummy filling method (that is, the 4-A method), and Fast fill (FMF) is a step-by-step dummy filling method (that is, the 4-B method) for all effective hot spots. Figure 6 shows that under the same filling amount, the average square error of the height profile of the SMDF and FMF methods is about 58% smaller on average than the density-driven linear programming method, showing that the two filling methods based on the CMP simulation model proposed by the present invention have obvious advantage. In addition, it can be seen from Figure 6 that under the same filling amount, the filling effects of the FMF method and the SMDF method are roughly the same.

Embodiment 2 The comparison between the method of the present invention and the traditional rule-based dummy synthesis method on CPU computing time

In this embodiment, different dummy filling methods are tested on problems of different scales. Fig. 7 shows the execution time of 3 different filling methods. It can be seen from the figure that the linear programming method is the fastest for solving small-scale problems, but because its time complexity is O(n ³ ), the time increases rapidly. The two dummy filling methods based on the CMP model simulation need to call the CMP simulator repeatedly, and the time overhead is large, but the important thing is that they are not sensitive to the problem scale. The experimental data shows that the time complexity is about O(n), so In large-scale problems, it is much faster than the density-driven linear programming method.

Comparing the two model-based dummy filling methods, the FMF method is about 6 times faster than SMDF. Considering the experimental conclusion that the mean square error of the height profile is roughly the same, the FMF method is an ideal filling method.

Embodiment 3 Comparison between the method of the present invention and the traditional rule-based dummy element synthesis method after filling the layout graphic features

In order to further analyze the difference in filling effect between the dummy filling method based on CMP model simulation and the dummy filling method driven by density rules, Table 1 counts the graphic features of the layout obtained by different dummy filling methods. In Table 1, three The number of dummy insertions of the two methods is basically the same.

Table 1 The density distribution characteristics of the results of different dummy filling methods

As can be seen from Table 1, the minimum window density after filling (0.26) of the density rule-driven method is much higher than that of the two model-based dummy filling methods (0.187 and 0.193, respectively). In fact, this value is the lower bound of the window density. The density rule-driven method forcibly raises the lower bound of the window density to a higher position. In fact, unnecessary overfilling is performed on the part of the window with a lower density but whose final shape deviation does not exceed the deviation threshold, resulting in the overall Increase in the amount of dummy padding.

Based on the experimental results of the above examples, it can be seen that the key advantage of the dummy filling method based on the CMP simulation model is that it directly uses the chip surface morphology after CMP polishing as the optimization basis to ensure the final effect of the dummy filling, and can effectively Reduce the amount of unnecessary dummy padding.

Claims (7)

1. a kind of dummy comprehensive optimization method based on CMP emulation model, it is characterized in that, described method is based on full-chip CMP accurate emulator and local fast CMP emulator to carry out the iterative solution process of dummy filling, and its step comprises: Step 1: High-precision full-chip CMP simulation, using a full-chip CMP accurate simulator to simulate a specific layer in the layout to be filled to obtain the height profile after CMP polishing; Step 2: Count the height profile of the whole chip and calculate the effective hot spot; where, the calculation method of the full chip profile statistics and effective hot spot is: First, count the average height h _mean within the current full-chip range, and the calculation formula is: ${\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; a</span>}\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; \&times;</span>\mathrm{<span\; class="notranslate">\; no</span>}}\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\overset{\mathrm{<span\; class="notranslate">\; m</span>}}{<span\; class="notranslate">\; \&Sigma;</span>}}\underset{\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\overset{\mathrm{<span\; class="notranslate">\; no</span>}}{<span\; class="notranslate">\; \&Sigma;</span>}}\mathrm{<span\; class="notranslate">\; h</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$ Among them, m and n are the number of grids that the chip is divided into horizontally and vertically, respectively; Then, calculate the deviation of the height of each grid in the whole chip range from the average height as: $\mathrm{<span\; class="notranslate">\; \&lambda;</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; h</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; a</span>}\mathrm{<span\; class="notranslate">\; no</span>}}}{{\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; a</span>}\mathrm{<span\; class="notranslate">\; no</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$ Given a height deviation threshold λ _tol according to the actual process requirements of the chip factory, the grid points with |λ(i,j)|＞λ _tol are defined as height deviation hotspots; the hot spots with λ(i,j)＞λ _tol It is called a positive deviation hotspot, and the hot spot of λ(i,j)<-λ _tol is called a negative deviation hotspot; The grid density D _t (i, j) is defined as the ratio of the total area of all graphics in the grid to the grid area, that is: ${\mathrm{<span\; class="notranslate">\; D.</span>}}_{\mathrm{<span\; class="notranslate">\; t</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; S</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}}\underset{\mathrm{<span\; class="notranslate">\; g</span>}<span\; class="notranslate">\; \&Element;</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; j</span>}}}{<span\; class="notranslate">\; \&Sigma;</span>}{\mathrm{<span\; class="notranslate">\; S</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}}<span\; class="notranslate">\; ,</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$ Among them, S _g is the area of the geometric figure g in the grid T _i,j , S _T is the area of the grid T _i,j , and i,j are the indexes of the row and column of the grid T _i,j on the chip, respectively , the elements in matrix D _t (i,j) are the density of grid T _i,j ; The effective density ρ(i,j) of the grid is defined as: $\mathrm{<span\; class="notranslate">\; \&rho;</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\underset{\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; r</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 2</span>}}{\overset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; r</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; \&Sigma;</span>}}\underset{\mathrm{<span\; class="notranslate">\; l</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; r</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 2</span>}}{\overset{\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; r</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; \&Sigma;</span>}}<span\; class="notranslate">\; \&lsqb;</span>{\mathrm{<span\; class="notranslate">\; D.</span>}}_{\mathrm{<span\; class="notranslate">\; t</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; l</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; f</span>}}_{\mathrm{<span\; class="notranslate">\; w</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; l</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&rsqb;</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$ Among them, f _w is the effective density weight of the surrounding grid to the grid (i, j), and r is the effective density influence distance; Then the average effective density of positively biased hotspot grids can be calculated separately and the average effective density of the negative bias hotspot grid They are: $\left\{\begin{array}{c}{\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\mathrm{<span\; class="notranslate">\; \&rho;</span>}}}_{<span\; class="notranslate">\; +</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; N</span>}}_{<span\; class="notranslate">\; +</span>}}\underset{\mathrm{<span\; class="notranslate">\; \&lambda;</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ></span>{\mathrm{<span\; class="notranslate">\; \&lambda;</span>}}_{\mathrm{<span\; class="notranslate">\; t</span>}\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; l</span>}}}{<span\; class="notranslate">\; \&Sigma;</span>}\mathrm{<span\; class="notranslate">\; \&rho;</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; )</span>\\ {\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\mathrm{<span\; class="notranslate">\; \&rho;</span>}}}_{<span\; class="notranslate">\; -</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; N</span>}}_{<span\; class="notranslate">\; -</span>}}\underset{\mathrm{<span\; class="notranslate">\; \&lambda;</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ></span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; \&lambda;</span>}}_{\mathrm{<span\; class="notranslate">\; t</span>}\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; l</span>}}}{<span\; class="notranslate">\; \&Sigma;</span>}\mathrm{<span\; class="notranslate">\; \&rho;</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; )</span>\end{array}\right.<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$ Among them, N ₊ is the number of positive deviation hotspot grids, and N- is the number of negative deviation hotspot grids; Hotspots should be populated defined as: (1) If Then define the negative deviation hot spot as the hot spot that should be filled; (2) If Then define the positive deviation hot spot as the hot spot that should be filled; Finally, define the hotspots that should be filled with a filling margin greater than zero as valid hotspots; Step 3: Determine whether there is a valid hot spot, if there is a valid hot spot, then jump to step 4; otherwise, the dummy synthesis process ends; Step 4: Carry out step-by-step dummy filling to the grid of the effective hotspot area, and propose two filling strategies: (4-A) select the worst effective hotspot area for step-by-step dummy filling; All effective hotspot areas are filled with step-by-step dummy elements; Step 5: Use the local area fast CMP simulator to perform local fast simulation on the filled effective hot spot area, and update the local surface height profile; Step 6: In the local area, calculate the effective hot spot; Step 7: In the local area, judge whether there is an effective hotspot, if there is a local effective hotspot, return to step 4; otherwise, return to step 1. 2. by the described method of claim 1, it is characterized in that, in described step 1, do not need to limit the principle and the manufacturer of full-chip CMP accurate emulator, can select any one through silicon chip data verification and emulation A full-chip CMP simulator whose accuracy meets the requirements of chip manufacturers, and simulates the height of each grid on the chip. 3. by the method for claim 1, it is characterized in that, in described step 4, two kinds of dummy element filling methods are proposed: carry out stepwise dummy element filling method (SMDF) to the worst effective hotspot grid, A stepwise dummy fill method (FMF) is performed on all valid hotspot meshes. 4. The method according to claim 3, characterized in that, in the step-by-step dummy filling method to the worst effective hotspot grid, in each iteration, only find |λ(i, j )|The largest effective hotspot grid for step-by-step dummy filling; the filling amount of a step-by-step filling is: Δδ(i, j) = δ·s(i, j) (6) Among them, δ is the incremental filling coefficient, and s(i,j) is the filling margin of the effective hotspot grid. 5. The method according to claim 4, characterized in that, in the step-by-step dummy filling method for all effective hotspot grids, appropriate slack control is adopted to speed up the execution speed of the filling process, and one-time All effective hotspot grids are filled step by step, and the filling amount of stepwise dummy filling is still determined by formula (6). 6. by the described method of claim 1, it is characterized in that, in described step 5, local fast CMP emulation adopts DSH model; DSH model does not adopt the pressure distribution problem of solving chip-polishing pad elastic contact by complicated mathematical method, The effective density is introduced for fast calculation, which simplifies the CMP simulation into a mapping process from local graphic features to local height topography, and the calculation speed is fast; The formula for calculating grid height is: h(i,j)= _fDSH (W(i,j),S(i,j),ρ(i,j)), (7) Among them, f _DSH represents the simulation function of the DSH model, W(i,j) is the average line width, S(i,j) is the average line spacing, ρ(i,j) is the effective density, and its calculation is as formula (4) shown. 7. The method according to claim 1, characterized in that, in the step 6, the local hotspot detection method is to utilize the formula (2) to update the height profile deviation at the hotspot grid, if the hotspot grid still belongs to If the hot spot is valid, it means that the hot spot is still not eliminated, and the dummy filling needs to be continued; otherwise, it means that the hot spot has been eliminated.