CN103533045B - A kind of method fault-tolerant for PCIE data link layer high-performance - Google Patents
A kind of method fault-tolerant for PCIE data link layer high-performance Download PDFInfo
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Abstract
The present invention relates to a kind of method fault-tolerant for PCIE data link layer high-performance, on the basis of the original CRC error detections of PCIE, error detection and correction is added（ECC, Error Checking and Correcting）Code real-time error and self-repair function, it can be corrected while detecting wrong, and calculating speed is quickly.The wrong bag that the present invention can correct avoids the need for retransmitting, and increases the fault-tolerance of link, while can save bandwidth and time, improves the efficiency of link transmission.
Description
Technical field
The present invention relates to a kind of method fault-tolerant for PCIE data link layer high-performance.
Background technology
PCIE is for interconnecting the third generation high-performance I/O buses such as calculated with communications platform application peripheral devices.
Data link layer is located at the intermediate layer of PCIE master control cores, major function be link management and ensure the transmission of data reliability and
Integrality.Data link layer ensures the integrality and uniformity of data transmission using fault-tolerant and retransmission mechanism.PCIE data at present
The fault-tolerance of link layer is very low, can only error detection, it is impossible to error correction.Learnt according to current PCIE present Research, in order to reduce data
The bit error rate transmitted in data link, PCIE carry out error detection with cyclic redundancy check (CRC), and CRC is a kind of in data communication
In widely used error control coding, there is stronger error detecing capability.Inspections of the CRC in data link layer is described in detail below
Miss journey.
The transmitting terminal of data link layer receives the data TLP from transaction layer, before TLP is sent, is first sealed TLP
Dress, plus sequence number prefix and CRC suffix, CRC suffix is according to the content of TLP packets, with the verification of CRC algorithm generation
Code.Packaged TLP copies are stored in retransmission buffer, while the TLP is sent.The receiving terminal of data link layer
TLP is received from physical layer, sequence number prefix and CRC suffix are now contained in the TLP, after receiving TLP, according to TLP packets
In data in addition to crc field, with the same CRC algorithm of transmitting terminal, expectation crc value is calculated, it would be desirable to crc value with
The CRC that TLP is carried is compared, if matching, illustrates that CRC check is correct, continue other inspections.If mismatch, CRC
Check errors, illustrate link error occurs in data transmission procedure, then reply NAK data link layer packets to transmitting terminal
（DLLP）, transmitting terminal can all carry out repeating transmission operation, to ensure each TLP numbers to whole TLP corresponding to the NAK DLLP that receive
It can be transmitted according to bag correct.
The existing fault-toleranr technique of PCIE data link layers only check that the mistake that data occur during link transmission,
But it can not be corrected.Simultaneously as being unable to error correction, all packets that link transmission mistake occurs will be retransmitted, and not only increase
The burden of link transmission is added, has also reduced the efficiency of data transfer, cause bandwidth and waste of time.
The content of the invention
It is an object of the invention to overcome above-mentioned deficiency, there is provided a kind of side fault-tolerant for PCIE data link layer high-performance
Method, by increasing capacitance it is possible to increase the fault-tolerance of link, while bandwidth and time can be saved, improve the efficiency of link transmission.
The object of the present invention is achieved like this：A kind of method fault-tolerant for PCIE data link layer high-performance,
On the basis of the original CRC error detections of PCIE, ECC real-time errors and self-repair function are added, can be to it while detecting wrong
Corrected, and calculating speed is quickly.
Its further technical scheme is：Comprise the following steps that：
1）ECC coding circuits are added in data link layer transmitting terminal, coding circuit is responsible for coding, generation TLP packets
Initial ECC check code；
2）ECC decoding circuits are added in receiving terminal circuit structure, decoding circuit is responsible for generating new ECC check code, and
Initial ECC check code entrained by new ECC check code and data is subjected to XOR EDC error detection and correction；
3）When decoding circuit detects that mistake can not still correct (the error correction scope for exceeding encryption algorithm) to it, can give birth to
Id signal occurs into a mistake, to show to have not repairable mistake to produce, then according to ACK/NAK agreements to that can not correct
Wrong bag retransmitted；
4）After data link layer transmitting terminal receives the TLP packets from transaction layer, it is packaged according to protocol contents,
In existing fault-toleranr technique（Add CRC redundant cyclic check codes）On the basis of, the present invention generates ECC check by ECC coding circuits
Code, waits complete TLP that ECC check code is added in the bag tail of packet after receiving；
5）In the receiving terminal of data link layer, the TLP data from physical layer are received, the TLP packets received are carried out
Error detection, CRC check is first carried out, if CRC check is errorless, illustrate no link transmission mistake, then need not carry out ECC error correction.If
CRC check mistake, then carry out ECC error correction.Currently used ECC codings are Hamming codes, can be one with error correction, error detection 2, if having
Multi-bit error is, not repairable, then provides error identification signal, to notify transmitting terminal to retransmit the TLP of error.
The ECC check error correction is to be based on Hamming decoding method, and the data block of every 512 byte will generate 3 byte longs
The ECC check code of degree.
Compared with prior art, the beneficial effects of the invention are as follows：
The present invention improves the fault freedom of PCIE data link, can realize error correction, by existing data
On the basis of the fault-toleranr technique of link, ECC real-time errors and self-repair function are added so that originally can only error detection, it is impossible to error correction
Tolerant system, error correction can be realized, so as to strengthen the fault-tolerance of link.
Brief description of the drawings
Fig. 1 is data link layer ECC fault-toleranr technique frame diagrams of the present invention.
Fig. 2 is the ECC coding circuits of data link layer transmitting terminal of the present invention.
Fig. 3 is ECC parity information generation table of the present invention.
Fig. 4 is the ECC decoding circuits of data link layer receiving terminal of the present invention.
Fig. 5 is ECC check flow chart of the present invention.
Embodiment
A kind of method fault-tolerant for PCIE data link layer high-performance of the present invention, the described method comprises the following steps：
1）ECC coding circuits are added in data link layer transmitting terminal, coding circuit is responsible for coding, generation TLP packets
Initial ECC check code.ECC decoding circuits are added in receiving terminal circuit structure, decoding circuit is responsible for generating new ECC check
Code, and the initial ECC check code entrained by new ECC check code and data is subjected to XOR EDC error detection and correction.When decoding electricity
When road detects mistake but (the error correction scope for exceeding encryption algorithm) can not be corrected to it, a mistake can be generated and identified
Signal, to show to have not repairable mistake to produce, then not repairable wrong bag is retransmitted according to ACK/NAK agreements.Side
Case overall framework figure is shown in accompanying drawing 1；
2）ECC coding circuits are added in transmitting terminal, generate ECC check code.The master of the ECC coding circuit modules of input data
It is to carry out ECC codings to data before data are sent to physical layer to act on, and the ECC error correcting codes of generation are added into TLP
In packet.TLP data packet lengths from transaction layer are indefinite, and in units of double word, minimum length is 4 double words.From affairs
The TLP that layer receives is cached in FIFO, not only will be according in agreement after a complete TLP packet receives
It is defined to add sequence number and CRC check code in TLP, also ECC check is added in TLP bag tail to the further encapsulation of TLP
Code, ECC check code are that ECC coding circuits can generate according to fixed algorithm.By in packaged TLP copies deposit retransmission buffer
In case retransmitted when needing.First determined whether before packaged TLP is sent, upper one either with or without the correspondence received from opposite end
The retransmission flag signal of TLP packets, if it is not, packaged TLP can be sent to lower floor, if necessary to retransmit,
Then prevent to continue to the TLP from transaction layer, and preferentially retransmit.Idiographic flow is shown in such as accompanying drawing 2：
ECC codings use Hamming error correction technology in the present invention.Hamming volume is carried out exemplified by 512 byte datas below
Code, generate the Error correction and detection of 3 bytes.
2a) the generation of ECC check codes：ECC check algorithm is to be based on Hamming decoding method used by this programme,
The data block of every 512 byte will generate the ECC check code of 3 byte lengths.The initial data of 512 bytes forms a size
512x8 matrix.Initial data is carried out calculating by row in units of byte and produces row check code, is carried out by row in units of position
Calculate and produce row check code.Its constituent is the row parity check code and the row parity check code of 18 of 6.ECC check code
Generation as shown in Figure 3：Wherein P1~P4 is row parity check code, and P8~P2048 is row parity check code.
P1 = Bit7⊕Bit5⊕Bit3⊕Bit1
P1’ = Bit6⊕Bit4⊕Bit2⊕Bit0
P2 = Bit7⊕Bit6⊕Bit3⊕Bit2
P2’ = Bit5⊕Bit4⊕Bit1⊕Bit0
P4 = Bit7⊕Bit6⊕Bit5⊕Bit4
P4’ = Bit3⊕Bit2⊕Bit1⊕Bit0
P8 = 512th byte⊕510th byte…4th byte⊕2nd byte
P8’ = 511th byte⊕509th byte…3rd byte⊕1st byte
………………
P2048 = 512th byte⊕511th byte…258th byte⊕257th byte
P2048’ = 256th byte⊕255th byte…2nd byte⊕1st byte
Wherein, Bit0~Bit7 is the XOR value of all data of the row, and 1st byte~512th byte are that the row owns
The XOR value of data.
2b）The distribution of ECC code：The distribution of ECC check code is as shown in table 1, and wherein p1 ~ p4 is row check code, p8 ~ p1024
For row check code.
Table 1：The allocation table of ECC check code
Errant bit locations determine：Error Offset=P1024, P512, P256, P128, P64, P32, P16, P8,
P4, P2, P1 }.Wherein { P1024, P512, P256, P128, P64, P32, P16, P8 } is used for the byte location for determining mistake,
{ P4, P2, P1 } is used for the bit position for determining mistake.
3）After data link layer receiving terminal receives TLP from physical layer, according to beginning and end mark is unwrapped, to TLP data
Bag is parsed, and the entrained initial ECC check code of TLP bags, while ECC decoder modules is parsed, with same with transmitting terminal
ECC encryption algorithms, generate new ECC check code.Then initial ECC check code is carried out with newly-generated ECC check code different
Or, judged whether according to the result of XOR wrong, and whether can correct.If inerrancy or the mistake that can be corrected
By mistake, then ACK DLLP packets are replied to opposite end using the TLP packets as correct processing data packets；If it can not entangle
Positive mistake, then error flag signal can be produced, NACK DLLP packets are replied to opposite end, inform that transmitting terminal is retransmitted and is somebody's turn to do
TLP packets corresponding to NACK DLLP.Detailed process is shown in accompanying drawing 4.
4）ECC check code error-detection error-correction is to be compared initial ECC check code and newly-generated ECC check code, is judged
Whether data malfunction in transmitting procedure.The ECC check code generated twice is subjected to step-by-step XOR, thereby determines that out error
The byte offsets and position offset of position, notice correction module carries out negating error correction after carrying out the definition of error bit.
5) ECC check code error-detection error-correction flow is will to send end data to generate initial ECC check by ECC coding circuits
Code, data link layer receiving terminal, the decoding circuit identical encryption algorithm of receiving terminal are sent to data by link together
New ECC check code is generated, initial ECC check code and newly-generated ECC check code are then subjected to XOR, according to the knot of XOR
Whether fruit is 0, is judged whether wrong.If XOR result total data position is 0, illustrate no mistake；If XOR knot
It is 1 to have in general data bit in fruit, illustrates only a data mistake, can correct；If not both the above situation, then say
Bright data are wrong and beyond ECC error correction scope, can produce mistake and contract for fixed output quotas raw mark, and notice transmitting terminal carries out weight to the packet
Hair.ECC check code error-detection error-correction flow chart is as shown in Figure 5.
ECC error-detection error-correction processes are illustrated by taking 512 bytes as an example.
ECC check ECC schools newly-generated when being using the ECC check code and read block that are stored in redundant storage space
A yard step-by-step XOR is tested, whether is malfunctioned according to the result of XOR judging data block and carries out error correction.If XOR result is：
A) 24 data are all 0 and represent that the data block does not malfunction.
B) there are 12 data to represent that the data block has 1 data to make a mistake for 1, and XOR result can be utilized
Correct the mistake.
C) only a data is that 1 ECC check code for representing the data block is wrong.
D) three cases above is removed, then it represents that an error has occurred for the data block, and the data bits to make a mistake is big
In 1, mistake at this can not be corrected using XOR result.
The present invention is the fault-toleranr technique in existing data link（It is fault-tolerant by CRC CRCs, can only error detection,
It is unable to error correction）On the basis of, ECC real-time errors and self-repair function are added, to improve the fault-tolerance of data link layer, is improved simultaneously
Data transmission efficiency.
Above-described is only the preferred embodiment of the present invention, and the invention is not restricted to above example.It is appreciated that this
Other improvement and become that art personnel directly export or associated without departing from the spirit and concept in the present invention
Change, be considered as being included within protection scope of the present invention.
Claims (2)
- A kind of 1. method fault-tolerant for PCIE data link layer high-performance, it is characterised in that：In the original CRC error detections bases of PCIE On plinth, ECC real-time errors and self-repair function are added, it can be corrected while detecting wrong, and improve meter Speed is calculated, is comprised the following steps that：1）ECC coding circuits are added in the transmitting terminal of data link layer, ECC coding circuits are responsible for coding, generate TLP packets Initial ECC check code；2）ECC decoding circuits are added in the receiving terminal circuit structure of above-mentioned data link layer, it is new that ECC decoding circuits are responsible for generation ECC check code, and new ECC check code and the initial ECC check code entrained by data are subjected to XOR EDC error detection and correction；3）When ECC decoding circuits detect that mistake can not still correct to it, a mistake can be generated id signal occurs, with Show to have not repairable mistake to produce, then not repairable wrong bag is retransmitted according to ACK/NAK agreements；4）After the transmitting terminal of data link layer receives the TLP packets from transaction layer, it is packaged according to protocol contents, On the basis of existing fault-toleranr technique, ECC check code is generated by ECC coding circuits, wait complete TLP receive after by ECC schools Test the bag tail that code is added in packet；5）The TLP packets from physical layer are received in the receiving terminal of data link layer, the TLP packets received are examined Mistake, CRC check is first carried out, if CRC check is errorless, illustrate no link transmission mistake, then need not carry out ECC error correction, if CRC check mistake, then carry out ECC error correction.
- A kind of 2. method fault-tolerant for PCIE data link layer high-performance according to claim 1, it is characterised in that：It is described ECC check error correction is to be based on Hamming decoding method, and the data block of every 512 byte will generate the ECC check of 3 byte lengths Code.
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| CN103763067B (en) * | 2014-01-28 | 2017-11-10 | 天地融科技股份有限公司 | A kind of communication data packet error checking and correction method and apparatus |
| CN105045526A (en) * | 2015-05-08 | 2015-11-11 | 湖南国科微电子有限公司 | Method for improving transmission reliability of PCIe solid-state disk |
| CN105205021B (en) * | 2015-09-11 | 2018-02-13 | 华为技术有限公司 | Disconnect the method and apparatus linked between PCIe device and main frame |
| CN105280239B (en) * | 2015-10-22 | 2016-09-07 | 湖南国科微电子股份有限公司 | A kind of method and apparatus of dynamic implement solid state hard disc ECC check code |
| US9965352B2 (en) * | 2015-11-20 | 2018-05-08 | Qualcomm Incorporated | Separate link and array error correction in a memory system |
| CN108108264A (en) * | 2017-12-25 | 2018-06-01 | 郑州朗睿科技有限公司 | A kind of verification error correction method of serial communication |
| CN108988990A (en) * | 2018-07-05 | 2018-12-11 | 郑州云海信息技术有限公司 | A method of processing link layer data mistake |
| CN109376028B (en) * | 2018-09-27 | 2021-11-09 | 郑州云海信息技术有限公司 | Error correction method and device for PCIE (peripheral component interface express) equipment |
| CN110995392B (en) * | 2019-11-28 | 2022-08-02 | 上海集成电路研发中心有限公司 | A data transmission method and device |
| CN111541519B (en) * | 2020-04-17 | 2023-01-17 | 展讯通信（上海）有限公司 | Communication device |
| CN112511276B (en) * | 2020-11-24 | 2021-11-30 | 广州技象科技有限公司 | Data processing method and device |
| CN114598418A (en) * | 2020-12-07 | 2022-06-07 | 山东新松工业软件研究院股份有限公司 | Method, device and system applied to encoder data transmission |
| CN113489570B (en) * | 2021-06-30 | 2023-05-09 | 郑州云海信息技术有限公司 | A data transmission method, device and equipment for a PCIe link |
| CN117573455B (en) * | 2024-01-16 | 2024-04-05 | 苏州元脑智能科技有限公司 | PCIE equipment detection system, method, device and product |
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