CN103532686B - Serial data transceiver circuit with line sequence adaptive function and its control method - Google Patents

Abstract

The invention discloses a serial data transceiver circuit with a line sequence self-adaptive function and a control method thereof, wherein the circuit comprises a serial data transmitting end signal processing module and a serial data receiving end signal processing module, wherein the front end of the serial data transmitting end signal processing module is connected with a serial data transmitting end signal generating module, and the rear end of the serial data transmitting end signal processing module is connected with a serial signal transmission channel; the front end of the serial data receiving end signal processing module is connected with a serial signal transmission channel, and the rear end of the serial data receiving end signal processing module is connected with the serial data receiving end signal receiving module. The serial data transceiver circuit with the line sequence self-adaptive function and the control method thereof provided by the invention not only can better detect the line sequence error in the serial signal transmission, but also can self-adaptively adjust the line sequence of the serial signal, so that the data can be correctly transmitted at the two ends of the data transceiver. Meanwhile, the invention has better universality and can be applied to various system serial data transmission in various wired or wireless transmission channels and the like.

Description

Serial data transceiver circuit with line sequence adaptive function and its control method

technical field

The present application relates to the technical field of circuit systems, in particular to a serial data transceiver circuit with a line sequence adaptive function and a control method thereof.

Background technique

Serial data communication transmission has been widely used due to its small number of signal lines, such as Universal Asynchronous Receiver/Transmitter (UART), Serial Peripheral Interface (SPI) and other Implementation (such as I2C), where UART is an asynchronous serial communication method, usually using two signal lines for data transmission (TxD) and data reception (RxD); SPI is a synchronous serial communication method, usually using three lines (CLK, DATA and EN three-wire) or four-wire (CLK, MOSI, MISO, and EN four-wire) mode.

Since there are few serial data signal lines, the line sequence problem is particularly important, and the wrong line sequence will directly cause the transmitted data to be incorrectly received. In the implementation of serial signal transmission, the problem of line sequence error often occurs due to errors in flying wires, design errors, and wireless channel frequency errors.

Several patents have proposed solutions to detect and correct line sequence related problems.

The patent "A Wire Sequence Test Method" with application number 201010002667.7 proposes a method for performing a wire sequence test on an Ethernet cable. However, this method can only test the Ethernet cable; and only has the error detection function, but no adaptive error correction function; at the same time, this method is based on resistor voltage division, and requires an analog-to-digital conversion chip (hereinafter referred to as ADC), resistors and ADC. Stability will affect the line sequence test results. A similar patent also has the patent "Network Wiring Fault Simulation Tester" with application number 200820029252.7, which also has the defect that it can only be based on RJ-45 because it has no error correction function.

Patent Application No. 200910154166.8 "A Comprehensive Tester for Multi-Core Communication Cables" proposes a comprehensive tester for multi-core communication cables, which uses codec CPU to test line sequence information, but this method also needs to be based on ADC, and A separate CPU is required, and it can only provide test functions without self-correcting functions. Similar patents include patent application number 94223771.4 "Multi-wire cable line sequence and fault detector", application number 200610146680.3 patent "detection method" and application number 200610166865.0 patent "used to at least one cable "Detection method for detection" also has the defects of requiring a separate CPU, only providing test functions and not having self-error correction functions.

The patent "Network Cable Line Sequence Converter" with the application number of 200620036870.5 proposes a network cable line sequence converter, which can perform line sequence conversion on RJ-45-based network cables, but this network cable line sequence converter can only perform RJ-45 based -45 network cable for conversion, and only fixed line sequence conversion, and there is no error detection and adaptive error correction function.

Summarizing the above patents, it can be seen that the current patents and their implementation methods all have the disadvantages of only detection or fixed line sequence switching, and most of them can only be based on a specific interface (RJ-45).

As shown in FIG. 1 , FIG. 1 is a schematic diagram of conventional serial data signal transmission. The existing serial signal sending and receiving method is as follows: the serial signal sending end converts the data to be sent by the sending end processing circuit into a serial data signal according to the protocol, and the serial data signal is transmitted on the serial data signal transmission channel, and the serial After receiving the serial data signal, the data receiving end will convert the serial data signal back to the serial data in the original data format according to the protocol, and the serial data converted back to the original data format will be sent to the receiving end processing circuit for the next step deal with. Wherein, the sending end processing circuit can be a processor (CPU or MCU), a digital signal processor (DSP) or other processing circuits (FPGA, CPLD, etc.), and the serial data signal transmission channel can be a wired cable or a PCB circuit board Metal wires can also be wireless signal channels.

Taking the format of the baseband control signal as an SPI standard signal as an example, the SPI signal is a synchronous serial peripheral interface bus, which enables the processor to communicate with various peripheral devices in a serial manner, and the working mode is master-slave Mode. The SPI transmission mode is divided into three-wire system and four-wire system. The upper part of Figure 2 shows a normal three-wire SPI implementation. The three-wire SPI generally has the following three signals: clock signal (CLK), enable signal (EN) and data signal (DATA). The CLK signal is a sampling signal. When the CLK signal is a rising edge, the signal is sampled. When EN is stable at high level during sampling, the current value of DATA will be read as valid data. If DATA is low level, it will be read as data. '0' is read, if DATA is high level, it is read as data '1'. As shown in Figure 2, in order to ensure that the rising edge of CLK can be accurately sampled, both the EN signal and DATA should be ready before the CLK rises. The period before the CLK rises is called "Setup Time" on the digital circuit. ", in the example shown in Figure 2, EN is established earlier than the DATA signal. In the example shown in the upper part of Figure 2, the receiving end samples at the rising edge of the clock, and when EN is high, it samples '0', '1', '0', '1', '1' in sequence ', '0', '1', and '0'. In the current example, the MSB first transmission mechanism (Most Significant Bit, most significant bit) is used, that is, the first '0' is the MSB, and the sampled 8-bit result is 0b01011010, expressed as 90 in decimal and hexadecimal is 0x5A.

The lower part of Figure 2 shows the data transmission error caused by the three-wire SPI due to the wrong line sequence of the wrong exchange of the EN signal and the DATA signal. Since the data level that should be DATA is treated as EN, and the data level that should be EN is treated as DATA, the rising edge of the clock is only when the original DATA signal (now the wrong EN signal) is '1' Valid data will be identified, and when the DATA signal is '1', the EN signal must be '1', which causes all the signals collected by the SPI to be '1', and the result obtained when 8 valid data are collected The signal value is 8-bit binary data 0b11111111 (0xFF in hexadecimal, 255 in decimal).

The lower part of Figure 3 shows the data transmission error caused by the three-wire SPI due to the wrong line sequence of the wrong exchange of the CLK signal and the DATA signal. Since the data level that should be DATA is processed as CLK, and the data level that should be CLK is processed as DATA, the EN signal must be '1' when the clock (the original DATA signal) rises (as previously As mentioned above, the EN signal is established some time earlier than the DATA signal (used as the CLK signal), and the DATA signal (the original CLK signal) must be '0' (due to the establishment time, the DATA signal is established earlier than the CLK signal, and when When the DATA signal is used as the clock signal (CLK), when the rising edge is sampled, the DATA signal (the original CLK) is just before the rising edge, and must be '0'), which causes all the signals collected by the SPI to be '0', When 8 valid data are collected, the obtained signal value is 8-bit binary data 0b00000000 (0x00 in hexadecimal, 0 in decimal).

Contents of the invention

(1) Technical problems to be solved

In view of the above-mentioned one or more problems existing in the prior art, the main purpose of the present invention is to provide a serial data transceiver circuit with a line sequence adaptive function and a control method thereof, so as to detect line sequence errors and self-adapt Adjust the line sequence and relative delay of the serial signal, so that the data can be transmitted correctly at both ends of the data sending and receiving ends.

(2) Technical solution

According to one aspect of the present invention, the present invention provides a serial data transceiver circuit with a line sequence adaptive function, the circuit includes a serial data sending end signal processing module 100 and a serial data receiving end signal processing module 200, wherein , the front end of the serial data sending end signal processing module 100 is connected to the serial data sending end signal generating module 300, and the back end is connected to the serial signal transmission channel; the front end of the serial data receiving end signal processing module 200 is connected to the serial signal transmission The channel is connected, and the back end is connected with the signal receiving module 400 of the serial data receiving end.

In the above solution, the serial data sending end signal processing module 100 includes a serial signal pattern generation unit 101, a serial signal sending end control unit 104, a feedback signal receiving unit 105 and an error model determination unit 106, wherein the serial signal The pattern generating unit 101 is connected with the serial data sending end signal generating module 300, the serial signal transmission channel and the serial signal sending end control unit 104 respectively, and the serial signal sending end control unit 104 is respectively connected with the serial signal pattern generating unit 101, The error model determination unit 106 is connected to the feedback signal receiving unit 105 .

In the above solution, the serial signal pattern generation unit 101 includes a serial signal cross matrix subunit 103, which is used to receive the original serial data signal sent by the serial data sending end signal generation module 300, and receive the serial signal sending end control signal of the control unit 104, and after the original serial data signal is processed by its serial signal cross matrix subunit 103, the corrected serial data signal is output. The serial signal crossing matrix subunit 103 is used to perform signal crossing according to the instruction of the serial signal sending end control unit.

In the above solution, the serial signal sending end control unit 104 is used to receive the serial data reception feedback signal transmitted by the feedback signal receiving unit 105, and transmit it to the error model determination unit 106, and receive the feedback signal returned by the error model determination unit 106. Error type, control the working mode of the serial signal pattern generating unit 101 according to the error type, if the error type is unknown, the serial signal sending end control unit 104 will send an alarm message to the serial data sending end signal generating module 300 .

In the above solution, the feedback signal receiving unit 105 is configured to preprocess the feedback signal of the serial data receiving end, and transmit the processed signal to the serial signal sending end control unit 104 .

In the above scheme, the error model judgment unit 106 includes an error model storage subunit 107, which is used to receive the error judgment request sent by the serial signal sending end control unit 104 and the serial data receiving end feedback signal, and store The comparison and analysis of the models stored in the subunit 107 analyzes the current error model and transmits the result to the serial signal sending end control unit 104 .

In the above solution, the serial data receiver signal processing module 200 includes: a serial signal receiver control unit 201, configured to receive the corrected serial data signal on the serial signal transmission channel, and transmit the signal to the serial Row data receiving end signal receiving module 400 and feedback signal generating unit 202, and enable feedback signal generating unit 202 to generate serial data receiving end feedback signal on feedback channel; Feedback signal generating unit 202 is used to receive serial signal receiving end The serial data signal and the feedback signal instruction transmitted by the control unit 201 generate a serial data receiving terminal feedback signal, and output it to the feedback signal receiving unit 105 . The feedback signal generating unit 202 adds an identification signal to the generated feedback signal.

According to another aspect of the present invention, the present invention also provides a serial data transceiver control method, which is applied to the serial data transceiver circuit with a line sequence adaptive function, and the method includes:

Step A: the serial signal sending end control unit 104 controls the serial signal pattern generating unit 101 to send a test serial data signal;

Step B: the serial signal sending end control unit 104 receives the serial data receiving end feedback signal and sends a judgment request and data to the error model judging unit 106;

Step C, when the serial signal sending end control unit 104 receives the "normal" signal from the error model determination unit 106, control the serial signal pattern generation unit 101 to directly transmit the original serial data signal to the serial signal transmission channel;

Step D, when the serial signal sending end control unit 104 receives the "known error model" signal from the error model determination unit 106, it controls the serial signal pattern generation unit 101 to perform signal presentation and signal crossover in a specific pattern, and the processed The signal is transmitted to the serial signal transmission channel;

Step E, after receiving the "unknown error model" signal from the error model determination unit 106, the serial signal sending end control unit 104 sends an alarm message to the serial data sending end signal generation module 300 and waits for further processing instructions.

(3) Beneficial effects

The serial data transceiver circuit and its control method with line sequence self-adaptive function provided by the present invention can not only better detect the line sequence error in serial signal transmission, but also can adaptively adjust the line sequence of the serial signal, so that The data receiving and sending ends can transmit data correctly. At the same time, the present invention has good versatility, and can be applied to various standard serial data transmissions in various wired or wireless transmission channels.

Description of drawings

FIG. 1 is a schematic diagram of existing serial data signal transmission;

FIG. 2 is a schematic diagram illustrating a data transmission error caused by a wrong line sequence (wrong exchange of EN and DATA signals) by taking the three-wire SPI as an example.

FIG. 3 is a schematic diagram illustrating a data transmission error caused by a wrong line sequence (wrong exchange of CLK and DATA signals) by taking a three-wire SPI as an example.

FIG. 4 is a schematic diagram of the hardware architecture of the serial data transceiver circuit with line sequence adaptive function provided by the present invention.

FIG. 5 is a schematic diagram of the implementation of the serial data transceiver circuit with the line sequence adaptive function provided by the present invention in the unidirectional serial data transmission system.

FIG. 6 is a schematic diagram of the implementation of the serial data transceiver circuit with line sequence adaptive function provided in the present invention in a bidirectional serial data transmission system.

FIG. 7 is a flow chart of error model judgment of the serial data transceiver circuit with line sequence adaptive function provided by the present invention.

FIG. 8 is a schematic diagram of working functions of a serial signal cross matrix subunit.

FIG. 9 is a flow chart of test signal generation, feedback and error model determination.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

In the specific implementation manner described below, it is assumed that the format of the serial data signal is an SPI signal, and those skilled in the art should understand that the present invention is also applicable to signals of other formats.

In an exemplary embodiment of the present invention, a serial data signal transceiver circuit with a line sequence adaptive function is proposed. As shown in Figure 4, Figure 4 is a schematic diagram of the hardware architecture of the serial data transceiver circuit with line sequence adaptive function provided by the present invention, the serial data signal transceiver circuit includes a serial data sending end signal processing module 100 and a serial data The signal processing module 200 at the receiving end. According to the requirements of system implementation, if the system requires one-way data transmission, the signal processing module at the sending end and the signal processing module at the receiving end can be respectively implemented at the sending end and the receiving end as shown in Fig. 5 . If the system requires two-way data transmission, the signal processing module at the sending end and the signal processing module at the receiving end are implemented at both the A end and the B end as shown in FIG. 6 . The serial data sending end signal generating module 300 and the serial data receiving end signal receiving module 400 in FIG. 4 are components of the existing serial data transmission shown in FIG. 1 .

Wherein, the serial data sending end signal processing module 100, its front end is connected with the serial data sending end signal generation module 300, and its rear end is connected with the serial signal transmission channel, and this module includes a serial signal pattern generating unit 101, a serial A signal sending end control unit 104 , a feedback signal receiving unit 105 and an error model determining unit 106 . in:

The serial signal pattern generation unit 101 includes a serial signal cross matrix subunit 103, which is respectively connected to the serial data sending end signal generation module 300, the serial signal transmission channel and the serial signal sending end control unit 104 for receiving the serial signal The original serial data signal sent by the line data sending end signal generation module 300 receives the control signal of the serial signal sending end control unit 104, and outputs the original serial data signal after being processed by its serial signal cross matrix subunit 103 Corrected serial data signal.

The serial signal sending end control unit 104 is respectively connected with the serial signal pattern generation unit 101, the error model judgment unit 106 and the feedback signal receiving unit 105, and is used to receive the serial data receiving feedback signal transmitted by the feedback signal receiving unit 105, and Send it to the error model determination unit 106, receive the error type returned by the error model determination unit 106, control the working mode of the serial signal pattern generation unit 101 according to the error type, if the error type is unknown, the serial signal sending end control unit 104 will send an alarm message to the signal generating module 300 of the serial data sending end.

The feedback signal receiving unit 105 is configured to preprocess the feedback signal of the serial data receiving end, and transmit the processed signal to the serial signal sending end control unit 104 .

The error model judgment unit 106 includes the error model storage subunit 107, is connected with the serial signal sending end control unit 104, receives the error judgment request and the serial data receiving end feedback signal sent by the serial signal sending end control unit 104, and passes the Compare and analyze the models stored in the error model storage subunit 107 , analyze the current error model, and send the result to the serial signal sending end control unit 104 .

Serial data receiving terminal signal processing module 200, its front end is connected with serial signal transmission channel, and its back end is connected with serial data receiving terminal signal receiving module 400, and this module comprises serial signal receiving terminal control unit 201 and feedback signal generation Unit 202. in:

The serial signal receiving end control unit 201 receives the corrected serial data signal on the serial signal transmission channel, and transmits the signal to the serial data receiving end signal receiving module 400 and the feedback signal generating unit 202 .

The feedback signal generating unit 202 receives the serial data signal and the feedback signal instruction transmitted by the serial signal receiving end control unit 201 , generates a serial data receiving end feedback signal, and outputs it to the feedback signal receiving unit 105 .

The present invention is described below in 3 subsections with exemplary embodiments: "serial data sending end signal processing module 100 part" and "serial data receiving end signal processing module 200 part" have described the hardware circuit of the present invention, namely "A serial data transceiver circuit" described in the foregoing summary of the invention; "test signal generation, feedback, and error model determination process" illustrate the process of the present invention in terms of error model determination, that is, the process described in the foregoing summary of the invention "A Serial Data Transceiver Control Method".

Serial data sending end signal processing module 100 parts

The serial signal pattern generation unit 101 includes a serial signal cross matrix subunit 103 inside, the front end is connected to the serial data sending end signal generation module 300, receives the original serial data signal, and the back end is connected to the serial signal transmission channel, using It is used to process the original serial data signal (correct line sequence) and output the corrected serial data signal.

The serial signal crossover matrix subunit 103 is included in the serial signal pattern generating unit 101 and can perform signal crossover according to the instruction of the serial signal sending end control unit. In this embodiment, ports 0, 1, and 2 are respectively defined as EN, CLK, and DATA signals in normal transmission. As shown in Figure 8, the present invention explains the mode of operation of the serial signal crossover matrix subunit with the signal misalignment problem in Figure 3: A better four-wire cross matrix is an example), the serial signal sending end control unit 104 provides 4 pairs of configuration data to the serial signal pattern generating unit 101, the form is as follows: (input port, output port), as shown in Figure 8 (2, 1) means that the signal input from port 2 is output from port 1 after passing through the matrix. The serial signal cross matrix subunit 103 reads the configuration data and corrects the signal line order during operation. As shown in FIG. The subunit 103 is corrected to restore the correct signal connection. The serial signal cross matrix subunit 103 can output the serial data test signal under the instruction of the serial signal sending end control unit 104 at the same time, as shown in FIG. , Feedback and Error Model Judgment Process” section.

The serial signal sending end control unit 104 is connected with the feedback signal receiving unit 105, the serial signal pattern generating unit 101 and the error model determination unit 106, and is used to receive the feedback signal after the feedback signal receiving unit 105 preprocesses, and The above signal is transmitted to the error model determination unit 106, and after receiving the return result of the error model determination unit 106, if the result is "normal" or "known error model", then configure the corrected serial signal cross matrix subunit according to the corresponding result 103 configuration data; if the result is “unknown error model”, the serial signal sending end control unit 104 will send an alarm message to the serial data sending end signal generation module 300 . At the same time, the serial data sending end control unit 104 can also control the serial signal pattern generating unit 101 to generate a serial data test signal, as shown in FIG. and error model judgment process” section.

The feedback signal receiving unit 105 is connected to the feedback channel and the serial signal sending end control unit 104, and is used to receive the signal on the feedback channel and preprocess it into a signal that can be processed by each part of the serial data sending end signal processing module . For example, the signal on the feedback channel is at a 5V TTL level, and the signal processing module 100 at the serial data sending end uses a 1.8V CMOS level, then the feedback signal receiving unit 105 needs to sample and convert the signal in the feedback signal into a 1.8V CMOS level. flat signal. For another example, the signals on the feedback channel and the signal processing module 100 of the serial data sending end are both at 1.8V CMOS level, but due to the signal attenuation of the feedback channel, when the level actually reaching the feedback signal receiving unit 105 is only about 1.2V, the feedback signal The receiving unit 105 will sample and regenerate the signal on the channel, and restore it to a standard 1.8V CMOS level.

The error model judgment unit 106 is connected with the serial signal sending end control unit 104, receives the feedback signal and the error model judgment request transmitted by the serial signal sending end control unit 104, and combines the feedback signal with the error model storage subunit 107 The signals are compared to obtain the error model judgment result ("normal", "known error model" or "unknown error model") and the error model code (the specific type of "known error model"), and the error model judgment result The data is transmitted to the serial signal sending end control unit 104, and further processed by the serial signal sending end control unit 104. The error model determination process in the current embodiment is shown in FIG. 9 , see the section "Generation and Feedback of Test Signals and Error Model Determination Process" below.

Serial data sending and receiving end signal processing module 200 part

The serial signal receiving end control unit 201 is connected with the serial signal transmission channel, the feedback signal generating unit 202 and the serial data receiving end signal receiving module 400, for receiving and preprocessing the corrected serial signal on the serial signal transmission channel. data signal (the level preprocessing method is the same as the feedback signal receiving unit 105), and at the same time, the received and preprocessed signal is sent to the feedback signal generating unit 202, and the feedback signal generating unit 202 is enabled to generate a serial signal on the feedback channel Line data receiving end feedback signal.

The feedback signal generation unit 202 is connected with the serial signal receiving end control unit 201 and the feedback channel, and is used to receive the data signal and the enabling instruction transmitted by the serial signal receiving end control unit 201, and generate a serial data reception signal on the feedback channel. terminal feedback signal. In order to enable each unit of the signal processing module 100 at the serial data sending end to identify the feedback signal, the feedback signal generation unit 202 needs to add an identification signal to the feedback signal, which is a leading signal in the current embodiment, and the generation of the feedback signal is shown in FIG. 9 For more information, please refer to the section "Generation of Test Signals, Feedback and Error Model Judgment Process" below.

Test signal generation, feedback and error model judgment process

As shown in Figure 7, when the serial data transceiver circuit with line sequence adaptive function proposed by the present invention performs a data transmission, the process is as follows: first, the serial signal sending end control unit 104 controls the serial signal pattern generation unit 101 Send a test serial data signal (step A); after receiving the test signal, the serial signal receiver control unit 201 transmits the data to the feedback signal generating unit 202, and enables the feedback signal generating unit 202 to generate a serial signal on the feedback channel The row data receiving end feeds back a signal, and the feedback signal will add an identifier for identification by the feedback signal receiving unit 105 (the current embodiment uses the preamble as the identifier). After receiving the signal pre-processed by the feedback signal receiving unit 105, the serial signal sending end control unit 104 transmits the signal data and the request to the error model judgment unit 106, and the error model judgment unit 106 combines the signal data with the error model memory The feature code in the unit 107 is compared, and draws error model judgment result (" normal ", " known error model " or " unknown error model " and judgment code) returns to serial signal sending end control unit 104 (step B); The serial signal sending end control unit 104 will control the serial signal pattern generation unit 101 and set the configuration data (step C, step D or step E) of the serial signal cross matrix subunit 103 according to the judgment result; Step C , when the serial signal sending end control unit 104 receives the "normal" signal from the error model determination unit 106, control the serial signal pattern generation unit 101 to directly transmit the original serial data signal to the serial signal transmission channel; step D, When the serial signal sending end control unit 104 receives the "known error model" signal from the error model determination unit 106, it controls the serial signal pattern generation unit 101 to perform signal demonstration and signal crossover in a specific mode, and transmits the processed signal To the serial signal transmission channel; step E, after the serial signal sending end control unit 104 receives the "unknown error model" signal of the error model determination unit 106, send an alarm message to the serial data sending end signal generation module 300 and wait Further processing instructions.

Fig. 9 illustrates the flow of test signal generation, feedback and error model determination with specific examples. As shown in Figure 9, when a data transmission starts, the serial signal sending end control unit 104 controls the serial signal pattern generating unit 101 to generate a test signal on the serial signal transmission channel, and the test signal in this embodiment is binary 0b01011010 (hexadecimal 0x5A), the serial signal receiver control unit 201 transmits the signal and the enable command to the feedback unit generation unit 202 after receiving the test signal, and the feedback unit generation unit 202 adds a 2-bit preamble ( In the current embodiment, 0b01) is used as an identifier and the received first 8 bits are output once after the preamble as a feedback signal.

If the current line sequence is correct, the 10-bit data added to the leading character are: "0", "1", "0", "1", "0", "1", "1", "0", "1" ", "0", (the value is 0x5A after removing the 2-bit leading character).

If the current line sequence has an error in the wrong exchange of EN and DATA signals as shown in Figure 2, the 10-bit data added to the preamble are: "0", "1", "1", "1", "1" , "1", "1", "1", "1", "1", (the value is 0xFF after removing the 2-bit leading character).

If the current line sequence has an error of CLK and DATA signal exchange as shown in Figure 3, the 10-bit data added to the preamble is: "0", "1", "0", "0", "0" , "0", "0", "0", "0", "0", (the value is 0x00 after removing the 2-bit leading character).

If the first EN signal of the test signal is not correctly sampled, resulting in the first "0" not being sampled, then the 10-bit data added to the preamble are: "0", "1", "1", "0" ", "1", "1", "0", "1", "0", "0", "unknown error" marked in Figure 9, (the value is 0xB8 after removing the 2bit leading character).

After receiving the feedback signal of the feedback channel and confirming the preamble, the feedback signal receiving unit 105 will decode the remaining 8 bits and send them to the serial signal sending end control unit 104, and the serial signal sending end control unit 104 will send the remaining 8 bits to the serial signal sending end control unit 104. The data value of is transmitted to the error model determination unit 106, and the error model determination unit 106 compares the data value with the feature code in the error model storage subunit and obtains a determination result. As shown in Figure 9, if the feedback value is 0x5A, it is determined as "normal", and the judgment code "0" is returned to the serial signal sending end control unit 104, representing "normal"; if the feedback value is 0x00, it is determined as "normal". Known error model", return judgment code "1" to the serial signal sending end control unit 104, representing "known error model, CLK/DATA signal error exchange"; if the feedback value is 0xFF, it is judged as "known error Model", return the judgment code "2" to the serial signal sending end control unit 104, representing "known error model, EN/DATA signal error exchange"; if the feedback value is other values, then it is judged as "unknown error model", Return judgment code "4" to the serial signal sending end control unit 104, representing "unknown error model";

According to the judgment result of the error model judging unit 106, the serial signal sending end control unit 104 makes different processing for different results:

If the judgment result is "normal" (judgment code "0"), the configuration value of the serial signal cross matrix subunit 103 is configured as ((0,0), (1,1), (2,2), ( 3, 3)) and continue subsequent data transmission;

If the determination result is "known error model, CLK/DATA signal error exchange" (judgment code "1"), the configuration value of the serial signal cross matrix subunit 103 is configured as ((0, 0), (1, 2), (2,1), (3,3)) and continue the subsequent data transmission, as described in Figure 8;

Similar to CLK/DATA signal error exchange, if the judgment result is "known error model, EN/DATA signal error exchange" (judgment code "2"), the configuration value of the serial signal cross matrix subunit 103 is configured as ( (0, 2), (1, 1), (2, 0), (3, 3)) and continue subsequent data transmission;

If the judgment result is "unknown error model" (judgment code "4"), an alarm is sent to the signal generating module 300 at the sending end.

To sum up, the serial data transceiver circuit with line sequence adaptive function and its control method provided by the present invention can not only better detect the line sequence error in serial signal transmission, but also can adaptively adjust the serial The signal line sequence enables the two ends of the data transceiver to transmit data correctly. At the same time, the present invention has good versatility, and can be applied to various standard serial data transmissions in various wired or wireless transmission channels.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (8)

1. the serial data transmission circuit with line sequence self-adaptive, it is characterised in that should Circuit includes at serial data transmitting terminal signal processing module (100) and Serial data receiving end signal Reason module (200), wherein, this serial data transmitting terminal signal processing module (100) front end and string Row data sending terminal signal generation module (300) connects, and rear end is connected with serial signal transfer channel； This Serial data receiving end signal processing module (200) front end is connected with serial signal transfer channel, Rear end is connected with Serial data receiving end signal receiver module (400)；

Wherein, described serial data transmitting terminal signal processing module (100) includes serial signal pattern Signal generating unit (101), serial signal transmitting terminal control unit (104), feedback signal reception unit (105) With error model identifying unit (106), wherein, serial signal schema creation unit (101) is respectively Send out with serial data transmitting terminal signal generation module (300), serial signal transfer channel and serial signal Sending end control unit (104) connect, serial signal transmitting terminal control unit (104) respectively with serial Signal mode signal generating unit (101), error model identifying unit (106) and feedback signal reception list Unit (105) connects；

Described serial signal transmitting terminal control unit (104) is used for receiving feedback signal reception unit (105) The Serial data receiving feedback signal transmitted, and it is sent to error model identifying unit (106), Receive the type of error that error model identifying unit (106) returns, control string according to this type of error The mode of operation of row signal mode signal generating unit (101), if type of error is unknown, then serial letter Number transmitting terminal control unit (104) will serially send by data sending terminal signal generation module (300) Warning message.

Serial data transmission circuit with line sequence self-adaptive the most according to claim 1, It is characterized in that, described serial signal schema creation unit (101), including serial signal cross matrix Subelement (103), is used for receiving that serial data transmitting terminal signal generation module (300) sends is former Beginning serial data signal, receives the control signal of serial signal transmitting terminal control unit (104), and By original serial data signal after its serial signal cross matrix subelement (103) processes, defeated Go out and revise serial data signal.

Serial data transmission circuit with line sequence self-adaptive the most according to claim 2, It is characterized in that, described serial signal cross matrix subelement (103) is for sending out according to serial signal The instruction of sending end control unit carries out signal cross.

Serial data transmission circuit with line sequence self-adaptive the most according to claim 1, It is characterized in that, described feedback signal reception unit (105) is for feeding back Serial data receiving end Signal carries out pretreatment, and the signal after processing sends serial signal transmitting terminal control unit to (104)。

Serial data transmission circuit with line sequence self-adaptive the most according to claim 1, It is characterized in that described error model identifying unit (106) comprises error model storing sub-units (107), it is used for receiving the wrong decision request that serial signal transmitting terminal control unit (104) sends And Serial data receiving end feedback signal, by storing in error model storing sub-units (107) The comparison of model and analysis, analyze current erroneous model, result sent to serial signal transmitting terminal Control unit (104).

Serial data transmission circuit with line sequence self-adaptive the most according to claim 1, It is characterized in that, described Serial data receiving end signal processing module (200) including:

Serial signal receiving terminal control unit (201), has been used for receiving on serial signal transfer channel Revise serial data signal, and this signal is sent to Serial data receiving end signal receiver module (400) With feedback signal generating unit (202), and enable feedback signal generating unit (202) in feedback letter Serial data receiving end feedback signal is produced on road；

Feedback signal generating unit (202), is used for receiving serial signal receiving terminal control unit (201) The serial data signal transmitted and feedback signal instruction, generate Serial data receiving end feedback signal, defeated Go out to feedback signal reception unit (105).

Serial data transmission circuit with line sequence self-adaptive the most according to claim 6, It is characterized in that, described feedback signal generating unit (202) adds in the feedback signal generated to be known Level signal.

8. a serial data receiving and sending control method, is applied to institute any one of claim 1 to 7 The serial data transmission circuit with line sequence self-adaptive stated, it is characterised in that the method includes:

Step A: serial signal transmitting terminal control unit (104) controls serial signal schema creation list Unit (101) sends test serial data signal；

Step B: serial signal transmitting terminal control unit (104) receives Serial data receiving end feedback Signal also sends decision request and data to error model identifying unit (106)；

Step C, judges single when serial signal transmitting terminal control unit (104) receives error model After " normally " signal of unit (106), control serial signal schema creation unit (101) by original Serial data signal is conveyed directly to serial signal transfer channel；

Step D, judges single when serial signal transmitting terminal control unit (104) receives error model After " known error model " signal of unit (106), control serial signal schema creation unit (101) Carrying out signal demonstration and signal cross by AD HOC, the signal after processing is sent to serial signal and passes Defeated channel；

Step E, judges single when serial signal transmitting terminal control unit (104) receives error model After " unknown error model " signal of unit (106), serially data sending terminal signal generation module (300) alert wait process instruction further.