CN103531593B - Pixel structure, array substrate, display device and manufacturing method of pixel structure - Google Patents

Abstract

The present invention relates to the technical field of display panel manufacturing, in particular to a pixel structure, an array substrate, a display device, and a method for manufacturing a pixel structure, which are used to reduce the probability of disconnection between a second transparent electrode layer and a source-drain layer, and improve the reliability of the array substrate. quality. The pixel structure includes: a base substrate provided with a source and drain layer, a first passivation layer covering the source and drain layer and having a first via hole, a resin layer covering the first passivation layer and having a second via hole, The first transparent electrode layer arranged on the resin layer, the second passivation layer covering the resin layer and the first transparent electrode layer and having a third via hole, the conductive compensation block arranged in the first via hole; The second transparent electrode layer on the second passivation layer, in the third via hole, in the second via hole and in the first via hole, the second transparent electrode layer passes through the conductive compensation block and the source drain layer electrical connections.

Description

Pixel structure, array substrate, display device and method for manufacturing pixel structure

technical field

The present invention relates to the technical field of display panel manufacturing, in particular to a pixel structure, an array substrate, a display device and a method for manufacturing the pixel structure.

Background technique

At present, high resolution is a major development trend of the display panel. When the resolution of the display panel is increased from 200 pixels per inch (pixels per inch, hereinafter referred to as ppi) to 300Pppi, 400ppi, 500ppi or above 500ppi, due to the pixel The reduction of the distance between them leads to a sharp decrease in the aperture ratio. Therefore, an array substrate manufactured by eight patterning processes has emerged, which can effectively compensate the aperture ratio.

As shown in FIG. 1 , it is a structural schematic diagram of a pixel structure in the prior art. The pixel structure includes: a base substrate, a gate layer 1 disposed on the base substrate, a gate insulating layer 2 covering the gate layer 1, an active layer 3 disposed on the gate insulating layer 2, covering the active The source-drain layer 4 of layer 3 covers the first passivation layer 5 of the source-drain layer 4. The first passivation layer 5 has a plurality of first via holes communicating with the source-drain layer 4, and is arranged on the first passivation layer. The resin layer 6 on the layer 5, the resin layer 6 has a plurality of second via holes corresponding to a plurality of first via holes, the first transparent electrode layer 7 arranged on the resin layer 6; covering the first transparent electrode The second passivation layer 8 of the layer 7, the second passivation layer 8 has a plurality of third via holes corresponding to the plurality of second via holes one by one, and the second transparent electrode arranged on the upper surface of the second passivation layer 8 layer 9, the second transparent electrode layer 9 is electrically connected to the source and drain layer 4 through the conductive film deposited in the corresponding third via hole, the second via hole and the first via hole.

The inventors of the present application found that, in the process of manufacturing the pixel structure of the above-mentioned array substrate, the first via hole formed on the first passivation layer 5 and the second via hole formed on the resin layer 6 respectively through the patterning process When the first passivation layer 5 is etched laterally, the diameter of the first via hole and the second via hole will be inconsistent; thus, the second transparent electrode layer will be disconnected from the source and drain layers. , as shown in area A in FIG. 1 , the second transparent electrode layer 9 is disconnected from the source-drain layer 4, thereby affecting the quality of the array substrate.

Contents of the invention

The object of the present invention is to provide a pixel structure, an array substrate and a method for manufacturing the pixel structure, which are used to reduce the probability of disconnection between the second transparent electrode layer and the source-drain layer and improve the quality of the array substrate.

In order to achieve the above object, the present invention provides the following technical solutions:

A pixel structure, comprising: a substrate provided with a source-drain layer, a first passivation layer covering the source-drain layer, the first passivation layer having a first passivation layer communicating with the source-drain layer A via hole covers the resin layer of the first passivation layer, the resin layer has a second via hole corresponding to the first via hole, and the first transparent electrode layer disposed on the resin layer is located at The second passivation layer on the resin layer and covering the first transparent electrode layer, the second passivation layer has a third via hole corresponding to the second via hole; and also includes:

a conductive compensation block disposed in the first via hole;

a second transparent electrode layer disposed on the second passivation layer, in the third via hole, in the second via hole and in the first via hole; the second transparent electrode layer passes through the The conductive compensation block is electrically connected to the source-drain layer.

Preferably, the thickness of the conductive compensation block, the thickness of the second transparent electrode layer, and the thickness of the first passivation layer satisfy the following relationship:

T1+T2≥T3

Wherein, T1 is the thickness of the conductive compensation block, T2 is the thickness of the second transparent electrode layer, and T3 is the thickness of the first passivation layer.

Preferably, the thickness of the conductive compensation block, the thickness of the second transparent electrode layer, and the thickness of the first passivation layer satisfy the following relationship:

T1+T2≥1.4×T3

Wherein, T1 is the thickness of the conductive compensation block, T2 is the thickness of the second transparent electrode layer, and T3 is the thickness of the first passivation layer.

Preferably, the conductive compensation block is an indium tin oxide compensation block, a molybdenum compensation block or a molybdenum aluminum alloy compensation block.

Preferably, the second passivation layer includes: a transparent oxide layer disposed on the resin layer, the first transparent electrode layer, the first via hole and the second via hole, a silicon nitride layer on the transparent oxide layer;

The thickness of the conductive compensation block is equal to the thickness of the transparent oxide layer.

Further, the above-mentioned pixel structure further includes: a gate layer, a gate insulating layer and an active layer located between the base substrate and the source-drain layer; wherein,

The gate layer is disposed on the base substrate;

The gate insulating layer covers the gate layer;

The active layer is disposed on the gate insulating layer.

The present invention also provides an array substrate, including a plurality of pixel structures provided in the above technical solution.

The present invention also provides a display device, including the array substrate mentioned in the above technical solution.

The display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like. For the implementation of the display device, reference may be made to the above-mentioned embodiments, and repeated descriptions will not be repeated.

The present invention also provides a method for manufacturing a pixel structure, including:

A patterned gate layer is formed on the upper surface of the base substrate through a patterning process;

forming a gate insulating layer covering the gate layer;

forming a patterned active layer on the upper surface of the gate insulating layer through a patterning process;

forming a source-drain layer covering the active layer through a patterning process;

Through a patterning process, a patterned first passivation layer and a patterned resin layer are formed; wherein, the first passivation layer covers the source and drain layers, and the first passivation layer has the same A first via hole communicating with the source-drain layer; the resin layer is disposed on the upper surface of the first passivation layer, and the resin layer has a second via hole corresponding to the first via hole;

A patterned first transparent electrode layer is formed on the upper surface of the resin layer through a patterning process, and a conductive compensation block is formed in the first via hole;

A second passivation layer covering the resin layer and the first transparent electrode layer is formed through a patterning process, and the second passivation layer has a third via hole corresponding to the second via hole;

A second transparent electrode layer is formed on the upper surface of the second passivation layer, in the third via hole, in the second via hole and in the first via hole through one patterning process, so that The second transparent electrode layer is electrically connected to the source-drain layer through the conductive compensation block.

Preferably, a patterned first passivation layer and a patterned resin layer are formed through a patterning process, which specifically includes:

coating a passivation material on the source-drain layer to form a first passivation layer;

Coating resin on the first passivation layer to form a resin layer;

A second via hole is formed on the resin layer through masking, etching, and stripping procedures, and a first via hole is formed on the first passivation layer, and the first via hole corresponds to the second via hole.

The present invention also provides a method for manufacturing a pixel structure, including:

A patterned gate layer is formed on the upper surface of the base substrate through a patterning process;

forming a gate insulating layer covering the gate layer;

forming a patterned active layer on the upper surface of the gate insulating layer through a patterning process;

forming a source-drain layer covering the active layer through a patterning process;

Through a patterning process, a patterned first passivation layer and a patterned resin layer are formed; wherein, the first passivation layer covers the source and drain layers, and the first passivation layer has the same a first via hole communicating with the source-drain layer; the resin layer is disposed on the upper surface of the first passivation layer, and the resin layer has a second via hole corresponding to the first via hole;

forming a first transparent electrode layer on the resin layer through a patterning process;

A second passivation layer is formed on the first transparent electrode layer, on the resin layer, in the first via hole and in the second via hole, and the second passivation layer includes: formed on the A transparent oxide layer on the first transparent electrode layer, on the resin layer, in the first via hole, and in the second via hole, and a silicon nitride layer formed on the transparent oxide layer;

Forming a third via hole in communication with the transparent oxide layer in a region of the silicon nitride layer corresponding to the first via hole through a mask and etching process;

Through a plasma treatment process, the area of the transparent oxide layer corresponding to the first via hole becomes a conductor, and the conductor is the conductive compensation block;

Through one patterning process, on the upper surface of the second passivation layer, on the inner wall of the third via hole, on the inner wall of the second via hole, on the inner wall of the first via hole and on the conductive compensation A second transparent electrode layer is formed on the block, and the second transparent electrode layer is electrically connected to the source-drain layer through the conductive compensation block.

In the pixel structure provided by the present invention, by adding a conductive compensation block in the first via hole, the second transparent electrode layer is electrically connected to the source and drain layers through the conductive compensation block, so as to reduce the The probability of disconnection of the second transparent electrode layer, that is, reduces the probability of disconnection of the second transparent electrode layer and the source-drain layer, thereby improving the quality of the array substrate.

Description of drawings

FIG. 1 is a schematic structural diagram of a pixel structure in the prior art;

FIG. 2 is a schematic structural diagram of a pixel structure provided by an embodiment of the present invention;

3 is a cross-sectional view of a pixel structure in which the second passivation layer has a two-layer structure;

Fig. 4 is a flow chart of making a pixel structure provided by an embodiment of the present invention;

5a is a cross-sectional view of the pixel structure after etching the resin layer in the first passivation layer and the resin layer;

5b is a cross-sectional view of the first passivation layer and the pixel structure after etching the first passivation layer in the resin layer;

Fig. 5c is a cross-sectional view of a pixel structure provided with a conductive compensation block in a first via hole;

5d is a cross-sectional view of a pixel structure formed with a second passivation layer;

5e is a cross-sectional view of the pixel structure after etching the second passivation layer;

Fig. 5f is a cross-sectional view of a pixel structure formed with a second transparent electrode layer;

6a is a cross-sectional view of a pixel structure when the second passivation layer has a two-layer structure;

6b is a cross-sectional view of the pixel structure after etching the upper structure of the second passivation layer;

Fig. 6c is a cross-sectional view of the pixel structure after the plasma treatment of the lower structure of the second passivation layer.

Reference signs:

1-Gate layer, 2-Gate insulating layer, 3-Active layer,

4-source-drain layer, 5-first passivation layer, 6-resin layer,

7-the first transparent electrode layer, 8-the second passivation layer, 9-the second transparent electrode layer,

10-conductive compensation block, 81-transparent oxide layer, 82-silicon nitride layer.

Detailed ways

In order to reduce the probability that the second transparent electrode layer is disconnected from the source-drain layer and improve the quality of the array substrate, the present invention provides a pixel structure. By adding a conductive compensation block in the first via hole, the second transparent electrode Layer is electrically connected to the source and drain layer through the conductive compensation block, so as to reduce the probability of disconnection of the second transparent electrode layer deposited in the first via hole, that is, to reduce the disconnection of the second transparent electrode layer and the source and drain layer chance, thereby improving the quality of the array substrate.

In order to enable those skilled in the art to better understand the technical solutions of the present invention, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

As shown in FIG. 2 , it is a schematic structural diagram of a pixel structure provided by an embodiment of the present invention. The pixel structure provided by the embodiment of the present invention includes: a base substrate provided with a source-drain layer 4; a first passivation layer 5 covering the source-drain layer 4, and the first passivation layer 5 has an The first via hole; the resin layer 6 covering the first passivation layer 5, the resin layer 6 has a second via hole corresponding to the first via hole; the first transparent electrode layer 7 arranged on the resin layer 6; located in the resin A second passivation layer 8 on the layer 6 and covering the first transparent electrode layer 7, the second passivation layer 8 has a third via hole corresponding to the second via hole; and,

Conductive compensation block 10 arranged in the first via hole;

The second transparent electrode layer 9 arranged on the second passivation layer 8, in the third via hole, in the second via hole and in the first via hole, the second transparent electrode layer 9 passes through the conductive compensation block 10 and the source and drain Layer 4 is electrically connected.

In the embodiment of the present invention, a conductive compensation block 10 is correspondingly arranged in the first via hole, and when the second transparent electrode layer 9 is formed by depositing a coating film in the third via hole, the second via hole and the first via hole, The existence of the conductive compensation block 10 can effectively reduce the impact of lateral etching in the first via hole, and can effectively reduce the disconnection probability of the second transparent electrode layer 9 deposited in the first via hole, thereby reducing the The probability that the second transparent electrode layer 9 is disconnected from the source-drain layer 4 further improves the quality of the array substrate. It is worth mentioning that the above-mentioned second transparent electrode layer 9 includes: a film layer located on the upper surface of the second passivation layer 8 and located on the inner wall of the third via hole, on the inner wall of the second via hole, on the inner wall of the first via hole, The film layer on the upper surface of the conductive compensation block 10 .

During specific implementation, in order to effectively eliminate the impact of the lateral etching in the first via hole on the second transparent electrode layer 9, and improve the pass rate of the pixel structure; preferably, the thickness of the conductive compensation block 10, the second transparent electrode layer 9 The thickness of and the thickness of the first passivation layer 5 satisfy the following relationship:

T1+T2≥T3

Wherein, T1 is the thickness of the conductive compensation block 10 , T2 is the thickness of the second transparent electrode layer 9 , and T3 is the thickness of the first passivation layer 5 . It is so set that the sum of the thicknesses of the conductive compensation block 10 and the second transparent electrode layer 9 is greater than or equal to the thickness of the first passivation layer 5, thereby eliminating the influence of lateral etching and reducing the second electrode deposited in the first via hole. The disconnection probability of the transparent electrode layer 9 reduces the probability of disconnection between the second transparent electrode layer 9 and the source-drain layer 4 , thereby improving the quality of the array substrate.

However, sometimes due to the instability of the manufacturing process or other factors, the thickness of the conductive compensation block 10, the thickness of the second transparent electrode layer 9, and the thickness of the first passivation layer 5 are not very uniform. Therefore, in order to increase the pixel structure Reliability, the thickness of the conductive compensation block 10, the thickness of the second transparent electrode layer 9, and the thickness of the first passivation layer 5 satisfy the following relationship:

T1+T2≥1.4×T3

Wherein, T1 is the thickness of the conductive compensation block, T2 is the thickness of the second transparent electrode layer, and T3 is the thickness of the first passivation layer.

For example, when the thickness of the first passivation layer 5 is 1000A, the thickness of the conductive compensation block 10 is required to be 700A, and the thickness of the second transparent electrode layer 9 is 700A. It should be noted that the thickness of the first passivation layer 5 is generally 500-1500A, the thickness of the conductive compensation block 10 is generally 400-800A, which is equal to the first transparent electrode layer 7, and the thickness of the second transparent electrode layer 9 is generally 400-800A.

Therefore, the thickness of the conductive compensation block 10 can be set by the above two relational expressions, and can be specifically selected according to actual conditions.

In the above pixel structure, the conductive compensation block 10 can be formed simultaneously with the first transparent electrode layer 7, or can be formed after the formation of the first passivation layer 5, after the formation of the resin layer 6 or after the formation of the second passivation layer 8. Specifically, the required conductive compensation block 10 can be formed in the first via hole through processes such as deposition, masking, etching, and stripping; continue to refer to FIG. 2 , in order to simplify the manufacturing process of the pixel structure, preferably, the conductive compensation block 10 It is formed simultaneously with the first transparent electrode layer 7 ; therefore, the thickness of the conductive compensation block 10 is equal to the thickness of the first transparent electrode layer 7 . In addition, because the first transparent electrode layer 7 is usually made of indium tin oxide (ITO), molybdenum compensation block or molybdenum aluminum alloy material, so preferably, the conductive compensation block 10 is indium tin oxide compensation block, molybdenum compensation block or Molybdenum aluminum alloy compensation block.

But not limited to the above two implementations, it can also be implemented in the following way, as shown in Figure 3, which is a cross-sectional view of a pixel structure with a second passivation layer having a two-layer structure; in this implementation, the second passivation layer 8 Including: the transparent oxide layer 81 disposed in the resin layer 6, the first transparent electrode layer 7, the first via hole, and the second via hole, and the silicon nitride layer 82 disposed on the transparent oxide layer 81; the conductive compensation block 10 The thickness is equal to the thickness of the transparent oxide layer 81 . The transparent oxide layer 81 and the silicon nitride layer 82 can be specifically formed by deposition, and the conductive compensation block 10 first forms the transparent oxide layer 81 and the transparent oxide layer 81 in the area corresponding to the silicon nitride layer 82 and the first via hole through processes such as masking and etching. After connecting the third via hole, the area corresponding to the transparent oxide layer 81 and the first via hole is converted into a conductor through a plasma treatment process, and the conductor can be used as the conductive compensation block 10, and then the stripping process is performed.

Continuing to refer to FIG. 2 , further, the above-mentioned pixel structure further includes: a gate layer 1, a gate insulating layer 2 and an active layer 3 located between the base substrate and the source-drain layer 4; wherein, the gate layer 1 is set On the substrate; the gate insulating layer 2 covers the gate layer 1; the active layer 3 is disposed on the gate insulating layer 2.

An embodiment of the present invention also provides an array substrate, including: a plurality of pixel structures described in the above technical solution.

An embodiment of the present invention also provides a display device, including the array substrate mentioned in the above technical solution.

As shown in FIG. 4 , it is a flow chart of manufacturing a pixel structure provided by an embodiment of the present invention. The manufacturing method of the pixel structure provided by the embodiment of the present invention includes:

Step 101, forming a patterned gate layer 1 on the upper surface of the base substrate through a patterning process;

Step 102, forming a gate insulating layer 2 covering the gate layer 1;

Step 103, forming a patterned active layer 3 on the upper surface of the gate insulating layer 2 through a patterning process;

Step 104, forming a source-drain layer 4 covering the active layer 3 through a patterning process;

The specific manufacturing process of the above steps 101 to 104 is well known to those skilled in the art, and will not be described in detail here.

Step 105, forming a patterned first passivation layer 5 and a patterned resin layer 6 through a patterning process; wherein, the first passivation layer 5 covers the source and drain layers 4, and the first passivation layer 5 There is a first via hole communicating with the source and drain layer 4; the resin layer 6 is arranged on the upper surface of the first passivation layer 5, and the resin layer 6 has a second via hole corresponding to the first via hole; see FIG. 5a and FIG. 5b, wherein, Fig. 5a is a cross-sectional view of the pixel structure after etching the first passivation layer and the resin layer in the resin layer; Fig. 5b is etching the first passivation layer and the first passivation layer in the resin layer Cross-sectional view of the pixel structure after. A patterned first passivation layer 5 and a patterned resin layer 6 are formed through a patterning process, which specifically includes: coating a passivation material on the source and drain layer 4 to form the first passivation layer 5; A passivation layer 5 is coated with resin to form a resin layer 6; a second via hole is formed on the resin layer 6 through masking, etching, and stripping processes, and a first via hole is formed on the first passivation layer 5, and the second via hole is formed on the first passivation layer 5. The first via corresponds to the second via. With such a design, the first via hole can be formed in the first passivation layer 5 and the second via hole can be formed in the resin layer 6 through one patterning process, so that the subsequent offset resin layer 6 or the first passivation layer can be omitted. The process of forming the layer 5 so that the first via hole is opposite to the second via hole will not affect the aperture ratio of the pixel structure, thereby facilitating the manufacture of an array substrate with high resolution.

Step 106, through a patterning process, form a patterned first transparent electrode layer 7 on the upper surface of the resin layer 6, and form a conductive compensation block 10 in the first via hole; see FIG. A cross-sectional view of a pixel structure with a conductive compensation block disposed in a via hole. It can be seen that through a patterning process, a patterned first transparent electrode layer 7 is formed on the upper surface of the resin layer 6, and a conductive compensation block 10 is formed in the first via hole, specifically including: on the resin layer 6 A layer of transparent conductive film is deposited on the surface and in the first via hole; a second transparent electrode layer 7 is formed on the resin layer 6 through masking, etching, and stripping processes, and a conductive compensation block 10 is formed in the first via hole.

Step 107: Form a second passivation layer 8 covering the resin layer 6 and the first transparent electrode layer 7 through a patterning process, and the second passivation layer 8 has a third via hole corresponding to the second via hole; see FIG. 5d and FIG. 5e, wherein, FIG. 5d is a cross-sectional view of the pixel structure formed with the second passivation layer; FIG. 5e is a cross-sectional view of the pixel structure after the second passivation layer is etched.

Step 108, through a patterning process, form the second transparent electrode layer 9 on the upper surface of the second passivation layer 8, in the third via hole, in the second via hole and in the first via hole, and the second transparent electrode layer 9 Layer 9 is electrically connected to source-drain layer 4 through conductive compensation block 10 . Referring to FIG. 5f, it is a cross-sectional view of the array substrate formed with the second transparent electrode layer. Through a patterning process, the second transparent electrode layer 9 is formed on the upper surface of the second passivation layer 8, specifically including: on the upper surface of the second passivation layer 8, in the third via hole, and in the second via hole A layer of transparent conductive film is deposited in the first via hole, and the transparent conductive film covers the conductive compensation block 10, specifically including: a transparent conductive film located on the upper surface of the second passivation layer 8, located in the third via hole, the first The transparent conductive film in the second via hole, in the first via hole and on the conductive compensation block 10 makes the second transparent electrode layer 9 electrically connected to the source and drain layer 4 through the conductive compensation block 10 .

In the above embodiment, the conductive compensation block 10 is formed simultaneously with the first transparent electrode layer 7, but it is not limited thereto, it can also be formed by performing plasma treatment on the second passivation layer 8, specifically, please refer to Fig. 6a and Fig. 6b and Fig. 6c, wherein, Fig. 6a is a cross-sectional view of the pixel structure when the second passivation layer has a two-layer structure; Fig. 6b is a cross-sectional view of the pixel structure after etching the upper structure of the second passivation layer; Fig. 6c is a cross-sectional view of the second passivation layer A cross-sectional view of the pixel structure after the plasma treatment of the lower structure of the second passivation layer. After the first transparent electrode layer 7 is formed on the resin layer 6 through a patterning process, a second transparent electrode layer 7 is formed on the first transparent electrode layer 7, on the resin layer 6 and in the first via hole and the second via hole. The passivation layer 8, the second passivation layer 8 includes: a transparent oxide layer 81 formed on the first transparent electrode layer 7, on the resin layer 6, in the first via hole, and in the second via hole, formed on the transparent oxide layer Silicon nitride layer 82 on 81. The concrete manufacturing process of this second passivation layer 8 comprises:

A transparent oxide layer 81 is formed on the first transparent electrode layer 7 and the resin layer 6 and in the first via hole and the second via hole. The transparent oxide layer 81 can be indium tritium zinc oxide (ITZO), indium gallium zinc oxide ( IGZO), zinc oxide (ZnO) and other materials are made by sputtering deposition. Selecting appropriate parameters during deposition can obtain an insulating transparent oxide film. For example, when indium gallium zinc oxide (IGZO) is used, the deposition The gas uses oxygen (O ₂ ), and when the oxygen content is 60-200 sccm, an insulating indium gallium zinc oxide (IGZO) transparent oxide film layer can be obtained.

Form a silicon nitride layer 82 on the transparent oxide layer 81; through masking, etching, and stripping processes, form a third via hole communicating with the transparent oxide layer 81 in the area of the silicon nitride layer 82 corresponding to each first via hole ; Through the plasma treatment process, the area corresponding to the transparent oxide layer 81 and the first via hole becomes a conductor, and the conductor is the conductive compensation block 10 . The thickness of the above-mentioned transparent oxide layer 81 is generally 600-1500 Å, and the thickness of the silicon nitride layer 82 is generally 300-1000 Å. Preferably, the thickness of the transparent oxide layer 81 is 1000 Å, and the thickness of the silicon nitride layer 82 is 500 Å. The first transparent electrode layer 9 is connected to the source-drain layer 4 through the conductor of the transparent oxide layer 81 .

It should be noted that plasma treatment can be carried out in dry etching (Dry Etch) equipment or plasma enhanced chemical vapor deposition (PEVCD) equipment, which is well known to those skilled in the art, so the specific process of plasma treatment will not be described here. Describe in detail.

It can be seen from the above technical solution that in the method for manufacturing the pixel structure provided by the embodiment of the present invention, seven patterning processes are used to fabricate the pixel structure, which reduces mask The number of templates used simplifies the production process, thereby improving the yield rate of the pixel structure substrate; in addition, the second via hole can be formed on the resin layer 6 by one patterning process, and the second via hole can be formed on the first passivation layer 5. The first via hole does not need the third via hole and the second via hole to carry out a certain offset distance to form the half contact of the second transparent electrode layer 9 and the source drain layer 4, and the first via hole can be connected to the second via hole. The via holes are directly opposite each other, and the saved offset distance is very beneficial to the mask design, thereby facilitating the fabrication of an array substrate with high resolution.

To sum up, in the pixel structure provided by the embodiment of the present invention, the second transparent electrode layer is electrically connected to the source-drain layer through the conductive compensation block through the addition of a conductive compensation block in the first via hole, so as to The probability of disconnection of the second transparent electrode layer deposited in the first via hole is reduced, that is, the probability of disconnection of the second transparent electrode layer and the source-drain layer is reduced, thereby improving the quality of the array substrate.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (10)

1. A pixel structure, comprising: a base substrate provided with a source-drain layer, a first passivation layer covering the source-drain layer, and the first passivation layer having a structure communicating with the source-drain layer The first via hole, the resin layer covering the first passivation layer, the resin layer has a second via hole corresponding to the first via hole, the first transparent electrode layer disposed on the resin layer , a second passivation layer located on the resin layer and covering the first transparent electrode layer, the second passivation layer has a third via hole corresponding to the second via hole; characterized in that, include: a conductive compensation block disposed in the first via hole; a second transparent electrode layer disposed on the second passivation layer, in the third via hole, in the second via hole and in the first via hole; the second transparent electrode layer passes through the The conductive compensation block is electrically connected to the source-drain layer; The second passivation layer includes: a transparent oxide layer disposed on the resin layer, the first transparent electrode layer, the first via hole and the second via hole, and disposed on the transparent a silicon nitride layer on the oxide layer; The thickness of the conductive compensation block is equal to the thickness of the transparent oxide layer. 2. The pixel structure according to claim 1, wherein the thickness of the conductive compensation block, the thickness of the second transparent electrode layer, and the thickness of the first passivation layer satisfy the following relationship: T1+T2≥T3 Wherein, T1 is the thickness of the conductive compensation block, T2 is the thickness of the second transparent electrode layer, and T3 is the thickness of the first passivation layer. 3. The pixel structure according to claim 1, wherein the thickness of the conductive compensation block, the thickness of the second transparent electrode layer, and the thickness of the first passivation layer satisfy the following relationship: T1+T2≥1.4×T3 Wherein, T1 is the thickness of the conductive compensation block, T2 is the thickness of the second transparent electrode layer, and T3 is the thickness of the first passivation layer. 4. The pixel structure according to any one of claims 1-3, wherein the conductive compensation block is an indium tin oxide compensation block, a molybdenum compensation block or a molybdenum aluminum alloy compensation block. 5. The pixel structure according to claim 1, further comprising: a gate layer, a gate insulating layer and an active layer located between the base substrate and the source-drain layer; wherein, The gate layer is disposed on the base substrate; The gate insulating layer covers the gate layer; The active layer is disposed on the gate insulating layer. 6. An array substrate, comprising: a plurality of pixel structures according to any one of claims 1-5. 7. A display device, comprising the array substrate according to claim 6. 8. A method for manufacturing a pixel structure, comprising: A patterned gate layer is formed on the upper surface of the base substrate through a patterning process; forming a gate insulating layer covering the gate layer; forming a patterned active layer on the upper surface of the gate insulating layer through a patterning process; forming a source-drain layer covering the active layer through a patterning process; Through a patterning process, a patterned first passivation layer and a patterned resin layer are formed; wherein, the first passivation layer covers the source and drain layers, and the first passivation layer has the same a first via hole communicating with the source-drain layer; the resin layer is disposed on the upper surface of the first passivation layer, and the resin layer has a second via hole corresponding to the first via hole; A patterned first transparent electrode layer is formed on the upper surface of the resin layer through a patterning process, and a conductive compensation block is formed in the first via hole; A second passivation layer covering the resin layer and the first transparent electrode layer is formed through a patterning process, and the second passivation layer has a third via hole corresponding to the second via hole; A second transparent electrode layer is formed on the upper surface of the second passivation layer, in the third via hole, in the second via hole and in the first via hole through one patterning process, so that The second transparent electrode layer is electrically connected to the source-drain layer through the conductive compensation block. 9. The method for manufacturing a pixel structure according to claim 8, wherein a patterned first passivation layer and a patterned resin layer are formed through one patterning process, specifically comprising: coating a passivation material on the source-drain layer to form a first passivation layer; Coating resin on the first passivation layer to form a resin layer; A second via hole is formed on the resin layer through masking, etching, and stripping procedures, and a first via hole is formed on the first passivation layer, and the first via hole corresponds to the second via hole. 10. A method for manufacturing a pixel structure, comprising: A patterned gate layer is formed on the upper surface of the base substrate through a patterning process; forming a gate insulating layer covering the gate layer; forming a patterned active layer on the upper surface of the gate insulating layer through a patterning process; forming a source-drain layer covering the active layer through a patterning process; Through a patterning process, a patterned first passivation layer and a patterned resin layer are formed; wherein, the first passivation layer covers the source and drain layers, and the first passivation layer has the same a first via hole communicating with the source-drain layer; the resin layer is disposed on the upper surface of the first passivation layer, and the resin layer has a second via hole corresponding to the first via hole; forming a first transparent electrode layer on the resin layer through a patterning process; A second passivation layer is formed on the first transparent electrode layer, on the resin layer, in the first via hole and in the second via hole, and the second passivation layer includes: formed on the A transparent oxide layer on the first transparent electrode layer, on the resin layer, in the first via hole, and in the second via hole, and a silicon nitride layer formed on the transparent oxide layer; Forming a third via hole in communication with the transparent oxide layer in a region of the silicon nitride layer corresponding to the first via hole through a mask and etching process; Through a plasma treatment process, the area of the transparent oxide layer corresponding to the first via hole becomes a conductor, and the conductor is the conductive compensation block; Through one patterning process, on the upper surface of the second passivation layer, on the inner wall of the third via hole, on the inner wall of the second via hole, on the inner wall of the first via hole and on the conductive compensation A second transparent electrode layer is formed on the block, and the second transparent electrode layer is electrically connected to the source-drain layer through the conductive compensation block.