CN103531239A - Memory erasing method and driving circuit thereof - Google Patents

Abstract

The invention provides a memory erasing method and a driving circuit thereof, and the main technical scheme comprises the following steps: when the memory cell is selected to be erased, setting the gates of a plurality of memory cells to be erased in the selected memory block, the drains of all memory cells in the selected memory pile and the gates of a plurality of unselected memory cells to be floating; providing a positive voltage to all sources of the selected memory stack and the shared P-well and N-well; a negative voltage is provided to the gates of a plurality of memory cells in the memory block that are selected to be erased. Therefore, the grid floating can receive the coupling voltage from the positive electricity of the P-type well, the erasing inhibition of a plurality of unselected memory blocks is achieved, the decoding is more simplified, and the expansion of more memory blocks or memory stacks and the division of memory sections in the memory blocks are easily achieved by using a smaller layout area.

Description

Memory erasing method and its driving circuit

technical field

The present invention relates to a NOR flash memory (NOR FLASH MEMORY), and in particular to a memory erasing method suitable for NOR flash memory, and a driving circuit for implementing the memory erasing method.

Background technique

With the progress of semiconductor technology, the capacity of memory is getting bigger and bigger, and its speed is getting faster and faster. Or non-type flash memory is currently widely used in electronic products, or non-type memory will have multiple storage banks (BANK), and each storage bank has multiple storage blocks (BLOCK), each storage bank It has multiple memory cells arranged in rows and columns. Generally speaking, multiple storage units in each storage block can share a P-type well (P WELL) and an N-type well (N WELL). When erasing multiple memory cells on a certain column in a certain memory block, traditionally, an erasing voltage (generally a relatively large positive voltage, such as 8V) will be applied to the P-type well, and a A negative voltage (generally a relatively large negative voltage, such as -9V) is applied to the gates of the memory cells in the column, thereby erasing data in the memory cells. However, in the same memory block, since the gates of the memory cells in the remaining columns that do not want to be erased must be applied with a system power supply voltage or a positive voltage lower than the erasing voltage (generally a lower positive voltage , such as VCC or 3V), such an operation will cause erasure disturbance (ERASE DISTURB) during the erasing process.

Generally speaking, smaller memory blocks can have a better ability to suppress erasure disturbances, but relatively, the more memory blocks are divided, the larger the chip size. Therefore, NOR flash memory is currently in the large Some applications are limited to, for example, erasing 4K bits (ie, a sector (SECTOR)) or 64K bits (ie, a block) at a time. In addition, there is still no optimal design method proposed for erasing disturbances. Therefore, for a memory that must be configured with a fixed number of ranks, in order to reduce erase disturbances, it is necessary to divide the ranks into more storage blocks or storage segments. Furthermore, to be divided into more memory blocks or memory segments, more power exchange decoding circuits and driving circuits are required to generate corresponding voltage signals, which leads to an increase in chip size.

Please refer to FIG. 1 and FIG. 2 , FIG. 1 is a schematic diagram of the configuration of storage stacks of flash memory; and FIG. 2 is a circuit block diagram of a traditional NOR flash drive circuit in the area of FIG. 1A . The traditional NOR flash memory has multiple driving circuits, and each driving circuit 10 is disposed between two adjacent corresponding storage blocks (eg, BLOCK_n) of two adjacent storage banks (eg, BANK_0, BANK_1). The driving circuit 10 includes a word line driving circuit WL_DRIVER, two block P-well voltage supply circuits BGPW1 and BGPW2, sixteen negative voltage supply circuits VNNI_X16 and a bit line driving circuit YDSL_DRIVER. Generally speaking, each storage segment has 4K bits (that is, a storage segment has 4K storage units), and each storage block (such as: BLOCK_0, BLOCK_1) has sixteen storage segments (that is, A storage block has 64K storage units). The word line driving circuit WL_DRIVER generally has a plurality of word line pre-drivers WL_pre_Driver, and each word line pre-driver WL_pre_Driver is used to drive the corresponding sixteen left word lines LWL_X16 and sixteen right word lines RWL_X16 to drive the corresponding The corresponding storage units in two adjacent storage blocks (for example: BLOCK_n).

The two block P-well voltage supply circuits BGPW1 and BGPW2 receive system power supply Y_POWER to respectively provide positive voltages to the P-well and N-well corresponding to the two adjacent memory blocks BLOCK_n. The word line driving circuit WL_DRIVER receives sixteen power sources X_POWER_X16 from a power exchange decoding circuit (not shown in the figure), and generates sixteen word line driving signals to gates of a plurality of memory cells in a plurality of columns accordingly. The bit line driving circuit YDSL_DRIVER receives the system power Y_POWER and is used to drive a plurality of bit lines YBL corresponding to two adjacent memory blocks BLOCK_n. Each of the sixteen negative voltage supply circuits VNNI_X16 receives the negative voltage VNNG, and generates sixteen negative voltages to the word line drive circuit WL_DRIVER according to the negative voltage VNNG, so as to control the sixteen storage segments of the two storage blocks BLOCK_n The selected character lines are erased.

When erasing a plurality of memory cells in a certain column in a certain storage segment, the word line driver circuit WL_DRIVER will supply a negative voltage to the word line in this column, wherein the word line in this column is connected to a plurality of memory cells in this column the grid. At the same time, in the memory blocks to which the memory cells to be erased belong, the word lines to which the memory cells not to be erased belong are supplied with the system power supply voltage. In addition, if there is no memory cell to be erased in the memory block, the word lines of the memory block are all applied with the ground voltage (0V) supplied by the word line driving circuit WL_DRIVER.

In traditional NOR flash memory, a driving circuit 10 is arranged in the space between corresponding two adjacent storage blocks in two adjacent storage piles, and the space for configuring the driving circuit 10 is shown as BLOCK_0 and BLOCK_1 in FIG. 1 , and the long space between BLOCK_2 and BLOCK_3, therefore, based on the premise of reducing erase disturbance, the NOR flash memory will have more storage blocks or storage segments. Too many suppression voltage circuits and the division of storage segments will make the word line drive circuit too complicated. If you want to expand more storage blocks or storage stacks, you must repeatedly configure the drive circuit of the traditional NOR flash memory, so That is, the occupied area will be increased.

Contents of the invention

An object of the present invention is to make the memory erasing method and its drive circuit decoding more compact, and it is easier to achieve more storage blocks or storage heap expansion with a smaller layout area, and to increase the storage area in the storage block Segmentation.

For reaching above-mentioned purpose and other purpose, the present invention provides a kind of method of erasing memory, when a plurality of storage cells of a column of a storage block of a storage heap are selected to erase, this method of erasing memory comprises: will be selected Gates of memory cells not selected to be erased under the memory block, drains of all memory cells under the selected memory stack, and unselected memory areas under the selected memory stack The gate of each memory cell of the block is set to float; a positive voltage is provided to the source electrodes of all memory cells under the selected memory stack, a shared P-type well and an N-type well; and providing A negative voltage is applied to the gates of the memory cells to be erased in the column of the selected memory block.

In order to achieve the above-mentioned purpose and other purposes, the driving circuit provided by the present invention includes a plurality of groups of adjacently configured storage piles, a main driving circuit is arranged in two adjacent corresponding storage blocks of one group of storage piles, and the storage piles of the remaining groups Two adjacent corresponding memory blocks are each equipped with a sub-drive circuit, the main drive circuit includes: a global word line driver, used to receive a power source from a power exchange decoding circuit, and generate a plurality of global word lines accordingly. The word line signal and its reverse global word line signal; two extended first area word line drivers are used to receive the global word line signal and its reverse global word line signal, and receive another signal from the power exchange decoding circuit A power source, and accordingly generate and provide the voltages of the word lines adjacent to the two memory blocks; a global negative voltage supply circuit, used to receive a reference negative voltage, and provide a negative voltage to the extensions type first regional word line driver; and a first bit line driver circuit for driving the bit lines of the two adjacent memory blocks. The secondary drive circuit includes: an extended second area word line driver for receiving the global word line signals and their reverse global word line signals, and receiving another power source from the power exchange decoding circuit, And accordingly generate and provide the voltages of the word lines of the adjacent storage block; and a second bit line driving circuit for driving the bit lines of the adjacent storage block.

To sum up, the present invention provides a memory erasing method and a driving circuit for implementing the memory method. By using the driving method of the present invention, the circuit complexity can be simplified and the erasing disturbance can be better suppressed. The driving circuit of the present invention and the matching sub-driving circuit can increase multiple rows and multiple columns of the NOR flash memory by using the expansion of the sub-driving circuit, without using two adjacent storage areas of two adjacent storage stacks The areas occupied by the driving circuits between the blocks must be the same, which greatly simplifies the circuit complexity and reduces the area occupied by the circuits.

Description of drawings

FIG. 1 is a schematic diagram of configuration among storage heaps of a flash memory.

FIG. 2 is a circuit block diagram of a traditional NOR flash drive circuit in the area of FIG. 1A .

FIG. 3 is a flowchart of a memory erasing method provided by an embodiment of the present invention.

FIG. 4 is a schematic configuration diagram of a memory stack of a flash memory in an embodiment of the present invention.

FIG. 5 is a circuit block diagram of a driving circuit for implementing the erasing method in FIG. 3 in an embodiment of the present invention.

FIG. 6 is a circuit block diagram of a driving circuit for implementing the flow method of FIG. 3 in another embodiment of the present invention.

7A, 7B, and 7C are schematic diagrams of operations of the extended area word line driver in different states during the erasing process according to an embodiment of the present invention.

Figure number:

10 drive circuit

30 Main drive circuit

40 Auxiliary drive circuit

A, A' area

B, B' area

BANK_0~3 storage heap

BLOCK_1～3 storage block

WL_DRIVER Character Line Driver Circuit

WL_pre_Driver Character line pre-driver

LWL_X16 left character line

RWL_X16 Right Character Line

X_POWER_X16 power supply

BGPW1, BGPW2 block P-type well voltage supply circuit

VNNI_X16 Negative voltage supply circuit

YDSL_DRIVER bit line drive circuit

Y_POWER System Power

YBL bit line

VNNG Negative voltage

S20, S22, S24 steps

L_WL_DRIVER Extended area word line driver

GBGVNN global negative voltage supply circuit

GBGVNNC Negative voltage

GWL Global character line signal

GWLB reverse global character line signal

G_WL_DRIVER global character line driver

XDC16 regional character line drive unit

GWL_UNIT global character line drive unit

BKVNN storage stack negative pressure signal

N1~N3 Transistor

Detailed ways

In order to fully understand the purpose, characteristics and effects of the present invention, the present invention will be described in detail through the following specific embodiments, and in conjunction with the accompanying drawings, as follows:

In order to expand multiple rows and multiple columns of the NOR flash memory more easily to increase the capacity of the NOR flash memory without excessively increasing the chip size, the present invention provides a method for erasing memory and implementing the memory method By using the driving circuit of the present invention, multiple rows and multiple columns of the NOR flash memory can be increased without greatly increasing the chip size.

First, please refer to FIG. 3 . FIG. 3 is a flow chart of a memory erasing method provided by an embodiment of the present invention. The NOR flash memory has multiple storage piles, each storage pile has multiple storage blocks, each storage block has multiple storage units, and these storage units are arranged in multiple rows and multiple columns, and each word line is connected To the gates of multiple memory cells in the corresponding column, each regional bit line is connected to the drains of multiple memory cells in the corresponding row, and the sources of multiple memory cells in each row are connected to a global through multiple selection transistors bit line.

Wherein, when a plurality of storage units in a row in a storage block of a storage heap are selected to be erased, the NOR flash memory will be executed with a memory erasing method. In step S20, the following parts (A), (B), and (C) are set to floating, wherein (A), under the selected storage block, a plurality of data not selected to be erased Gate in the memory cell; (B), under the selected memory stack, the drains of all memory cells; (C), under the selected memory stack, each memory cell in all unselected memory blocks the grid.

Then proceed to step S22, providing a positive voltage (for example: 8V) to the sources of all memory cells in all memory blocks under the selected memory stack, and providing a positive voltage (for example: 8V) to the shared P-type well and N-type well. Step S24 is: providing a negative voltage (for example: -9V) to the gates of a plurality of memory cells to be erased under the column of the selected memory block. In general, in the selected memory block, the floating gates of the memory cells in the unselected columns have a voltage lower than the positive voltage of the P-type well (for example, are floated The gate voltage is about 4V). It should be noted that the execution order of the above-mentioned steps S20, S22 and S24 is not intended to limit the present invention. Steps S22 and S24 are preferably implemented at the same time. In addition, steps S22 and S24 can also be performed before step S20, or three steps implemented simultaneously.

In addition, the erasing method in FIG. 3 also includes other steps, which are performed before steps S20 and S22. This step provides a driving circuit between two adjacent storage blocks of two adjacent storage stacks, the driving circuit is used to provide a negative voltage, and is responsible for multiple unselected storage blocks under the storage block to be selected. The gates of the erased memory cells are set to float.

Next, please refer to FIG. 4 , which is a schematic diagram of the configuration of the memory stack of the flash memory in an embodiment of the present invention, which is on both sides of the main drive circuit (that is, the occupied space is similar to that of the existing drive circuit), so that the occupied circuit area is small The sub-driver circuit (A' area) is used to replace the existing global word line driver which is repeatedly configured, so as to reduce the configuration space required for the drive circuit in the existing flash memory. In other words, the driving circuit in the embodiment of the present invention includes multiple sets of memory banks arranged adjacently, for example: a set of BANK_0 and BANK_1, a set of BANK_1 and BANK_2, and a set of BANK_2 and BANK_3. A main drive circuit (with a global word line driver and two extended area word line drivers) is arranged in two adjacent corresponding memory blocks of a group of memory banks (BANK_1, BANK_2), and in the memory banks of the remaining groups (BANK_0 and BANK_1, BANK_1 and BANK_2) are each configured with a secondary driver circuit (with only one extended area word line driver). That is, in the embodiment of the present invention, one main driving circuit is matched with several auxiliary driving circuits. Each memory bank needs to be configured with one extended area word line driver, and at the same time, one global word line driver in the main driving circuit is configured to drive all the extended area word line drivers. For example: if there are 4 memory banks, you need 1 main drive circuit (with 1 global word line driver), and 4 extended area word line drivers (including: 2 extended area word line drivers in the main drive circuit) line driver, and the respective extended area word line driver in the 2 sub-drive circuits); if there are 8 memory banks, only 1 main drive circuit (with 1 global word line driver) is still required, and the collocation 8 extended area word line drivers (2 extended area word line drivers in the main driving circuit, and respective extended area word line drivers in the 6 sub driving circuits).

5 is a circuit block diagram of a driving circuit for realizing the erasing method in FIG. 3 in an embodiment of the present invention, and at the same time, it is a circuit block diagram representing the present invention under the B' region of FIG. 4 . NOR flash includes multiple memory stacks and multiple drives. Each storage pile has a plurality of storage blocks, each storage block has a plurality of storage units, and the storage units are arranged in a plurality of rows and a plurality of columns. Each word line is connected to the gates of a plurality of memory cells in a corresponding column, each regional bit line is connected to the drains of a plurality of memory cells in a corresponding row, and the sources of a plurality of memory cells in each row are selected by a plurality of The transistor is connected to a global bit line. The driving circuit of the present invention includes a main driving circuit 30 and a secondary driving circuit 40 .

As shown in FIG. 5, each main driving circuit 30 is configured between two adjacent memory blocks BLOCK_n and BLOCK_n (for example: BANK_1 of BANK_1) of two adjacent memory banks (BANK_1 and BANK_2 shown in FIG. 4 ). BLOCK_1 and BLOCK_1 of BANK_2), the main driving circuit 30 includes a global word line driver G_WL_DRIVER, two extended local word line drivers L_WL_DRIVER, a global negative voltage supply circuit GBGVNN and a bit line driving circuit YDSL_DRIVER. The two extended area word line drivers L_WL_DRIVER are used to receive the global word line signal GWL and the reverse global word line signal GWLB, and receive two power sources X_POWER_X16 from the power exchange decoding circuit (not shown in the figure), and generate A plurality of word lines LWLX_16 and RWLX_16 providing voltages to two adjacent memory blocks. The global negative voltage supply circuit GBGVNN is used for receiving the reference negative voltage VNNG, and providing the negative voltage GBGVNNC to the extended local word line drivers L_WL_DRIVER and the global word line driver G_WL_DRIVER. The bit line driving circuit YDSL_DRIVER receives the system voltage Y_POWER and is used to drive a plurality of bit lines YBL of two adjacent memory blocks BLOCK_1 and BLOCK_2.

The global word line driver G_WL_DRIVER is used to receive another power source X_PLUS_POWER from the power exchange decoding circuit, and accordingly generate the global word line signal GWL and the reverse global word line signal GWLB to the two extended local word line drivers L_WL_DRIVER. The embodiment of the present invention is to make the NOR flash memory add more storage blocks under the same storage pile, and its way is to copy the extended type regional word line driver L_WL_DRIVER, and to set it on the phase of every two adjacent storage piles BANK_0, BANK_1 A secondary driver circuit 40 without a global word line driver G_WL_DRIVER is arranged between two adjacent memory blocks BLOCK_n and BLOCK_n (see FIG. 6 ).

Fig. 6 is a circuit block diagram of a driving circuit for realizing the flow method of Fig. 3 in another embodiment of the present invention, and Fig. 6 is a circuit block diagram of the present invention representing the B' region of Fig. 4 . Through the architecture of the embodiment of the present invention shown in FIG. 5, when the NOR flash memory needs to add storage banks, only two adjacent corresponding storage areas of two adjacent storage banks BANK_0 and BANK_1 (see FIG. 4) are required. The sub-driver circuit 40 mentioned above may be copied between blocks BLOCK_n and BLOCK_n (for example: BLOCK_1 of BANK_1 and BLOCK_1 of BANK_0). The extended area word line driver L_WL_DRIVER between two adjacent memory blocks BLOCK_n and BLOCK_n of two adjacent memory banks BANK_0 and BANK_1 receives the negative voltage GBGVNNC provided by the global negative voltage supplier GBGVNN, and the global word line driver G_WL_DRIVER The output global word line signal GWL and its reverse global word line signal GWLB. Each bank also receives a bank negative voltage signal BKVNN (not shown in the figure) for supplying 0 or negative voltage operation. Compared with traditional or non-flash memory drivers, the main driver circuit 30 and the auxiliary driver circuit 40 only use a single global negative voltage supplier GBGVNN, a smaller global word line driver G_WL_DRIVER and an extended area word line driver L_WL_DRIVER, therefore, the overall The drive circuit size can be greatly reduced. In this way, if the architecture provided by the embodiments of the present invention is used, it is easier to achieve expansion of more memory blocks or memory heaps with a smaller layout area. How many extended area word line drivers L_WL_DRIVER can be coupled to a main driving circuit 30 depends on factors such as the driving capability, load, and operating speed of the global word line driver G_WL_DRIVER, which belongs to the prior art and can be easily adopted by those skilled in the art. Suitable global word line driver G_WL_DRIVER.

Please continue to refer to FIG. 6, each extended area word line driver L_WL_DRIVER can have sixty-four area word line drive units XDC16, each area word line drive unit XDC16 receives power X_POWER_X16, negative voltage GBGVNNC, global word line signal GWL and its Invert the global word line signal GWLB, and generate sixteen word line voltages accordingly. Similarly, the global word line driver G_WL_DRIVER includes sixty-four global word line drive units GWL_UNIT, each global word line drive unit GWL_UNIT corresponds to two regional word line drive units XDC16, and generates a corresponding global word line signal GWL and its inverse The global word line signal GWLB is sent to the corresponding two regional word line drive units XDC16. The regional word line driving unit XDC16 can have three transistors connected in series during implementation, however, when the breakdown voltage of the first transistor is high enough, the regional word line driving unit XDC16 can only have two transistors connected in series, and can even be used directly single transistor.

When a plurality of memory cells in a column of a memory block of one of the adjacent two memory banks BANK_0 and BANK_1 are selected and erased, the corresponding extended area word line driver L_WL_DRIVER applies a negative voltage to the selected memory area The word lines corresponding to the gates of the plurality of memory cells to be erased in the column of the block, and the corresponding extended area word line driver L_WL_DRIVER will be selected under the memory block that is not selected to be erased The gates of each memory cell are floating, and the sources of all memory cells under the selected memory stack, the shared P-type well and N-type well are all applied with a positive voltage, and all memory cells under the selected memory stack The drains of the cells and the gates of the plurality of memory cells of all unselected memory blocks under the selected memory bank are set to float.

The above global word line driver G_WL_DRIVER generates and provides the global word line signal GWL and the reverse global word line signal GWLB to each extended area word line driver L_WL_DRIVER according to the power source X_PLUS_POWER from the power exchange decoding circuit to achieve character The goal of line-wide decoding. In addition, the above-mentioned P-type wells of each memory stack are commonly connected to a positive voltage, which can reduce the complexity of having to generate positive voltages separately for the P-type wells of each memory segment.

Next, please refer to FIG. 7A , FIG. 7B , and FIG. 7C , which are schematic diagrams of operations of the extended area word line driver in different states during the erasing process according to an embodiment of the present invention. It is the case when the memory cells of one column of one memory block of one memory heap are selected to be erased.

Fig. 7A shows the situation that in the column of the selected memory block, the extended area word line driver applies a voltage to the word lines of the memory cells to be erased, and the extended area word line is selected by the power supply X_POWER_X16 The driver L_WL_DRIVER supplies voltage to determine the word lines of the memory cells to be erased. In this case, the global word line signal GWL is operated as a negative voltage (-HV), for example: -9V; the reverse global word line signal GWLB and the memory stack negative voltage signal BKVNN are operated as a ground voltage (zero voltage ), the global negative voltage supply circuit GBGVNN is operated to make the output voltage a negative voltage GBGVNNC. As for the P-type well (not shown), it is supplied with positive voltage as in the prior art. Accordingly, for the word lines of the memory cells to be erased, the corresponding extended local word line driver L_WL_DRIVER outputs a negative voltage to the gates of the word lines of the memory cells to be erased.

Fig. 7B shows the situation that the extended area word line driver applies voltage to the word lines of the memory cells that are not erased under the selected memory block, and the selected extended area word line driver L_WL_DRIVER is supplied by the power supply X_POWER_X16 voltage to determine the word lines of these memory cells not to be erased. In this case, the global word line signal GWL is operated as a negative voltage (-HV), for example: -9V; the reverse global word line signal GWLB and the memory stack negative voltage signal BKVNN are operated as a ground voltage (zero voltage ), the global negative voltage supply circuit GBGVNN is operated to make the output voltage a negative voltage GBGVNNC. As for the P-type well (not shown), it is supplied with positive voltage as in the prior art. Thereby, for the word lines of the memory cells not to be erased, the corresponding extended area word line driver L_WL_DRIVER will output a restricted voltage (inhibit voltage) to the word lines of the memory cells not to be erased. gate, so that the gate in this case is set to float.

FIG. 7C shows the situation that the extended area word line driver applies voltage to the unselected storage blocks under the selected memory stack, and the selected extended area word line driver L_WL_DRIVER supplies voltage through the power supply X_POWER_X16, to determine the word lines of the memory cells of the memory blocks that are not selected. In this case, the global word line signal GWL, the inverted global word line signals GWLB, BKVNN, and the global negative voltage supply circuit GBGVNN are operated as ground voltage (zero voltage). As for the P-type well (not shown), it is supplied with positive voltage as in the prior art. Thereby, for the word lines of the memory cells of the unselected memory blocks under the selected memory stack, the corresponding extended area word line driver L_WL_DRIVER will output a restricted voltage (inhibit voltage) The gates in the word lines of these memory cells are not erased, so that the gates in this case are set to float. Similarly, in this case, the drains of all the memory cells under the selected memory stack are also applied with a voltage in the manner shown in FIG. 7C , so that the drains in this case are also set to float.

The aforementioned extended area word line driver L_WL_DRIVER in FIG. 7A, FIG. 7B, and FIG. 7C is an example of three transistors N1, N2, and N3, such as n-type transistors. Those skilled in the art should understand that these transistors are only As an example, other circuit arrangements capable of achieving the aforementioned signal operations can also implement the present invention without departing from the scope of the present invention.

To sum up, the present invention provides a memory erasing method and a driving circuit for implementing the memory method. When the gate is floating, it receives the coupling voltage from the positive electrode of the P-type well to achieve a plurality of unselected memories. The block erasure suppression makes the decoding more streamlined, and it is easy to achieve more storage blocks or expansion of the storage heap and division of the storage segments in the storage block with a smaller layout area. The main drive circuit and the matched auxiliary drive circuit of the present invention can increase multiple rows and multiple columns of the NOR flash memory by using the expansion of the extended area word line driver L_WL_DRIVER, without constantly repeating the configuration of the global word line driver G_WL_DRIVER , which can greatly simplify the circuit complexity and reduce the chip area occupied by the circuit, and also have a better suppression ability for erasure disturbance.

The present invention has been disclosed above with preferred embodiments, but those skilled in the art should understand that the embodiments are only used to describe the present invention and should not be construed as limiting the scope of the present invention. It should be noted that all changes and substitutions equivalent to this embodiment should be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined in the claims.

Claims (5)

1. an internal memory erasing method, is characterized in that, when selected the erasing of a plurality of storage unit of row of a memory block of a memory heap, described internal memory erasing method comprises:

By the grid of the selected storage unit that will be erased under selecteed described memory block, the drain electrode of all storage unit under selecteed described memory heap and the grid of each storage unit of the non-selected memory block under selecteed described memory heap, be made as and float;

The source electrode of one positive voltage to all storage unit under selecteed described memory heap, a p type wells of being shared and a N-type well are provided; And

The grid of described these storage unit of wanting to erase under the described row of one negative voltage to selecteed described memory block is provided.

2. one kind for carrying out the driving circuit of internal memory erasing method as claimed in claim 1, it is characterized in that, be applied to an or/no type flash memory, described driving circuit comprises the memory heap of many group disposed adjacent, in the adjacent two corresponding stored blocks of one group of memory heap, configure a main driving circuit, adjacent two corresponding stored blocks in the memory heap of all the other groups are respectively configured a secondary driving circuit, and described secondary driving circuit comprises:

One extended second area novel word-line driver design for pseudo two-port, a plurality of universe character line signal universe character line reverse with it signal producing in order to receive described main driving circuit, and provide to the voltage of the character line of described two memory block adjacent with described extended second area novel word-line driver design for pseudo two-port in order to produce; And

One second line drive circuit, in order to drive the bit line of described two memory block adjacent with described extended second area novel word-line driver design for pseudo two-port.

3. driving circuit as claimed in claim 2, is characterized in that, described main driving circuit comprises:

One universe novel word-line driver design for pseudo two-port, in order to produce described a plurality of universe character line signal universe character line reverse with it signal;

Two extended first area novel word-line driver design for pseudo two-port, in order to receive universe character line signal universe character line reverse with it signals such as described, and provide to the voltage of the character line of described two memory block adjacent with described extended first area novel word-line driver design for pseudo two-port in order to produce;

One universe negative voltage supply circuit, in order to receive one with reference to negative voltage, and provides a negative voltage to described two extended first area novel word-line driver design for pseudo two-port; And

One first bit line drive circuit, in order to drive the bit line of described two memory block adjacent with described extended first area novel word-line driver design for pseudo two-port.

4. a driving circuit, it is characterized in that, be applied to an or/no type flash memory, described or/no type flash memory has a plurality of memory heaps, each memory heap has a plurality of memory block, each memory block has a plurality of storage unit, two adjacent memory heaps are one group, described these memory cell arrangements become a plurality of row and a plurality of row, each character line is connected to the grid of described these storage unit of corresponding described row, each region bit line is connected to the drain electrode of described these storage unit of corresponding described row, the source electrode of described these storage unit of every number row is connected to a universe bit line by a plurality of selection transistors, described driving circuit comprises the main driving circuit in adjacent two memory block of adjacent two memory heaps that are disposed at a group, adjacent two memory block of adjacent described two memory heaps of all the other groups are respectively configured a secondary driving circuit, described secondary driving circuit comprises:

One extended second area novel word-line driver design for pseudo two-port, a plurality of universe character line signal universe character line reverse with it signal producing in order to receive described main driving circuit, and provide to the voltage of the character line of described two memory block adjacent with described extended second area novel word-line driver design for pseudo two-port in order to produce; And

One second line drive circuit, in order to drive the bit line of described two memory block adjacent with described extended second area novel word-line driver design for pseudo two-port.

5. driving circuit as claimed in claim 4, is characterized in that, described main driving circuit comprises:

One universe novel word-line driver design for pseudo two-port, in order to produce universe character line signal universe character line reverse with it signals such as described;

Two extended first area novel word-line driver design for pseudo two-port, in order to receive universe character line signal universe character line reverse with it signals such as described, and provide to the voltage of the character line of described two memory block adjacent with described extended first area novel word-line driver design for pseudo two-port in order to produce;

One universe negative voltage supply circuit, in order to receive one with reference to negative voltage, and provides a negative voltage to described two extended first area novel word-line driver design for pseudo two-port; And

One first bit line drive circuit, in order to drive the bit line of described two memory block adjacent with described extended first area novel word-line driver design for pseudo two-port.

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