CN103516471B - Without number of bit errors according to method of reseptance and device - Google Patents

Abstract

The invention discloses a method and device for receiving error-free data. Wherein, the method includes: detecting the predetermined number of phase values in the data eye diagram of the received data and the bit error values corresponding to the phase values; The edge of the clock is adjusted to the time position corresponding to the phase value of the center point of the data eye diagram, and the error-free data is received according to the adjusted associated clock. Through the present invention, it is possible to quickly perform error-free locking and receiving even when the data does not have enough jumps, thereby achieving the effect of greatly saving bit error testing time and improving testing efficiency.

Description

Error-free data receiving method and device

technical field

The present invention relates to the field of communications, in particular to a method and device for receiving data without error codes.

Background technique

As the market's requirements for communication system capacity continue to increase, the single-link rate of digital signals inside communication system equipment is also gradually increasing. For example, for transmission communication systems, the high-speed interface rate has increased from the initial 1.25Gbps to the current 11.3Gbps. Interface throughput increases exponentially. However, as the rate increases, more and more technical problems are encountered, among which the correct reception of high-speed data is the key technical difficulty.

In previous communication systems, the reception of high-speed data usually uses the serial-parallel (SERDES) transceiver inside the chip to recover the associated clock through Clock Data Recovery (CDR), relying on the rising edge of the clock and the data The relationship between the center position, to achieve error-free reception. But this must meet two conditions: 1. The received data must have enough jumps; 2. The number of data 0 and 1 must be basically balanced. Digital communication systems usually rely on the sending end to scramble the data for transmission, and the receiving end performs descrambling to receive the data. However, for ultra-high-speed optical communication transmission equipment and broadband wireless communication equipment, it is impossible to use the above methods. Please refer to Figure 1 and Figure 2. Figure 1 is a structural block diagram of a 100Gb/s wavelength division transmission system according to related technologies. Figure 1 2 is a structural block diagram of a broadband wireless communication system according to the related art.

In the system shown in Figure 1, due to the influence of dispersion and nonlinearity, the 100Gb/s WDM transmission system adopts high-speed digital signal processing (Digital Signal Process, referred to as DSP), coherent reception, forward error correction (Forward errorcorrection, referred to as For FEC) technology to restore optical transmission signals, the receiving end needs to convert the analog electrical signal into a digital signal through a high-speed analog-to-digital converter (Analog-to-Digital Converter, referred to as ADC), and transmit it to the chip through the SERDES link for further processing. deal with. Since the high-speed ADC sampling signal cannot self-scramble the sampled data, nor can it ensure that the data on each link has enough jumps, the system shown in Figure 2 also has a similar situation, so how the sampled data Receiving without errors is a huge problem.

At present, major communication equipment manufacturers are striving to gain the commanding heights in ultra-high-speed optical transmission systems and broadband wireless communication systems. Among them, the receiving side is the core part of the system. How to ensure stable performance, first of all, ensure data transmission within the system No bit errors.

In the existing technology, to ensure error-free transmission between links, the built-in CDR of the interface is generally used for data recovery, and then the parameters of the links are adjusted to achieve the best performance. However, this method does not apply to the above mentioned conditions. to the situation.

Aiming at the problem in the related art that it is difficult to receive the data sampled by the ADC without error, no effective solution has been proposed so far.

Contents of the invention

The present invention provides a method and device for receiving error-free data to at least solve the above problems.

According to one aspect of the present invention, a method for receiving data without error codes is provided, including: performing an associated clock edge detection on a predetermined number of phase values and error values corresponding to the phase values in the data eye diagram of the received data; As a result, the phase value of the center point of the data eye diagram is determined; the edge of the associated clock is adjusted to the time position corresponding to the phase value of the center point of the data eye diagram, and error-free data is received according to the adjusted associated clock.

Preferably, performing the edge detection of the associated clock on the predetermined number of phase values in the data eye diagram of the received data and the error value corresponding to the phase value, including: detecting the falling edge of the associated clock on the phase value and the error value; The rising edge detection of the associated clock is performed on the phase value and the error code value.

Preferably, detecting the falling edge of the associated clock on the phase value and the bit error value includes: when the value of the enable signal is 1, starting from the phase value of 0, performing the falling edge detection on the phase value and the bit error value; When the first phase jump point where the bit error value changes from non-zero to zero is detected, it is determined to perform rising edge detection.

Preferably, the rising edge detection of the associated clock for the phase value and the bit error value includes: starting from the first phase jump point, continuing to detect the rising edge of the phase value and the bit error value; when the bit error value is detected from When zero changes to a non-zero second phase jump point, it is determined that the detection result is normal; otherwise, it is determined that the detection result is abnormal.

Preferably, determining the center point of the data eye diagram according to the detection result includes: when the detection result is normal, calculating the phase value of the center point of the data eye diagram according to the first phase jump point and the second phase jump point; If it is abnormal, set the phase value of the center point of the data eye diagram to the preset default value.

Preferably, calculating the phase value of the center point of the data eye diagram according to the first phase jump point and the second phase jump point includes: calculating the phase value C of the center point of the data eye diagram according to the following formula: C=(A+B)/2 , where A is the phase value of the first phase jump point, and B is the phase value of the second phase jump point; or, C=mod[(A+Y+B)/2, Y], where A is The phase value of the first phase jump point, B is the phase value of the second phase jump point, and Y is a predetermined number of phase values.

According to another aspect of the present invention, there is provided an error-free data receiving device, including: a detection module, which is used to follow the predetermined number of phase values and the error values corresponding to the phase values in the data eye diagram of the received data Clock edge detection; a determination module, used to determine the phase value of the center point of the data eye diagram according to the detection result; a processing module, used to adjust the edge of the associated clock to the time position corresponding to the phase value of the center point of the data eye diagram, according to the adjusted The associated clock receives error-free data.

Preferably, the detection module includes: a first detection module for detecting the falling edge of the associated clock for the phase value and the error value; a second detection module for rising the associated clock for the phase value and the error value edge detection.

Preferably, the first detection module includes: a first detection unit, which is used to detect the falling edge of the phase value and the bit error value starting from the phase value 0 when the value of the enable signal is 1; the first determination unit, It is used for determining to perform rising edge detection when the first phase jump point where the bit error value changes from non-zero to zero is detected.

Preferably, the second detection module includes: a second detection unit, configured to continue to perform rising edge detection on the phase value and bit error value starting from the first phase jump point; a second determination unit, configured to detect a bit error When the value changes from zero to a non-zero second phase jump point, it is determined that the detection result is normal; otherwise, it is determined that the detection result is abnormal.

Preferably, the determination module includes: a calculation module, used to calculate the phase value of the center point of the data eye diagram according to the first phase jump point and the second phase jump point when the detection result is normal; the setting module is used to In the case that the detection result is abnormal, the phase value of the central point of the data eye diagram is set to a preset default value.

Preferably, the calculation module includes: a calculation unit for calculating the phase value C of the central point of the data eye diagram according to the following formula: C=(A+B)/2, where A is the phase value of the first phase jump point, and B is the phase value of the second phase jump point; or, C=mod[(A+Y+B)/2, Y], where A is the phase value of the first phase jump point, and B is the second phase jump point The phase value of the change point, Y is the predetermined number of phase values.

According to the present invention, by detecting the falling edge and rising edge of the associated clock on the predetermined number of phase values and the error values corresponding to the phase values in the data eye diagram of the received data, the phase of the central point of the data eye diagram is determined according to the detection result The value method solves the problem that it is difficult to receive the data sampled by the ADC without error in the related technology, and then achieves fast error-free locking and reception even when the data does not have enough jumps, which greatly saves errors. Code test time, improve the effect of test efficiency.

Description of drawings

The accompanying drawings described here are used to provide a further understanding of the present invention and constitute a part of the application. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations to the present invention. In the attached picture:

Fig. 1 is a structural block diagram of a 100Gb/s wavelength division transmission system according to related technologies;

FIG. 2 is a structural block diagram of a broadband wireless communication system according to the related art;

3 is a flowchart of a method for receiving data without errors according to an embodiment of the present invention;

Fig. 4 is a "bath curve" diagram of bit error statistics used in the error-free data receiving method according to a preferred embodiment of the present invention;

Fig. 5 is a schematic diagram of the calculation flow of the calculation state machine of the data center point phase value according to a preferred embodiment of the present invention;

6 is a structural block diagram of an error-free data receiving device according to an embodiment of the present invention; and

Fig. 7 is a structural block diagram of an error-free data receiving device according to a preferred embodiment of the present invention.

detailed description

Hereinafter, the present invention will be described in detail with reference to the drawings and examples. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

First, a brief introduction to the execution idea of the error-free data receiving method provided by the embodiment of the present invention: the most direct indicator to measure the performance of a high-speed link is the bit error rate (BER). Normally, the order of magnitude of the BER should reach 10- 12 to 10-15. For example, the Common Electrical I/O (CEI-6G-LR) protocol stipulates that the rate reaches 6.375Gbps, and the link with a wiring length of 40 inches has a bit error rate of 10-15. To measure such a low bit error rate, the time factor is a very big problem for testers. For example, the rate of the link is 2.620Gbps (381ps/bit), calculated according to the average statistics of 100 error probability, it takes 381ps ×10^12×100=381000s≈2.7hours.

Using the phase relationship between the associated clock of the high-speed analog/digital converter (ADC) and the sampled data, the mode (Lock To Data) of the usual SERDESCDR locked in the data is changed to the mode locked in the reference clock (Lock ToReference), and the The eye diagram width of the channel clock is used as the base point, the data is re-sampled, the current data bit error rate is obtained by adjusting the clock edge, and the center point of the eye diagram of the data is finally determined.

Fig. 3 is a flowchart of a method for receiving data without error codes according to an embodiment of the present invention. As shown in Fig. 3 , the method mainly includes the following steps (step S302-step S306).

Step S302, performing channel-associated clock edge detection on a predetermined number of phase values in the data eye diagram of the received data and bit error values corresponding to the phase values.

Step S304, determine the phase value of the central point of the data eye diagram according to the detection result.

Step S306, adjusting the edge of the channel-associated clock to the time position corresponding to the phase value of the center point of the data eye diagram, and receiving error-free data according to the adjusted channel-associated clock.

In this embodiment, step S302 may be implemented as follows: firstly detect the falling edge of the associated clock for the phase value and the error value; then perform the rising edge detection for the phase value and the error value.

Among them, when the falling edge detection of the associated clock is performed on the phase value and bit error value, it can be realized in this way: when the value of the enable signal is 1, starting from the phase value of 0, the phase value and bit error value value to perform falling edge detection; when the first phase jump point where the bit error value changes from non-zero to zero is detected, it is determined to perform rising edge detection. Wherein, when the rising edge detection of the associated clock is performed on the phase value and the bit error value, it can be realized in such a way: starting from the first phase jump point, continue to detect the rising edge of the phase value and the bit error value; When detecting the second phase jump point where the bit error value changes from zero to non-zero, it is determined that the detection result is normal; otherwise, it is determined that the detection result is abnormal.

In this embodiment, step S304 can be implemented as follows: if the detection result is normal, calculate the phase value of the center point of the data eye diagram according to the first phase jump point and the second phase jump point; if the detection result is abnormal In this case, set the phase value of the center point of the data eye diagram to the preset default value.

Among them, when calculating the phase value of the center point of the data eye diagram according to the first phase jump point and the second phase jump point, it can be realized in this way: calculate the phase value C of the center point of the data eye diagram according to the following formula: C=( A+B)/2, where A is the phase value of the first phase jump point, B is the phase value of the second phase jump point; or, C=mod[(A+Y+B)/2, Y ], where A is the phase value of the first phase jump point, B is the phase value of the second phase jump point, and Y is the predetermined number of phase values.

Please refer to FIG. 4 and FIG. 5 at the same time. The error-free data receiving method provided by the above embodiment will be described in detail below in conjunction with FIG. 4 and FIG. 5 and the preferred embodiment.

This preferred embodiment utilizes the bit error statistics "bath curve" characteristic (Fig. 4 is the bit error statistics "bath curve" figure used in the error-free data receiving method according to the preferred embodiment of the present invention), as shown in Figure 4, find The bit error value is the transition point from non-0 to 0, and then find out the clock phase value corresponding to the bit error value from 0 to non-0, and finally determine the phase value of the center point of the data eye diagram.

Fig. 5 is a schematic diagram of the calculation flow of the calculation state machine of the phase value of the data center point according to a preferred embodiment of the present invention. As shown in Fig. 5, the calculation flow can be implemented through the following steps:

(1) Initialization (initial). Make sure that the state machine is reset, the enable signal is pulled high, and the number of bit errors corresponding to the 32 phase values of the data eye diagram has been calculated.

(2) Idle state (idle). Wait for the phase calculation to start (depending on whether the enable signal is valid), start calculation when the enable signal is valid (that is, the value of the enable signal phas_calc_start=1), enter the falling edge detection state (Nedge_Pose), otherwise, continue to idle.

(3) Falling edge detection state (Nedge_Pose). Start detection from the bit error value corresponding to phase 0. When the phase point a with the bit error value from positive to 0 is found, it is determined that the detection is normal and enters the rising edge detection state (Posed_nedge). If the phase increases to 31, the phase point a still cannot be found. , it is determined to be an abnormal detection, jump to the phase calculation state (PHA_CAL) to determine the best phase value (that is, the phase value of the center point of the data eye diagram) according to the default value.

(4) Rising edge detection status (Posed_nedge). Start detection from the bit error value corresponding to phase a, and when the bit error value is found from 0 to positive phase point b, it is determined that the detection is normal, enter the phase value calculation state (PHA_CAL), and calculate the best phase value combined with phase point a ( That is, the phase value of the center point of the data eye diagram), otherwise, it is determined that the detection is abnormal, and jumps to the phase calculation state (PHA_CAL) to determine the optimal phase value (ie, the phase value of the center point of the data eye diagram) according to the default value. It can be seen that no matter whether the phase point b is detected or not, it enters the phase value calculation state (PHA_CAL).

(5) Phase value calculation status (PHA_CAL). According to different situations, calculate the phase value of the center point (the phase value of the center point of the data eye diagram). If phase points a and b can be obtained, the optimal phase value = (phase point a+b)/2 or mod[(a+32+b)/2,32], as shown in Figure 3. Otherwise best phase value = default 16.

(6) Adjust the edge of the associated clock to the time position corresponding to the phase value of the center point of the data eye diagram, and receive the error-free data according to the adjusted associated clock (the receiving operation of the error-free data after adjustment belongs to the prior art part, no more details).

Using the error-free data receiving method provided by the above-mentioned embodiment, by detecting the falling edge and rising edge of the associated clock on the predetermined number of phase values and the error values corresponding to the phase values in the data eye diagram of the received data, according to the detection results Determining the phase value of the center point of the data eye diagram solves the problem in the related art that it is difficult to receive the data sampled by the ADC without error, and then achieves fast error-free locking even when the data does not have enough jumps. reception, which greatly saves the time of bit error testing and improves the test efficiency.

Fig. 6 is a structural block diagram of an error-free data receiving device according to an embodiment of the present invention. The device is used to implement the error-free data receiving method provided in the above embodiment. As shown in Fig. 6, the device mainly includes: a detection module 10, a determination Module 20 and processing module 30. Among them, the detection module 10 is used to detect the associated clock edge of the predetermined number of phase values and the error values corresponding to the phase values in the data eye diagram of the received data; the determination module 20 is connected to the detection module 10. The detection result determines the phase value of the center point of the data eye diagram; the processing module 30 is connected to the determination module 20, and is used to adjust the edge of the associated clock to the time position corresponding to the phase value of the center point of the data eye diagram, according to the adjusted associated clock Receive error-free data.

Fig. 7 is a structural block diagram of an error-free data receiving device according to a preferred embodiment of the present invention. As shown in Fig. 7, in the device provided in this preferred embodiment, the detection module 10 may include: a first detection module 12 for detecting The phase value and the bit error value are detected by the falling edge of the associated clock; the second detection module 14 is connected to the first detection module 12, and is used for detecting the rising edge of the associated clock for the phase value and the bit error value.

Wherein, the first detection module 12 may include: a first detection unit 122, configured to perform falling edge detection on the phase value and the bit error value starting from the phase value 0 when the value of the enable signal is 1; the first determination A unit 124, connected to the first detection unit 122, is configured to determine to perform rising edge detection when a first phase jump point at which the bit error value changes from non-zero to zero is detected.

The second detection module 14 may include: a second detection unit 142, which is used to continue to detect the rising edge of the phase value and the error code value from the first phase jump point; a second determination unit 144, connected to the second detection unit 142, configured to determine that the detection result is normal when a second phase jump point at which the bit error value changes from zero to non-zero is detected; otherwise, determine that the detection result is abnormal.

In the device provided in this preferred embodiment, the determination module 20 may include: a calculation module 22, configured to calculate the center of the data eye diagram according to the first phase jump point and the second phase jump point when the detection result is normal Point phase value; a setting module 24, configured to set the center point phase value of the data eye pattern to a preset default value when the detection result is abnormal.

Wherein, the calculation module 22 may include: a calculation unit 222, which is used to calculate the phase value C of the center point of the data eye diagram according to the following formula: C=(A+B)/2, where A is the phase value of the first phase jump point , B is the phase value of the second phase jump point; or, C=mod[(A+Y+B)/2, Y], where A is the phase value of the first phase jump point, B is the second The phase value of the phase jump point, Y is the predetermined number of phase values.

Using the error-free data receiving device provided by the above-mentioned embodiment, by detecting the falling edge and rising edge of the associated clock on the predetermined number of phase values and the error values corresponding to the phase values in the data eye diagram of the received data, according to the detection result Determining the phase value of the center point of the data eye diagram solves the problem in the related art that it is difficult to receive the data sampled by the ADC without error, and then achieves fast error-free locking even when the data does not have enough jumps. reception, which greatly saves the time of bit error testing and improves the test efficiency.

From the above description, it can be seen that the present invention achieves the following technical effects: by performing the corresponding phase values of the predetermined number of phase values and the error values corresponding to the phase values in the data eye diagram of the received data respectively Rising edge detection, which determines the phase value of the center point of the data eye diagram according to the detection results, solves the problem in related technologies that it is difficult to receive the data sampled by the ADC without error, and can ensure the data transmission of the internal link of the system, even in the Even if the data does not have enough jumps, it can quickly lock and receive error-free codes, thereby achieving the effect of greatly saving code error testing time and improving test efficiency.

Obviously, those skilled in the art should understand that each module or each step of the above-mentioned present invention can be realized by a general-purpose computing device, and they can be concentrated on a single computing device, or distributed in a network formed by multiple computing devices Alternatively, they may be implemented in program code executable by a computing device so that they may be stored in a storage device to be executed by a computing device, and in some cases in an order different from that shown here The steps shown or described are carried out, or they are separately fabricated into individual integrated circuit modules, or multiple modules or steps among them are fabricated into a single integrated circuit module for implementation. As such, the present invention is not limited to any specific combination of hardware and software.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (12)

1. A method for receiving data without errors, comprising: Performing rising edge detection and falling edge detection of the associated clock on the predetermined number of phase values in the data eye diagram of the received data and the bit error values corresponding to the phase values; Determine the phase value of the center point of the data eye diagram according to the detection result; Adjusting the edge of the associated clock to the time position corresponding to the phase value of the central point of the data eye diagram, and receiving error-free data according to the adjusted associated clock. 2. The method according to claim 1, characterized in that, the predetermined number of phase values in the data eye diagram of the received data and the bit error value corresponding to the phase value are carried out with the channel clock edge detection, comprising: First, the falling edge detection of the associated clock is performed on the phase value and the error value; Then, the rising edge detection of the associated clock is performed on the phase value and the bit error value. 3. The method according to claim 2, wherein the falling edge detection of the associated clock is carried out to the phase value and the error value, comprising: When the value of the enable signal is 1, starting from the phase value of 0, performing falling edge detection on the phase value and the error code value; When the first phase jump point at which the bit error value changes from non-zero to zero is detected, it is determined to perform the rising edge detection. 4. method according to claim 3, is characterized in that, carrying out the rising edge detection of road-associated clock to described phase value and described bit error value, comprising: Starting from the first phase jump point, continue to perform rising edge detection on the phase value and the bit error value; When the second phase jump point at which the bit error value changes from zero to non-zero is detected, it is determined that the detection result is normal; otherwise, it is determined that the detection result is abnormal. 5. The method according to claim 4, wherein determining the center point of the data eye diagram according to the detection result comprises: When the detection result is normal, calculate the phase value of the center point of the data eye diagram according to the first phase jump point and the second phase jump point; If the detection result is abnormal, the phase value of the center point of the data eye diagram is set to a preset default value. 6. The method according to claim 5, wherein calculating the phase value of the center point of the data eye diagram according to the first phase jump point and the second phase jump point comprises: Calculate the phase value C of the center point of the data eye diagram according to the following formula: C=(A+B)/2, where A is the phase value of the first phase jump point, and B is the phase value of the second phase jump point; or, C=mod[(A+Y+B)/2, Y], where A is the phase value of the first phase jump point, B is the phase value of the second phase jump point, and Y is the phase A predetermined number of values. 7. An error-free data receiving device, characterized in that it comprises: The detection module is used to perform the rising edge detection and falling edge detection of the associated clock on the predetermined number of phase values in the data eye diagram of the received data and the error value corresponding to the phase value; A determining module, configured to determine the phase value of the center point of the data eye diagram according to the detection result; The processing module is configured to adjust the edge of the associated clock to the time position corresponding to the phase value of the central point of the data eye diagram, and receive error-free data according to the adjusted associated clock. 8. The device according to claim 7, wherein the detection module comprises: The first detection module is used to first detect the falling edge of the associated clock on the phase value and the error value; The second detection module is configured to detect the rising edge of the associated clock on the phase value and the error code value. 9. The device according to claim 8, wherein the first detection module comprises: The first detection unit is configured to perform falling edge detection on the phase value and the bit error value starting from the phase value 0 when the value of the enable signal is 1; The first determining unit is configured to determine to execute the rising edge detection when detecting a first phase jump point at which the bit error value changes from non-zero to zero. 10. The device according to claim 9, wherein the second detection module comprises: The second detection unit is configured to continue to detect the rising edge of the phase value and the error code value starting from the first phase jump point; The second determination unit is configured to determine that the detection result is normal when the second phase jump point at which the bit error value changes from zero to non-zero is detected, otherwise, determine that the detection result is abnormal. 11. The device according to claim 10, wherein the determining module comprises: A calculation module, configured to calculate the phase value of the center point of the data eye diagram according to the first phase jump point and the second phase jump point when the detection result is normal; A setting module, configured to set the phase value of the center point of the data eye diagram as a preset default value when the detection result is abnormal. 12. The device according to claim 11, wherein the calculation module comprises: A calculation unit, configured to calculate the phase value C of the central point of the data eye diagram according to the following formula: C=(A+B)/2, where A is the phase value of the first phase jump point, and B is the phase value of the second phase jump point; or, C=mod[(A+Y+B)/2, Y], where A is the phase value of the first phase jump point, B is the phase value of the second phase jump point, and Y is the phase A predetermined number of values.