CN103515478A - Base board unit subjected to textured surface processing by using substrate, and forming method thereof - Google Patents

Abstract

The invention provides a substrate unit, a substrate structure and a manufacturing method thereof. The substrate structure includes a substrate unit array, the array includes a plurality of substrate units, each of the substrate units includes: a single crystal semiconductor substrate having a first doping type, the semiconductor substrate includes a first surface and an opposite The second surface, the third surface and the fourth surface opposite to it, the crystal orientation of the third surface and the fourth surface is {111}, and the crystal layer formed on the third surface of the semiconductor substrate has the second doping type, the surface is the first semiconductor layer of texture; and a plurality of substrates, wherein: for each of the spaced apart substrate units, its second surface shares a substrate with the second surface of the adjacent substrate on one side thereof, And the first surface thereof shares another substrate with the first surface of the adjacent substrate on the other side, so that the substrate structure forms a Great Wall structure. The invention effectively utilizes the thickness of the substrate and increases the processable surface area of the wafer. When used as a solar cell substrate, the textured surface can advantageously improve the light trapping effect and increase the light entry efficiency of the solar cell.

Description

A substrate unit for suede processing using a substrate and its forming method

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a substrate unit processed by using a substrate, a substrate structure and a manufacturing method thereof.

Background technique

In recent years, with the rapid development of the semiconductor industry, semiconductor devices continue to develop in the direction of small size, high circuit density, high speed, and low power consumption. Integrated circuits have now entered the sub-micron technology stage. Therefore, in order to meet the needs of small volume and high integration, two requirements are put forward at present. On the one hand, the diameter of the wafer is required to gradually increase. In 2010, silicon wafers with a diameter of 450mm (18in) will begin to be used, and the diameter of wafers will increase at a rate of 1.5 times every 9 years, and will develop into a large area. On the other hand, there is also a requirement, that is, it is hoped to increase the utilization rate of the surface area without increasing the size of the existing wafer, so as to increase its processable surface area. In particular, the thickness of the substrate can be used to process the substrate. When processing a single-crystal wafer, the crystal orientation of the wafer can provide benefits for the processing of the substrate. For example, using isotropic etching can A surface with a specific crystallographic orientation is obtained. When processing multi-crystalline wafers, anisotropic etching, such as RIE, can be used. However, regardless of whether it is a single crystal substrate or a polycrystalline substrate, processing using the substrate thickness will bring other problems. For example, in the processing of solar cell substrates, in order to improve the light trapping effect, it is usually desired to However, it will be very difficult to form texture on the surface obtained by isotropic etching in single crystal substrate, and the surface obtained by anisotropic etching in polycrystalline substrate There are also very strict requirements for making suede. So far, no solution has been proposed to increase wafer utilization and form texture on a specific surface based on the size of existing wafers.

Contents of the invention

In order to solve the above problems, the present invention provides a substrate unit for processing using a substrate: comprising: a semiconductor substrate, the semiconductor substrate is a single crystal substrate with a first doping type, and the semiconductor substrate includes a first surface and the second surface opposite to it, the third surface and the fourth surface opposite to it, the crystal orientation of the third surface and the fourth surface is {111}; formed on the third surface of the semiconductor substrate has a The second doping type, the first semiconductor layer with textured surface.

According to the second aspect of the present invention, there is also provided a substrate structure for processing with a substrate, the structure includes: a substrate unit array, the substrate unit array includes a plurality of substrate units arranged in a predetermined direction, each of the The substrate unit includes: a single crystal semiconductor substrate having a first doping type, the semiconductor substrate includes a first surface and a second surface opposite thereto, a third surface and a fourth surface opposite thereto, the third surface and the first surface The crystal orientation of the four surfaces is {111}, and a first semiconductor layer with a second doping type and a textured surface formed on the third surface of the semiconductor substrate; and a plurality of substrates, the plurality of The substrates are respectively arranged on the outer sides of the first surface and the second surface of the semiconductor substrate, wherein: for each of the spaced substrate units, the second surface and the second surface of the adjacent substrate on one side share a base sheet to form a first groove, and its first surface and the first surface of an adjacent substrate on the other side share another substrate to form a second groove, the first groove and the second groove The opening directions are opposite, so that the substrate structure forms a Great Wall structure.

According to the third aspect of the present invention, the present invention also provides a method for manufacturing a substrate structure for a semiconductor device, which is characterized in that it includes the following steps: A. providing a semiconductor substrate, said substrate being a single crystal substrate having a first doping type, said substrate comprising a first surface and a second surface opposite to the first surface; B. patterning the first surface and the second surface of the substrate; C. Etching the semiconductor substrate from the first surface to form at least two first trenches; and etching the semiconductor substrate from the second surface to form at least one second trench, wherein each of the second trenches The groove is located between two adjacent first grooves, and the crystal orientation of the side walls corresponding to the first groove and the second groove is {111}, D. A first semiconductor layer with second type doping is formed on the sidewall of the first trench, and the first semiconductor layer is wet-etched to form a textured layer on the surface thereof.

In addition, the present invention also provides another manufacturing method for a substrate structure of a semiconductor device, the method comprising: A, providing a semiconductor substrate, the semiconductor substrate has a first doping type, and the semiconductor substrate Including a first surface and a second surface opposite thereto; B, patterning the first surface of the substrate, and patterning the second surface of the substrate, and etching the substrate from the first surface forming at least two first grooves, and etching the substrate from the second surface to form at least one second groove, and forming a textured surface on the inner wall of the first groove, wherein each of the second grooves The groove is located between two adjacent first grooves; C, performing subsequent processing.

The present invention also provides a substrate structure processed by using a substrate formed according to the above method, the structure includes: a substrate unit array, the substrate unit array includes a plurality of substrate units arranged in a predetermined direction, each substrate unit Including: a semiconductor substrate, the semiconductor substrate includes a first surface and a second surface opposite to it, a third surface and a fourth surface opposite to it, wherein the third surface is textured; and a plurality of substrates, the A plurality of substrates are respectively arranged on the outside of the first surface and the second surface of the semiconductor substrate, wherein: for each of the spaced apart substrate units, its second surface is shared with the second surface of the adjacent substrate on one side thereof One substrate to form a first groove, and its first surface shares another substrate with the first surface of its adjacent substrate on the other side to form a second groove, the first groove and the second The opening directions of the grooves are opposite, so that the substrate structure forms a Great Wall structure.

In addition, the present invention also provides a method for forming a suede surface, said method comprising: A, a single crystal semiconductor substrate, said semiconductor substrate comprising a first surface, a second surface opposite to it, and a third surface and The fourth surface opposite to it; B, forming a first textured surface on at least the third surface by anisotropic wet etching; C, forming a second textured surface on the first textured surface.

And the substrate unit using the substrate for textured processing formed by the above method: including: a single crystal semiconductor substrate with a first doping type, the semiconductor substrate includes a first surface and a second surface opposite to it, and a third surface and a fourth surface opposite thereto; a first textured surface formed on the third surface of the semiconductor substrate; a second textured surface formed on the first textured surface.

The substrate structure according to the present invention effectively utilizes the thickness of the substrate, thereby increasing the processable surface area or surface area utilization rate of the wafer without increasing the size of the entire wafer. At the same time, the present invention also forms a suede surface on the surface with a specific crystal orientation, which can improve the light trapping effect and improve the light absorption efficiency of the solar cell during, for example, the processing of the solar cell substrate.

Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and easy to understand from the following description of the embodiments in conjunction with the accompanying drawings, wherein:

Figure 1 shows a schematic diagram of a substrate unit according to a first embodiment of the present invention;

2-4 show schematic diagrams of a substrate structure according to a second embodiment of the present invention;

5 shows a schematic diagram of a method for forming a substrate structure according to a second embodiment of the present invention;

6-15 are schematic diagrams showing various stages of a manufacturing method of a substrate structure according to a second embodiment of the present invention;

16-23 are schematic diagrams showing various stages of a method for manufacturing a substrate structure according to a fourth embodiment of the present invention;

FIG. 24 shows a schematic diagram of a method for forming a substrate structure according to a fourth embodiment of the present invention.

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention. The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described below. Of course, they are only examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. In addition, various specific process and material examples are provided herein, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials. Additionally, configurations described below in which a first feature is "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may include additional features formed between the first and second features. For example, such that the first and second features may not be in direct contact.

first embodiment

FIG. 1 shows a schematic diagram of a substrate unit 200 according to an embodiment of the present invention. The substrate unit is obtained by processing a substrate, and the substrate is a single crystal substrate, which may include, for example: single crystal Si, single crystal Ge , Single crystal SiGe. The substrate may have a thickness of 0.2-2mm. The substrate unit includes a semiconductor substrate 101, which is a single crystal substrate with a first doping type, such as an N-type doping configuration or a P-type doping configuration, and the semiconductor substrate includes a first surface and an opposite The second surface, the third surface and the fourth surface opposite to it, the crystal orientation of the third surface and the fourth surface is {111}; the second doping type formed on the third surface of the semiconductor substrate 1. The first semiconductor layer 202 with a textured surface.

In particular, the first surface and the second surface 301/302 of the semiconductor substrate are two surfaces of the semiconductor substrate.

In addition, the substrate unit may further include a second semiconductor layer (not shown in the figure) having a first doping type and having a textured surface formed on the fourth surface of the semiconductor substrate 101 . The material of the first and second semiconductor layers may be, for example, polysilicon, amorphous silicon or a combination thereof, and the thickness thereof may be about 1-10 μm.

In particular, in another embodiment (not shown in the figure), the crystal orientations of the third surface and the fourth surface of the semiconductor substrate may not be {111}, and the semiconductor substrate includes: single crystal Si, single crystal Ge, single crystal SiGe. In the embodiment where the crystal orientations of the third and fourth surfaces are not {111}, the substrate unit may further include a first textured surface formed on the third surface of the semiconductor substrate, and a first textured surface formed on the The second texture on the first texture, wherein the first texture has a crystal orientation of {111}, and the second texture includes polysilicon, amorphous silicon or a combination thereof.

Therefore, an embodiment of the present invention provides a substrate unit processed by using a substrate having a first doping type and being a single crystal substrate, whereby the isotropic etching technique can be used to process the substrate unit The substrate thus obtains a surface with a specific crystal orientation, thereby effectively utilizing the thickness of the substrate and improving the surface area utilization rate of the wafer. Moreover, a second doping type is formed on the third surface of the substrate unit. , the first semiconductor layer 202 with a textured surface, and a second semiconductor layer with the first doping type and a textured surface formed on the fourth surface. When the substrate unit is used in a solar cell substrate, the textured surface can advantageously improve the light trapping effect, thereby increasing the light entry efficiency of the solar cell.

In particular, when applied to a solar cell substrate, the substrate unit 200 may also include a first electrode layer respectively formed on the first semiconductor layer, and a second electrode layer formed on the second semiconductor layer (in the figure not shown). Wherein the first electrode layer is a light-incoming surface, which can be formed of TCO materials, such as SnO ₂ , In ₂ O ₃ , ZnO, ITO, CdO, Cd ₂ SnO ₄ , FTO, AZO or combinations thereof. The second electrode layer can also be used as a light-incoming surface, that is, it can also be formed of a TCO material, alternatively, it can not be used as a light-incoming surface, and can be formed of a metal material suitable for conducting electricity. The thicknesses of the first electrode layer and the second electrode layer are respectively about 10-200 nm.

Optionally, when applied to a solar cell substrate, the substrate unit may further include an anti-reflection layer formed on the first electrode layer, such as a nitride material. The anti-reflection layer may have a thickness of about 40-160 nm. Thereby, the light-introduction efficiency of the solar cell is further increased.

As an incidental structure obtained by processing the substrate, the substrate unit may further include sidewalls formed on the first surface and the second surface of the semiconductor substrate.

Therefore, an embodiment of the present invention provides a substrate unit processed by using a substrate having a first doping type and being a single crystal substrate, whereby the isotropic etching technique can be used to process the substrate unit The substrate thus obtains a surface with a specific crystal orientation, thereby effectively utilizing the thickness of the substrate and improving the surface area utilization rate of the wafer. Moreover, a second doping type is formed on the third surface of the substrate unit. , the first semiconductor layer 202 with a textured surface, and optionally, a second semiconductor layer with the first doping type and a textured surface formed on the fourth surface. When the substrate unit is used as a solar cell substrate, the textured surface can advantageously improve the light trapping effect, thereby increasing the light entry efficiency of the solar cell.

second embodiment

The substrate unit of the present invention has been described above according to the first embodiment of the present invention, and the second embodiment of the present invention will be described below with reference to the accompanying drawings.

According to the second embodiment of the present invention, there is provided a substrate structure processed by using a substrate. As shown in FIG. 2 , the structure includes: a substrate unit array.

The substrate unit array includes a plurality of substrate units 200 arranged in a predetermined direction, for example along direction A, preferably, they may be a plurality of substantially parallel substrate units. Each of the substrate units 200 includes a semiconductor substrate 101-x, which is a single crystal substrate with a first doping type, and its material may be, for example, single crystal Si, single crystal Ge, or single crystal SiGe. The semiconductor substrate includes a first surface 301 and a second surface 302 opposite thereto, a third surface 303 and a fourth surface 304 opposite thereto. The crystal orientations of the third surface and the fourth surface are {111}. The structure further includes: a plurality of substrates 307-x and 308-x, the plurality of substrates are respectively disposed outside the first surface and the second surface of the semiconductor substrate. The plurality of substrates may be formed of the same or different material from the plurality of substrate units and include at least one layer, and the material may be, for example, insulating material, metal, semiconductor material or a combination thereof.

Wherein, for each of the spaced substrate units 200, its second surface and the second surface of the adjacent substrate on one side share a substrate to form the first groove 305, and its first surface and the other side The first surfaces of adjacent substrates share another substrate to form a second groove 306, and the opening direction of the first groove is opposite to that of the second groove, so that the substrate structure forms a Great Wall structure. In particular, the substrate structure further includes a first semiconductor layer 202 with a second doping type and a textured surface formed in the first trench 305 .

In particular, the first surface and the second surface 301/302 of the semiconductor substrate are two surfaces of the semiconductor substrate. Preferably, the substrate structure may further include a second semiconductor layer 203 having a first doping type and a textured surface formed in the second trench 306 , as shown in FIG. 3 . The material of the first and second semiconductor layers may be, for example, polysilicon, amorphous silicon or a combination thereof, and the thickness thereof may be about 1-10 μm.

Furthermore, preferably, the substrate unit and the substrate connected thereto may be kept substantially vertical. And the depth of at least one of the first and second grooves is greater than twice the width of the substrate unit, and the width of the substrate unit is the distance between the surfaces corresponding to the side walls of two adjacent grooves belonging to the same substrate unit. The distance, that is, the distance between the third surface and the fourth surface of the same substrate unit. The thickness of the substrate is less than 1/3 of the width of the substrate unit.

Thus, embodiments of the present invention provide a substrate structure utilizing substrate processing, the substrate structure having a Great Wall-like structure. The substrate has the first doping type and is a single crystal substrate, so that the substrate can be processed by an isotropic etching technique to obtain a surface with a specific crystal orientation, thereby effectively utilizing the thickness of the substrate Form a Great Wall structure and improve the utilization rate of the surface area of the wafer. Moreover, a first semiconductor layer 202 with a second doping type and a textured surface is formed in the first trench of the substrate structure, and optionally, a semiconductor layer 202 with a second doping type is formed in the second trench. A doped second semiconductor layer 203 with textured surface. When the substrate unit is used in a solar cell substrate, the textured surface can advantageously improve the light trapping effect, thereby increasing the light entry efficiency of the solar cell.

In particular, when applied to a solar cell substrate, the substrate unit 200 may further include a first electrode layer 204 respectively formed on the first semiconductor layer, and a second electrode layer 205 formed on the second semiconductor layer, As shown in Figure 4. Wherein the first electrode layer is a light-incoming surface, which can be formed of TCO materials, such as SnO ₂ , In ₂ O ₃ , ZnO, ITO, CdO, Cd ₂ SnO ₄ , FTO, AZO or combinations thereof. The second electrode layer can also serve as a light-incoming surface, that is, it can also be formed of TCO material. Optionally, the second electrode layer may not serve as a light-incoming surface, and be formed of a metal material suitable for conducting electricity. The thicknesses of the first electrode layer and the second electrode layer are respectively about 10-200 nm.

Optionally, when applied to a solar cell substrate, the substrate unit may further include an anti-reflection layer (not shown in the figure), such as a nitride material, formed on the first electrode layer. The anti-reflection layer may have a thickness of about 40-160 nm. Thereby, the light-introduction efficiency of the solar cell is further increased.

The novel substrate unit and structure according to the embodiments of the present invention have been described above with reference to the accompanying drawings, and the substrate unit and structure can be applied in various fields such as the manufacture of semiconductor devices and the manufacture of thin-film solar cells. It should be noted that those skilled in the art can choose a variety of processes for manufacturing according to the above-mentioned substrate structure, such as different types of product lines, different process flows, etc., but as long as the substrate units and structures manufactured by these processes have the same Inventing basically the same structure and achieving basically the same effect should also be included in the protection scope of the present invention. In order to understand the present invention more clearly, the method and process for forming the above-mentioned substrate unit and structure of the present invention will be specifically described below. It should also be noted that the following steps are only illustrative and not limiting to the present invention. Technicians can also realize it through other techniques. The following embodiments are preferred embodiments of the present invention, which can effectively reduce manufacturing costs.

As shown in FIG. 5, it is a flowchart of a method for forming a substrate unit and a structure according to an embodiment of the present invention, including the following steps:

In step S101 , as shown in FIG. 6 , a substrate 100 is provided. In one embodiment of the present invention, the substrate 100 is a single crystal semiconductor substrate, such as single crystal Si, single crystal Ge, single crystal SiGe or a combination thereof. In other embodiments, the semiconductor substrate can be produced in various ways, such as deposition, epitaxial growth, etc., and the substrate can have an N-type doping configuration or a P-type doping configuration. Wherein, the thickness of the semiconductor substrate may be 0.2-2mm, of course, the present invention is not limited thereto. The substrate includes a first surface 301 and a second surface 302, and the first surface 301 and the second surface 302 are opposite to each other. In particular, the substrate may include one or more layers, for example, the substrate may include a semiconductor layer 300 and material layers 307 , 308 formed above and below the semiconductor layer, as shown in FIG. 7 . The material layer may also include one or more layers, and the material used for each layer may be configured as required, for example, may include an insulating layer for etching stop, a conductive layer for conduction, and the like. The material layer may be formed of the same or different material as the semiconductor layer, including but not limited to insulating material, metal, semiconductor material or a combination of the above materials. All of these can be configured according to the needs in the actual application process, which is not limited in the present invention.

Step S102 , as shown in FIGS. 8-13 , patterning the first surface 301 and the second surface 302 of the substrate 100 , as shown in FIG. 8 . For example, taking the structure of the substrate shown in FIG. 7 as an example, the substrate 100 can be patterned in the following manner: on the first surface 301 of the substrate 100, a plurality of grooves with a predetermined interval configuration are formed A photoresist layer 309, as shown in FIG. 9; etch the substrate 100 to remove the material layer 307 at the multiple grooves of the first surface 301, as shown in FIG. 10; remove The photoresist layer 309; then on the second surface 302, a photoresist layer 310 with a plurality of grooves arranged at predetermined intervals is formed, as shown in FIG. 11; the substrate is etched 100, to remove the material layer 308 at the multiple grooves of the second surface 302, as shown in FIG. 12; remove the photoresist layer, thereby patterning the substrate, as shown in FIG. 13 shown. Of course, the patterning steps described above are only examples, and those skilled in the art can obtain the patterned substrate described in this embodiment through many methods known in the art, which can be applied to this embodiment, and Without departing from the protection scope of the present invention.

Then, in step S103, as shown in FIG. 14, at least two first grooves 305 are etched from the first surface 301 of the substrate 100; The second trench 306 . Since the substrate is a single crystal substrate, an isotropic etching method can be selected to etch the substrate, for example, wet etching can be used, using potassium hydroxide (KOH), tetramethylhydrogen Ammonium oxide (TMAH) or ethylenediamine-catechol (EDP) and other solvents for etching, when the crystal orientation of the first surface and the second surface is {110} or {112}, the etching The agent will stop on the {111} crystal plane of the substrate, and the crystal orientation of the surfaces corresponding to the sidewalls of the formed first trench and second trench is {111}, thereby obtaining a surface with a specific crystal orientation .

Optionally, all or part of the semiconductor layer 300 can be etched, for example, the first surface 301 of the substrate can be etched and stop on the material layer 308 of the second surface 302, and the substrate can be etched. The second surface 302 of the bottom rests on the material layer 309 of the first surface 301 . Of course, only a part of the semiconductor layer may be etched, that is, the bottoms of the first trench and the second trench do not contact the material layers 308 , 309 . When the substrate is one layer, only part of the substrate can be etched. In FIG. 14 , the dark area defined by the solid line indicates the first trench 305 formed on the first surface 301, and the light area defined by the dotted line indicates the second trench 305 formed on the second surface 302. groove 306 . The first groove and the second groove may have equal or unequal intervals,

In particular, the substrate can be patterned so that the first groove and the second groove are substantially parallel, and these can be set according to design requirements. In this way, each of the second grooves 306 is located between two adjacent first grooves 305, so as to divide the substrate into at least two substrates and at least one substrate, and the substrate is formed by the first Defined by the side walls of a groove 305 and a second groove 306, the substrate connects two adjacent substrates, thereby obtaining a substrate structure with a Great Wall structure, as shown in FIG. 15 . Preferably, the depth 311 of one of the first groove 305 and the second groove 306 is greater than twice the substrate width (the distance between surfaces corresponding to the sidewalls of two adjacent grooves belonging to the same substrate) 310 .

In particular, when the plurality of first grooves 305 and the plurality of second grooves 306 are substantially parallel, the substrate array may include a plurality of substantially parallel substrates. In particular, the substrate and the substrate connected thereto may be substantially vertical, ie the first groove and the second groove may be substantially rectangular in shape.

Then, in step S104, a first semiconductor layer with second-type doping is formed on the sidewall of the first trench 305, and then the first conductive layer is wet-etched to form a textured layer 202 on its surface, as shown in picture 2. Optionally, as shown in FIG. 3 , a second semiconductor layer with the first type of doping may also be formed on the sidewall of the second trench 306, and then wet etch the second semiconductor layer to form a The suede layer 203 is formed. The material of the first and second semiconductor layers may be, for example, polysilicon, amorphous silicon or a combination thereof, and the thickness thereof may be about 1-10 μm.

Thus, embodiments of the present invention provide a method of forming a substrate structure capable of forming a Great Wall-like structured substrate structure. Utilize the single crystal substrate with the first doping type, process the substrate with isotropic etching technology to obtain a surface with a specific crystal orientation, and then effectively use the thickness of the substrate to form a Great Wall structure and improve the crystallinity. Surface area utilization of the wafer. Moreover, a first semiconductor layer 202 with a second doping type and a textured surface is formed in the first trench of the substrate structure, and optionally, a semiconductor layer 202 with a second doping type is formed in the second trench. A doped second semiconductor layer 203 with textured surface. When the substrate structure is used in the application of the solar cell substrate, the textured surface can advantageously improve the light trapping effect, thereby increasing the light entry efficiency of the solar cell.

In particular, when the substrate structure obtained by the method is applied to the field of solar cells, the first electrode layer 204 can also be formed on the first semiconductor layer 202 of the first groove 205, and the second semiconductor layer 203 is formed on the second electrode layer 205, as shown in FIG. 4 . Wherein the first electrode layer 204 is a light-incoming surface, which can be formed of TCO materials, such as SnO ₂ , In ₂ O ₃ , ZnO, ITO, CdO, Cd ₂ SnO ₄ , FTO, AZO or combinations thereof. The second electrode layer 205 can also serve as a light-incoming surface, that is, it can also be formed of TCO material. Optionally, the second electrode layer 205 may not serve as a light-incoming surface, and be formed of a metal material suitable for conducting electricity. The thicknesses of the first electrode layer and the second electrode layer are respectively about 10-200 nm.

Optionally, when the substrate structure obtained by the method is applied in the field of solar cells, an anti-reflection layer (not shown in the figure), such as a nitride material, may also be formed on the first electrode layer 204 . The anti-reflection layer may have a thickness of about 40-160 nm. Thereby, the light-introduction efficiency of the solar cell is further increased.

Further, the substrate structure can be cut along the first groove and the second groove to form a substrate unit, or when the thickness of the substrate is sufficiently thin, for example, less than 1/3 of the width of the substrate, it can be appropriately The process can easily stretch the substrate structure, so that the substrate unit arrays are formed on substantially the same plane, which is suitable for the next treatment and processing.

third embodiment

The single crystal substrate unit has been described above in the first embodiment, and the substrate structure of the single crystal crystal orientation {111} and its manufacturing method have been described in the second embodiment, and the single crystal crystal orientation non-{111} }’s substrate unit, structure and manufacturing method are described in detail (see the second embodiment for illustration).

According to a third embodiment of the present invention, a substrate structure processed by using a substrate is provided, and the structure includes: a substrate unit array.

The substrate unit array includes a plurality of substrate units arranged in a predetermined direction, preferably, they may be substantially parallel. Each of the substrate units includes a semiconductor substrate, and the semiconductor substrate is a single crystal substrate with a first doping type, and its material may be, for example, single crystal Si, single crystal Ge, or single crystal SiGe. The semiconductor substrate includes a first surface and a second surface opposite thereto, and a third surface and a fourth surface opposite thereto. The crystal orientations of the third surface and the fourth surface are not {111}. The structure further includes: a plurality of substrates disposed outside the first surface and the second surface of the semiconductor substrate, respectively. The plurality of substrates may be formed of the same or different material from the plurality of substrate units and include at least one layer, and the material may be, for example, insulating material, metal, semiconductor material or a combination thereof.

Wherein, for each of the spaced substrate units, its second surface and the second surface of the adjacent substrate on one side share a substrate to form the first groove, and its first surface is opposite to the second surface on the other side. The first surface adjacent to the substrate shares another substrate to form a second groove, and the opening direction of the first groove is opposite to that of the second groove, so that the substrate structure forms a Great Wall structure. In particular, the substrate structure further includes a first textured surface formed in the first groove, and a second textured surface with a second type of doping formed on the first textured surface, wherein the first textured surface The texture has a crystal orientation of {111}, and the second texture includes polysilicon, amorphous silicon or a combination thereof.

In particular, the first surface and the second surface of the semiconductor substrate are two surfaces of the semiconductor substrate. Preferably, the substrate structure may further include a third texture formed in the second groove, and a fourth texture with the first type of doping formed on the third texture, wherein the first texture The third textured surface has a crystal orientation of {111}, and the fourth textured surface includes polysilicon, amorphous silicon or a combination thereof.

Furthermore, preferably, the substrate unit and the substrate connected thereto may be kept substantially vertical. And the depth of at least one of the first and second grooves is greater than twice the width of the substrate unit, and the width of the substrate unit is the distance between the surfaces corresponding to the side walls of two adjacent grooves belonging to the same substrate unit. The distance, that is, the distance between the third surface and the fourth surface of the same substrate unit. The thickness of the substrate is less than 1/3 of the width of the substrate unit.

Thus, embodiments of the present invention provide a substrate structure utilizing substrate processing, the substrate structure having a Great Wall-like structure. The substrate has the first doping type and is a single crystal substrate, so that the substrate can be processed by an isotropic etching technique to obtain a surface with a specific crystal orientation, thereby effectively utilizing the thickness of the substrate Form a Great Wall structure and improve the utilization rate of the surface area of the wafer. Moreover, a first texture and a second texture are formed in the first groove of the substrate structure, and optionally, a third texture and a fourth texture are formed in the second groove. When the substrate unit is used in a solar cell substrate, the textured surface can advantageously improve the light trapping effect, thereby increasing the light entry efficiency of the solar cell.

The method for forming the substrate unit and the structure of this embodiment will be described below, and only the content that is different from that of the second embodiment will be described, and the same will not be repeated.

In step S101', a substrate is provided. In one embodiment of the present invention, the substrate is a single crystal semiconductor substrate, such as single crystal Si, single crystal Ge, single crystal SiGe or a combination thereof. The substrate includes a first surface and a second surface, the first surface and the second surface are opposite, wherein crystal orientations of the third and fourth surfaces are not {111}.

In step S102', the first surface and the second surface of the substrate are patterned, which is the same as the second embodiment, and will not be described again.

In step S103', etching at least two first trenches from the first surface of the substrate; and etching at least one second trench from the second surface of the substrate; and etching the first and/or A suede layer is formed in the second groove.

In one embodiment, at least two first grooves can be etched from the first surface by an anisotropic etching method, such as RIE method, and the sidewalls of the first grooves are the first grooves of the semiconductor substrate. The third and fourth surfaces, and then, by anisotropic wet etching, such as KOH or TMAH solvent, after etching, a crystal orientation of {111} is formed on the third and fourth surfaces of the first trench. The first textured surface, polysilicon, amorphous silicon, or a combination thereof may then be deposited on the first textured surface, and etched again to form a second textured surface, which may have a second type of doping , so that a suede layer including the first and the second suede is formed in the first groove. Then, at least one second trench can be etched from the second surface by anisotropic etching method, such as RIE method.

In another embodiment, an anisotropic etching method, such as RIE, can be used to etch at least two first grooves from the first surface and at least one second groove from the second surface, respectively. The sidewalls of the first and second trenches are the basic third and fourth surfaces of the semiconductor. Then, by anisotropic wet etching, such as KOH or TMAH solvent, after etching, a first textured surface with a crystal orientation of {111} is formed on the third and fourth surfaces of the first trench, and the A third texture with a crystal orientation of {111} is formed on the third and fourth surfaces of the second groove, and then polysilicon and amorphous silicon can be deposited on the first texture and the third texture or a combination thereof, and etch again to form a second texture on the first texture and a fourth texture on the third texture, the second texture may have a second type of doping, the third texture The texture may have a doping of the first type such that a texture layer comprising first and second textures is formed in the first groove and a texture layer comprising third and fourth textures is formed in the second groove Surface layer.

Thus, embodiments of the present invention provide a method of forming a substrate structure capable of forming a Great Wall-like structured substrate structure. The single crystal substrate with the first doping type is used to process the substrate by etching, and then the thickness of the substrate is effectively used to form a Great Wall structure, thereby improving the utilization rate of the surface area of the wafer. Furthermore, first and second textures are formed in the first groove of the substrate structure, and optionally, third and fourth textures are formed in the second groove. When the substrate structure is used in the application of the solar cell substrate, the textured surface can advantageously improve the light trapping effect, thereby increasing the light entry efficiency of the solar cell.

In particular, the substrate structure obtained by the method can be applied to the field of solar cells, and subsequent steps can be formed on the above structure, such as forming a first electrode on the second textured surface, and forming a first electrode on the second trench Forming the second electrode on the inner wall or the fourth suede, or other required steps, are the same as those described in the second embodiment, and will not be repeated here.

Fourth embodiment

The first embodiment, the second embodiment and the third embodiment of the present invention have been described above with reference to the accompanying drawings, and they are implemented based on a single crystal substrate. A substrate structure based on a polycrystalline substrate and a manufacturing method thereof according to a third embodiment of the present invention will be described below with reference to the accompanying drawings.

According to the fourth embodiment of the present invention, there is provided a substrate structure processed by using a substrate. Referring to FIG. 19 and FIG. 21 , the structure includes: a substrate unit array.

As shown in FIG. 19 , the substrate unit array includes a plurality of substrate units arranged in a predetermined direction, such as a plurality of substrate units 200 shown along direction A, preferably, they may be substantially parallel substrate units. Each substrate unit 200 includes a semiconductor substrate 101-x, which may be a polycrystalline substrate and may include, for example: polycrystalline Si, polycrystalline Ge, polycrystalline SiGe, III-V or II-VI compounds Semiconductors or combinations thereof. The semiconductor substrate includes a first surface 301 and a second surface 302 opposite thereto, a third surface 303 and a fourth surface 304 opposite thereto, wherein the third surface 303 is textured, and optionally, the The fourth surface 304 of the substrate unit can also be a suede surface, as shown in FIG. 21 . The structure further includes: a plurality of substrates 307-x and 308-x, the plurality of substrates are respectively disposed outside the first surface and the second surface of the semiconductor substrate. The plurality of substrates may be formed of the same or different material from the plurality of substrate units and include at least one layer, and the material may be, for example, insulating material, metal, semiconductor material or a combination thereof.

Wherein, for each of the spaced substrate units 200, its second surface and the second surface of the adjacent substrate on one side share a substrate to form the first groove 305, and its first surface and the other side The first surfaces of adjacent substrates share another substrate to form a second groove 306, and the opening direction of the first groove is opposite to that of the second groove, so that the substrate structure forms a Great Wall structure. In particular, the substrate structure further includes a first semiconductor layer 202 with a second doping type and a textured surface formed in the first trench 305 .

In particular, the first surface and the second surface 301/302 of the semiconductor substrate are two surfaces of the semiconductor substrate.

Furthermore, preferably, the substrate unit and the substrate connected thereto may be kept substantially vertical. And the depth of at least one of the first and second grooves is greater than twice the width of the substrate unit, and the width of the substrate unit is the distance between the surfaces corresponding to the side walls of two adjacent grooves belonging to the same substrate unit. The distance, that is, the distance between the third surface and the fourth surface of the same substrate unit. The thickness of the substrate is less than 1/3 of the width of the substrate unit.

Therefore, the embodiment of the present invention provides a substrate structure processed by using the substrate. The substrate structure has a Great Wall structure, which effectively utilizes the thickness of the substrate and improves the utilization rate of the surface area of the wafer. Moreover, the substrate The third surface of the unit is textured, and optionally the fourth surface may also be textured. When the substrate unit is used as a solar cell substrate, the textured surface can advantageously improve the light trapping effect, thereby increasing the light entry efficiency of the solar cell.

In particular, when applied to a solar cell substrate, referring to FIG. 22 and FIG. 23 , the substrate unit further includes: a second dopant doping layer formed on the textured third surface 303 of the semiconductor substrate 101 ; The first semiconductor layer 202 and the first electrode layer 204 thereon, and the second electrode layer 205 formed on the fourth surface 304 of the semiconductor substrate 101 . In addition, it may further include: a second semiconductor layer 203 with the first doping type formed between the fourth surface 304 of the semiconductor substrate and the second electrode layer 205 . Wherein the first electrode layer is a light-incoming surface, which can be formed of TCO materials, such as SnO ₂ , In ₂ O ₃ , ZnO, ITO, CdO, Cd ₂ SnO ₄ , FTO, AZO or combinations thereof. The second electrode layer can also be used as a light-incoming surface, that is, it can also be formed of a TCO material, alternatively, it can not be used as a light-incoming surface, and can be formed of a metal material suitable for conducting electricity. The thicknesses of the first electrode layer and the second electrode layer are respectively about 10-200 nm. Wherein the first and second semiconductor layers respectively include: polysilicon, amorphous silicon or a combination thereof. The thickness of the first and second semiconductor layers is about 10-500 nm, respectively.

Optionally, when applied to a solar cell substrate, the substrate unit may further include an anti-reflection layer formed on the first electrode layer, such as a nitride material. The anti-reflection layer may have a thickness of about 40-160 nm. Thereby, the light-introduction efficiency of the solar cell is further increased.

The novel substrate structure according to the third embodiment of the present invention has been described above with reference to the accompanying drawings, and the substrate structure can be applied in various fields such as the manufacture of semiconductor devices and the manufacture of thin-film solar cells. It should be noted that those skilled in the art can choose a variety of processes for manufacturing according to the above-mentioned substrate structure, such as different types of product lines, different process flows, etc., but as long as the substrate units and structures manufactured by these processes have the same Inventing basically the same structure and achieving basically the same effect should also be included in the protection scope of the present invention. In order to understand the present invention more clearly, the method and process for forming the above-mentioned substrate unit and structure of the present invention will be specifically described below. It should also be noted that the following steps are only illustrative and not limiting to the present invention. Technicians can also realize it through other techniques. The following embodiments are preferred embodiments of the present invention, which can effectively reduce manufacturing costs.

FIG. 24 shows a flow chart of a method for manufacturing a substrate structure according to an embodiment of the present invention. For the purpose of simplification, steps similar to those in the second embodiment of the present invention will not be repeated in this method.

In step S201 , as shown in FIG. 6 , a substrate 100 is provided. In one embodiment of the present invention, the substrate 100 is a polycrystalline semiconductor substrate, such as polycrystalline Si, polycrystalline Ge, polycrystalline SiGe, III-V or II-VI compound semiconductors or combinations thereof. In other embodiments, the semiconductor substrate can be produced in various ways, such as deposition, epitaxial growth, etc., and the substrate can have an N-type doping configuration or a P-type doping configuration. Wherein, the thickness of the semiconductor substrate may be 0.2-2mm, of course, the present invention is not limited thereto. The substrate includes a first surface 301 and a second surface 302, and the first surface 301 and the second surface 302 are opposite to each other. In particular, the substrate may include one or more layers, for example, the substrate may include a semiconductor layer 300 and material layers 307 , 308 formed above and below the semiconductor layer, as shown in FIG. 7 . The material layer may also include one or more layers, and the material used for each layer may be configured as required, for example, may include an insulating layer for etching stop, a conductive layer for conduction, and the like. The material layer may be formed of the same or different material as the semiconductor layer, including but not limited to insulating material, metal, semiconductor material or a combination of the above materials. All of these can be configured according to the needs in the actual application process, which is not limited in the present invention.

In step S202, etching the substrate 100 from the first surface 301 to form at least two first trenches 305, and etching the substrate 100 from the second surface 302 to form at least one second trench 306, wherein each Each of the second grooves 306 is located between two adjacent first grooves 305, and at least the inner wall of the first groove 305 forms a suede surface, as shown in FIG. 19 and FIG. 21 .

In one embodiment of the present invention, the substrate is respectively etched from the first surface 301 and the second surface 302 to form grooves 305, 306, and a textured surface is only formed on the inner wall of the first groove 305, as shown in Fig. 16, 17. Specifically, first, the first surface 301 of the substrate 100 is patterned: on the first surface 301 of the substrate 100, a photoresist layer 309 having a plurality of grooves arranged at predetermined intervals is formed ; etch the substrate 100 to remove the material layer 307 at the plurality of trenches of the first surface 301; remove the photoresist layer 309, thereby forming a multi- The first surface 301 is patterned by a layer of material 307 with two grooves. Then, the substrate 100 is patterned, and the substrate 100 is etched from the first surface 301 with the material layer 307 on the first surface as a hard mask to form at least two first grooves 305, as shown in FIG. 16 As shown, an anisotropic etching method may be selected to etch the substrate, such as a RIE (Reactive Ion Etching) method. Then, the device is wet etched, for example, using a solvent such as potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH), and the etchant will selectively stop at the {111} crystal plane of the substrate. , so that an uneven suede 303 surface is formed on the inner wall of the first groove 305, as shown in FIG. 17 . Then, the second surface 302 of the substrate 100 can be patterned: a photoresist layer 310 having a plurality of grooves arranged at predetermined intervals is formed on the second surface 302; the substrate is etched 100, to remove the material layer 308 at the multiple grooves of the second surface 302; remove the photoresist layer, thereby forming the material layer 308 with multiple grooves on the second surface, The patterning of the second surface 302 is realized, as shown in FIG. 18 . Then the substrate is patterned, using the material layer 308 on the second surface as a hard mask, etching the substrate 100 from the second surface 302 to form at least one second trench 306, wherein each of the The second trench 306 is located between two adjacent first trenches 305, as shown in FIG. 19, an anisotropic etching method can be selected to etch the substrate, such as RIE (reaction ion etching) method.

In another embodiment of the present invention, the substrate is respectively etched from the first surface 301 and the second surface 305 to form grooves 305 and 306, and textured surfaces are formed on the inner walls of the first 305 and the second groove 306, As shown in Figure 20. Specifically, the first surface 301 and the second surface 302 of the substrate 100 are patterned: on the first surface 301 of the substrate 100, a photoresist with a plurality of grooves arranged at predetermined intervals is formed Resist layer 309; etch the substrate 100 to remove the material layer 307 at the plurality of grooves on the first surface 301; remove the photoresist layer 309; and then on the second surface Form 302 a photoresist layer 310 with a plurality of grooves arranged at predetermined intervals; etch the substrate 100 to remove the material layer 308 at the plurality of grooves on the second surface 302; remove The photoresist layer, thereby patterning the substrate, forms material layers 307, 308 with a plurality of grooves on the first 301 and second surface 302, respectively. Then, using the material layers 307, 308 as hard masks, at least two first grooves 305 are etched from the first surface 301 of the substrate 100, and at least one trench is etched from the second surface 302 of the substrate 100. The second trenches 306, wherein each of the second trenches 306 is located between two adjacent first trenches 305, as shown in FIG. The substrate is etched by a method such as RIE (Reactive Ion Etching). Then, the device is wet etched, for example, using a solvent such as potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH), and the etchant will selectively stop at the {111} crystal plane of the substrate. Therefore, an uneven suede surface 303 is formed on the inner wall of the first groove 305, and an uneven suede surface 304 is formed on the inner wall of the second groove 306, as shown in FIG. 21 .

Of course, the patterning steps of the above-mentioned embodiments are only examples, and those skilled in the art can obtain the patterned substrate described in this embodiment through many methods known in the art, and these can be applied to this embodiment , without departing from the protection scope of the present invention.

Optionally, all or part of the semiconductor layer 300 can be etched, for example, the first surface 301 of the substrate can be etched and stop on the material layer 308 of the second surface 302, and the substrate can be etched. The second surface 302 of the bottom rests on the material layer 309 of the first surface 301 . Of course, only a part of the semiconductor layer may be etched, that is, the bottoms of the first trench and the second trench do not contact the material layers 308 , 309 . When the substrate is one layer, only part of the substrate can be etched. In FIG. 14 , the dark area defined by the solid line indicates the first trench 305 formed on the first surface 301, and the light area defined by the dotted line indicates the second trench 305 formed on the second surface 302. groove 306 . The first groove and the second groove may have equal or unequal intervals.

In particular, the substrate can be patterned so that the first groove and the second groove are substantially parallel, and these can be set according to design requirements. In this way, each of the second grooves 306 is located between two adjacent first grooves 305, so as to divide the substrate into at least two substrates and at least one substrate, and the substrate is formed by the first Defined by the side walls of the first groove 305 and the second groove 306, the substrate connects two adjacent substrates, so as to obtain a substrate structure with a Great Wall structure. Preferably, the depth 311 of one of the first groove 305 and the second groove 306 is greater than twice the substrate width (the distance between surfaces corresponding to the sidewalls of two adjacent grooves belonging to the same substrate) 310 .

In particular, when the plurality of first grooves 305 and the plurality of second grooves 306 are substantially parallel, the substrate array may include a plurality of substantially parallel substrates. In particular, the substrate and the substrate connected thereto may be substantially vertical, ie the first groove and the second groove may be substantially rectangular in shape.

Therefore, the embodiment of the present invention provides a method for forming a substrate structure, the method can form a substrate structure with a Great Wall structure, effectively utilize the thickness of the substrate to form a Great Wall structure, and improve the surface area utilization rate of the wafer . Moreover, a textured surface is formed on the inner wall of the first groove of the substrate structure, and optionally, a textured surface is formed on the side wall of the second groove, when the substrate structure is used for the application of a solar cell substrate , the suede surface can advantageously improve the light trapping effect, thereby increasing the light entering efficiency of the solar cell.

In step S203, subsequent processing is performed on the substrate structure. When applying the substrate structure obtained by the method to the field of solar cells, further, referring to FIG. 22 and FIG. The first semiconductor layer 202, and then the first electrode layer 204 is formed on the first semiconductor layer 202 on the sidewall of the first trench 305, and the second electrode layer 205 is formed on the sidewall of the second trench 306, The first electrode layer 204 is formed of a TCO material, and the TCO includes: SnO ₂ , In ₂ O ₃ , ZnO, ITO, CdO, Cd ₂ SnO ₄ , FTO, AZO or a combination thereof. In this example, the The first electrode layer 204 is a light-incoming surface. Optionally, the second semiconductor layer 203 with the first type of doping can also be formed at least between the sidewall of the second trench 306 and the second electrode 205, and the second electrode layer 205 can also be As the light-incoming surface, it can also be formed of TCO material. Optionally, the second electrode layer 205 may not serve as a light-incoming surface, and be formed of a metal material suitable for conducting electricity. The thicknesses of the first electrode layer 204 and the second electrode layer 205 are about 300-1000 nm respectively. The first 202 and the second semiconductor layer 203 respectively include: polysilicon, amorphous silicon or a combination thereof, and have a thickness of about 10-500 nm. Optionally, further, an anti-reflection layer (not shown in the figure), such as a nitride material, may also be formed on the light incident surface (the first electrode layer and/or the second electrode layer). The anti-reflection layer may have a thickness of about 40-160 nm. Thereby, the light-introduction efficiency of the solar cell is further increased.

Further, the substrate structure can be cut along the first groove and the second groove to form a substrate unit, or when the thickness of the substrate is thin enough, for example, less than 1/3 of the width of the substrate, it can be appropriately The process can easily stretch the substrate structure, so that the substrate unit arrays are formed on substantially the same plane, which is suitable for the next treatment and processing.

The method for manufacturing a substrate structure by using a semiconductor substrate in the embodiment of the present invention has been described above in detail. The method can form a substrate structure with a Great Wall structure, effectively utilize the thickness of the substrate to form a Great Wall structure, and improve the reliability of the wafer. Surface area utilization. Moreover, a textured surface is formed on the inner wall of the first groove of the substrate structure, and optionally, a textured surface is formed on the side wall of the second groove, when the substrate structure is used for the application of a solar cell substrate , the suede surface can advantageously improve the light trapping effect, thereby increasing the light entering efficiency of the solar cell. Moreover, a first semiconductor layer with a second doping type is formed in the first trench of the substrate structure, and optionally, a semiconductor layer with the first doping type is formed in the second trench. second semiconductor layer. When the substrate structure is used in the application of the solar cell substrate, the textured surface can advantageously improve the light trapping effect, thereby increasing the light entry efficiency of the solar cell.

Although the example embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made to these embodiments without departing from the spirit and scope of the invention as defined by the appended claims. For other examples, those of ordinary skill in the art will readily understand that the order of process steps may be varied while remaining within the scope of the present invention.

In addition, the scope of application of the present invention is not limited to the process, mechanism, manufacture, material composition, means, method and steps of the specific embodiments described in the specification. From the disclosure of the present invention, those of ordinary skill in the art will easily understand that for the processes, mechanisms, manufacturing, material compositions, means, methods or steps that currently exist or will be developed in the future, they are implemented in accordance with the present invention Corresponding embodiments described which function substantially the same or achieve substantially the same results may be applied in accordance with the present invention. Therefore, the appended claims of the present invention are intended to include these processes, mechanisms, manufacture, material compositions, means, methods or steps within their protection scope.

Claims (10)

1. the manufacture method that the formation method of utilizing substrate to carry out the base board unit of matte processing forms for matte, described method comprises:

A, provide single crystalline semiconductor substrate, described semiconductor substrate comprises first surface and second surface corresponding thereto and the 3rd surface and the 4th surface corresponding thereto;

B, by anisotropic wet, corrode on the 3rd surface and form the first matte;

C, on described the first matte, form the second matte.

2. method according to claim 1, also comprises:

D, by anisotropic wet, corrode and on the 4th surface, form the 3rd matte;

E, on described the 3rd matte, form the 4th matte.

3. method according to claim 1, wherein said semiconductor substrate comprises: single crystalline Si, monocrystalline Ge, single crystalline Si Ge.

4. method according to claim 1 and 2, wherein said the first matte, the 3rd matte are crystal orientation { 111}.

5. method according to claim 1 and 2, wherein said step C comprises:

A, on described the first matte, precipitate polysilicon, amorphous silicon or its combination;

B, by etching, form described the second matte;

Wherein step e comprises:

A, on described the 3rd matte, precipitate polysilicon, amorphous silicon or its combination;

B, by etching, form described the 4th matte.

6. a base board unit that utilizes substrate to carry out matte processing: comprising:

The single crystalline semiconductor substrate with the first doping type, described semiconductor substrate comprises first surface and second surface corresponding thereto and the 3rd surface and the 4th surface corresponding thereto;

Be formed at the 3rd lip-deep the first matte of described semiconductor substrate;

Be formed at the second matte on described the first matte.

7. base board unit according to claim 6, also comprises

Form the 4th lip-deep the 3rd matte with described semiconductor substrate;

Be formed at the 4th matte on described the 3rd matte.

8. base board unit according to claim 6, wherein said semiconductor substrate comprises: single crystalline Si, monocrystalline Ge, single crystalline Si Ge.

9. according to the base board unit described in claim 6 or 7, wherein said the first matte, the 3rd matte are crystal orientation { 111}.

10. according to the base board unit described in claim 6 or 7, wherein said the second matte, the 4th matte comprise polysilicon, amorphous silicon or its combination.

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