CN103515285A - Semiconductor structure and manufacturing process thereof - Google Patents

Abstract

The invention discloses a semiconductor structure and a manufacturing process thereof. The semiconductor structure comprises a liner layer, a silicon-rich layer and a filling material. The liner layer is located on the surface of the groove. The silicon-rich layer is located on the liner layer. The filling material is positioned on the silicon-rich layer and fills the groove. In addition, the invention also provides a semiconductor manufacturing process for forming the semiconductor structure.

Description

Semiconductor structure and its fabrication process

technical field

The invention relates to a semiconductor structure and its manufacturing process, and in particular to a semiconductor structure and its manufacturing process in which a silicon-rich layer is formed on the groove surface.

Background technique

In the current semiconductor manufacturing process, localized oxidation isolation (LOCOS) or shallow trench isolation (shallow trench isolation (STI)) is generally used to isolate components to avoid short circuits caused by mutual interference between components. However, as the design and manufacture of semiconductor chips become thinner and thinner, the pits, crystal defects and long bird's beaks produced in the LOCOS manufacturing process have shortcomings. , it will greatly affect the characteristics of the semiconductor chip, and the field oxide layer produced by the LOCOS method occupies a relatively large volume, which will affect the integration of the entire semiconductor chip. Therefore, in the submicron (submicron) semiconductor manufacturing process, the shallow trench isolation (shallow trench isolation, referred to as STI) manufacturing process, which is smaller in size and can increase the integration of semiconductor chips, has become a widely used isolation technology recently.

A typical STI manufacturing method is to make a groove between the MOS elements on the chip surface, and fill it with a dielectric material to produce the effect of electrical isolation. The dielectric substance is generally silicon oxide. When silicon oxide is formed, the high temperature in the step of forming silicon oxide or the subsequent manufacturing process will cause oxygen to diffuse into the silicon substrate next to the groove where the active region of the transistor is to be formed, and part of the silicon substrate is oxidized to form silicon oxide. In this way, not only the size of each SDI structure cannot be precisely controlled, but also the volume of the formed SDI structure increases, reducing the silicon base of the active region. However, as the size of semiconductor devices shrinks to close to the physical limit, different sizes of shallow trench isolation structures and active regions have seriously affected the electrical performance and manufacturing process quality of the devices thereon.

Contents of the invention

The object of the present invention is to provide a semiconductor structure and its manufacturing process, which forms a silicon-rich layer on the surface of the groove, especially the surface of the groove used to form the shallow trench isolation structure, so as to solve the above problems.

To achieve the above purpose, the present invention provides a semiconductor structure located in a groove of a substrate. The semiconductor structure includes a pad layer, a silicon-rich layer and a filling material. The backing layer is on the surface of the groove. The silicon-rich layer is on the liner layer. The fill material is on the silicon-rich layer and fills the grooves.

The present invention also provides a semiconductor manufacturing process, which includes the following steps. First, a groove is formed in a substrate. Next, a liner layer is formed to cover the surface of the groove. Next, a silicon-rich layer is formed on the liner layer. Then, filling a silicon nitride in the groove. Then, a conversion process is performed to convert the silicon nitride into silicon monoxide, and at least part of the silicon-rich layer is oxidized.

Based on the above, the present invention proposes a semiconductor structure and its manufacturing process, which forms a silicon-rich layer on the surface of the groove, especially the surface of the groove for forming a shallow trench isolation structure, and then fills silicon nitride in the groove , and then convert the silicon nitride into a filling material for insulation between active regions. In this way, since the present invention has formed a silicon-rich layer on the surface of the groove before filling the silicon nitride, it can prevent the components introduced during the transformation process, such as oxygen atoms, from diffusing into the substrate next to the groove, occupying part of the groove. The base of the active region and expand the volume of the formed shallow trench isolation structure.

Description of drawings

1-10 are schematic cross-sectional views of a semiconductor manufacturing process according to an embodiment of the present invention.

Description of main component symbols

110: base

120: hard mask layer

122: pad oxide layer

124: pad nitride layer

120': patterned hard mask layer

122': Patterned Pad Oxide

124': patterned pad nitride layer

130: Underlayment

130a: Planarized liner layer

140, 140a: silicon-rich layer

140b: planarized silicon-rich layer

150: Silicon nitride

160: filling material

160a: Planarized fill material

A, B: active area

G: shallow trench isolation structure

P1: Conversion Manufacturing Process

P2: Densification process

R: Groove

S: surface

S1, S2: contact surface

Detailed ways

1-10 are schematic cross-sectional views of a semiconductor manufacturing process according to an embodiment of the present invention. As shown in FIGS. 1-3 , a substrate 110 having a groove R is provided. In detail, as shown in FIG. 1, a substrate 110 is provided, wherein the substrate 110 is, for example, a silicon substrate, a silicon-containing substrate, a group III-V silicon-coated substrate (such as GaN-on-silicon), a graphene silicon-coated substrate (graphene-on-silicon) or a semiconductor substrate such as a silicon-on-insulator (SOI) substrate. Next, a hard mask layer 120 is formed on the substrate 110 . In this embodiment, the hard mask layer 120 may include a pad oxide layer 122 and a pad nitride layer 124 on the substrate 110 from bottom to top, but the invention is not limited thereto.

As shown in FIG. 2, the hard mask layer 120 is patterned to form a patterned hard mask layer 120', which includes a patterned pad oxide layer 122' and a patterned pad nitride layer 124'. The method for forming the patterned hard mask layer 120 ′ can be, for example, firstly using a photolithography method to form a patterned photoresist (not shown) on the hard mask layer 120 , the patterned The pattern of the photoresist (not shown) defines the position corresponding to the groove R to be formed thereunder. Etching is then performed, and a patterned hard mask layer 120' is formed using a patterned photoresist (not shown) pattern as a mask. Then, after selectively removing the patterned photoresist (not shown), as shown in FIG. A groove R is formed in the substrate 110 .

As shown in FIG. 4 , a liner layer 130 is formed to completely cover the substrate 110 , especially the surface S of the groove R. As shown in FIG. The liner layer 130 can be, for example, an oxide layer and/or a nitride layer, and can be formed, for example, by an in situ steam generation (ISSG) process, but the invention is not limited thereto.

As shown in FIG. 5 , a silicon-rich layer 140 is formed on the liner layer 130 . In this embodiment, the silicon-rich layer 140 is a silicon layer. However, in other embodiments, the silicon-rich layer 140 can also be a silicon nitride layer, a silicon monoxide layer, a silicon oxynitride layer, or a silicon carbon nitride layer, etc. The multiple compound material layers contain oxygen at a ratio lower than the normal constant composition, for example, if it is a silicon oxide layer, its molecular formula is SiOx, and x is less than 2. Furthermore, the silicon-rich layer 140 can be formed by a plasma-assisted chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process or an atomic layer deposition (Atomic Layer Deposition, ALD) process, etc., and what method is used to form the silicon-rich layer 140 It depends on the function of forming the silicon-rich layer 140 .

The purpose of forming the silicon-rich layer 140 in the present invention is to prevent components in the filling material (not shown) that is subsequently filled into the groove R and formed on the silicon-rich layer 140 or components introduced in subsequent manufacturing processes, Oxygen, for example, diffuses into the substrate 110 beside the groove R, occupies part of the active regions A and B where semiconductor structures such as transistors are to be formed, and expands the volume of the formed shallow trench isolation structure (not shown). Therefore, the method of preventing the filling material or components of the subsequent manufacturing process from contaminating the substrate 110 can be, for example: (1) absorbing the filling material or the components of the subsequent manufacturing process with the silicon-rich layer 140 , such as providing a reactive source of silicon to consume the filling material Oxygen atoms in the substrate 110 are prevented from entering into the substrate 110 by filling materials or oxygen components of subsequent manufacturing processes. At this time, the silicon-rich layer 140 preferably has a relatively loose structure, which can have enough space to absorb the components of the filling material or the subsequent manufacturing process. At this time, it is preferable to use plasma-assisted chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) ) fabrication process to form the silicon-rich layer 140 . Or, (2) directly prevent the filling material or components of the subsequent manufacturing process from entering the silicon-rich layer 140 . At this time, the silicon-rich layer 140 preferably has a denser structure, which can effectively block the filling material or components of the subsequent manufacturing process from entering the silicon-rich layer 140, and the silicon-rich layer 140 is therefore preferably suitable for atomic layer deposition (Atomic Layer Deposition). Layer Deposition, ALD) manufacturing process is formed.

In addition, the silicon-rich layer 140 is preferably formed on the liner layer 130. Since the silicon-rich layer 140 is rich in silicon components and the substrate 110 is generally a silicon substrate, the liner layer 130 can isolate the two, so that the formed silicon-rich layer 140 has a better structure, and the liner layer 130 can further prevent components in the filling material from entering the substrate 110 . Furthermore, when the stress of the silicon-rich layer 140 is relatively large, such as a silicon-rich silicon nitride layer with high stress, the liner layer 130 can serve as a stress buffer layer to prevent the silicon-rich layer 140 from peeling off.

As shown in FIG. 6 , a filler 150 is filled in the groove R. As shown in FIG. In this embodiment, the filler 150 is a silicon nitride; but in other embodiments, the filler 150 can also be a silicon oxide, etc., and the present invention is not limited thereto. The filler 150 is generally in a liquid state to fully fill the groove R, wherein the filler 150 includes, for example, trisilylamine (TSA), but the invention is not limited thereto. Because when the semiconductor element is miniaturized, the depth of the groove R can reach, for example, 3000 angstrom (angstrom), and the opening diameter is only 500 angstrom (angstrom). It is not easy to have a smooth section structure, so when the filler 150 is in a liquid state, it can completely flow into and fill the groove R with a high aspect ratio. Of course, in other embodiments, the filler 150 can also be in other physical states.

Next, as shown in FIG. 7 , a conversion process P1 is performed to convert the filling material 150 into a filling material 160 for insulation between two active regions A and B where semiconductor elements such as transistors are to be formed. In this embodiment, the filling material 160 is silicon monoxide, and when the filling material 150 is converted, the conversion process P1 will at least oxidize part of the silicon-rich layer 140 to form an oxygen-containing silicon-rich layer 140a. Since the silicon-rich layer 140 in this embodiment is a silicon layer, in a preferred embodiment, the silicon-rich layer 140 can be completely transformed into a silicon oxide layer. In this way, the silicon-rich layer 140 can be transformed into silicon oxide together with the filling material 160 for insulation, but the invention is not limited thereto. In other embodiments, when the silicon-rich layer 140 is a silicon nitride layer, the oxygen-containing silicon-rich layer 140a is a silicon oxynitride layer; when the silicon-rich layer 140 is a silicon carbon nitride layer, the oxygen-containing The silicon-rich layer 140a is a silicon oxynitride layer. In this embodiment, the conversion process P1 is an oxidation process, but the present invention is not limited thereto. Specifically, the oxidation process may include direct feeding of oxygen, ozone or water vapor. The manufacturing process temperature of the conversion manufacturing process P1 is, for example, 500° C.˜700° C. to fully convert the filler 150 into the filling material 160 . Of course, during the process of converting the filling material 150 into the filling material 160 , a part of the silicon-rich layer 140 is also oxidized to form an oxygen-containing silicon-rich layer 140 a. In one embodiment, the oxygen content of the oxygen-containing silicon-rich layer 140a presents a gradient distribution. For example, the oxygen content of the oxygen-containing silicon-rich layer 140a decreases from the contact surface S1 between the filling material 160 and the oxygen-containing silicon-rich layer 140a to the contact surface S2 between the oxygen-containing silicon-rich layer 140a and the liner layer 130. gradient distribution. The oxygen content of the oxygen-containing silicon-rich layer 140 a depends on the concentration of the injected oxygen or the structural density of the silicon-rich layer 140 . Based on the foregoing, when the silicon-rich layer 140 is formed by a plasma-assisted chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process, it has a relatively loose structure and can absorb more oxygen atoms, so the oxygen-rich layer 140 The silicon layer 140a contains more oxygen; when the silicon-rich layer 140 is formed by atomic layer deposition (Atomic Layer Deposition, ALD) manufacturing process, it has a relatively dense structure, which blocks most of the oxygen atoms out of it, making Fewer oxygen atoms are located therein, so the oxygen-containing silicon-rich layer 140a contains less oxygen.

As shown in FIG. 8 , a densification process P2 may optionally be performed to further densify the filling material 160 and the oxygen-containing silicon-rich layer 140 a. The densification process P2 may include a thermal process or an oxygen-containing process. The temperature of the densification process P2 is preferably higher than 1000° C. to achieve a significant densification effect. In a preferred embodiment, the process temperature of the densification process P2 is 1100°C. Similarly, the silicon-rich layer 140a of the present invention can also be used to absorb or block the oxygen atoms activated by the densification process P2 itself or by its high temperature.

Subsequently, the filling material 160, the oxygen-containing silicon-rich layer 140a and the liner layer 130 are planarized, and as shown in FIG. The liner layer 130a is flush with the hard mask layer 120'. Afterwards, the hard mask layer 120' is removed, as shown in FIG. 10 , to form a shallow trench isolation structure G. Then, semiconductor manufacturing processes such as transistors in the active regions A and B can be performed. The semiconductor fabrication process is well known to those skilled in the art and thus will not be repeated here.

Based on the above, the present invention first fills the filling material 150, and then performs the transformation process P1 to form the filling material 160 and oxidize at least part of the silicon-rich layer 140. A fluid chemical vapor deposition (flowable chemical vapor deposition, FCVD) can be applied. manufacturing process or a spin-on dielectric layer (spin-on dielectric, SOD) manufacturing process steps, but the present invention is not limited thereto.

In summary, the present invention proposes a semiconductor structure and its manufacturing process, which forms a silicon-rich layer on the surface of the groove, especially the surface of the groove for forming a shallow trench isolation structure, and then fills the silicon nitride in the groove In the trench, the silicon nitride is converted into a filling material for insulation between the two active regions. In this way, since the present invention forms a silicon-rich layer on the surface of the groove before filling the silicon nitride, it can prevent the components introduced in the conversion process or the components of the filling material itself, such as oxygen atoms, from diffusing to the surface of the groove. The substrate beside the groove occupies part of the substrate of the active region and expands the volume of the formed shallow trench isolation structure. Furthermore, the silicon-rich layer may include a silicon layer, a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, or a silicon carbon nitride layer, and the silicon-rich layer may be deposited by plasma-assisted chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) manufacturing process or atomic layer deposition (Atomic Layer Deposition, ALD) manufacturing process.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (19)

1. a semiconductor structure, is arranged in a groove of a substrate, and this semiconductor structure includes:

Laying, is positioned at the surface of this groove;

Silicon-rich layer, is positioned on this laying; And

Packing material, is positioned in this silicon-rich layer and fills up this groove.

2. semiconductor structure as claimed in claim 1, wherein this laying comprises oxide layer.

3. semiconductor structure as claimed in claim 1, wherein this silicon-rich layer comprises silicrete, silicon nitride layer, silicon oxide layer, silicon oxynitride layer or carbonitride silicon layer.

4. semiconductor structure as claimed in claim 1, wherein this silicon-rich layer comprises oxygen containing silicon-rich layer.

5. semiconductor structure as claimed in claim 4, wherein the oxygen content distribution gradient of this oxygen containing silicon-rich layer.

6. semiconductor structure as claimed in claim 5, wherein to distribute be that the contact-making surface to this silicon-rich layer and this laying successively decreases from the contact-making surface of this packing material and this silicon-rich layer to this gradient.

7. semiconductor structure as claimed in claim 1, wherein this packing material comprises silica.

8. a semiconductor fabrication process, includes:

Form a groove in a substrate;

Form the surface that a laying covers this groove;

Form a silicon-rich layer on this laying;

Insert a silicon nitride in this groove; And

Carry out a conversion manufacture craft, this silicon nitride is changed into silicon monoxide, and this silicon-rich layer of oxidized portion at least.

9. semiconductor fabrication process as claimed in claim 8, wherein this laying comprises oxide layer.

10. semiconductor fabrication process as claimed in claim 8, wherein this silicon-rich layer comprises with plasma auxiliary chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) manufacture craft or ald (Atomic Layer Deposition, ALD) manufacture craft forms.

11. semiconductor fabrication process as claimed in claim 8, wherein this silicon-rich layer comprises silicrete, silicon nitride layer, silicon oxide layer, silicon oxynitride layer or carbonitride silicon layer.

12. semiconductor fabrication process as claimed in claim 8, wherein the manufacture craft temperature of this conversion manufacture craft is 500 ℃～700 ℃.

13. semiconductor fabrication process as claimed in claim 8, wherein this conversion manufacture craft comprises an oxidation manufacture craft.

14. semiconductor fabrication process as claimed in claim 13, wherein this oxidation manufacture craft comprises and passes into oxygen, ozone or steam.

15. semiconductor fabrication process as claimed in claim 8, after carrying out this conversion manufacture craft, also comprise:

Carry out a densification manufacture craft, with this silica of densification and this silicon-rich layer.

16. semiconductor fabrication process as claimed in claim 15, wherein the manufacture craft temperature of this densification manufacture craft is higher than 1000 ℃.

17. semiconductor fabrication process as claimed in claim 16, wherein the manufacture craft temperature of this densification manufacture craft is 1100 ℃.

18. semiconductor fabrication process as claimed in claim 8, wherein this silicon nitride comprises trimethyl silicane alkanamine (trisilylamine, TSA).

19. semiconductor fabrication process as claimed in claim 8, the step of wherein inserting this silicon nitride and carrying out this conversion manufacture craft is first-class body chemical vapor phase growing (flowable chemical vapor deposition, FCVD) step of manufacture craft or a rotary coating dielectric layer (spin-on dielectric, SOD) manufacture craft.

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