CN103514934B - Address transition signal detection circuit - Google Patents

Abstract

The invention provides an address transition signal detection circuit which is characterized by comprising a delay amplifying circuit, wherein the delay amplifying circuit is used for delaying and inverting an input address signal and outputting the delayed and inverted address signal and amplifying and outputting the input address signal. By using the delay amplifying circuit, the delay inverting output can be carried out on the input address signal, the accuracy of the address conversion signal is ensured, the input address signal can be amplified and output at the same time, the attenuation of the address signal is avoided, and the use of a subsequent circuit is facilitated.

Description

Address transition signal detection circuit

technical field

The invention relates to an asynchronous circuit system, in particular to an address signal transition detection circuit.

Background technique

In the operation of asynchronous circuit system especially SRAM memory, when there is a change on the address line, it means to start a new read or write cycle. Although SRAM has no external clock and does not require additional timing and control signals, its memory operations are initiated by events on the address bus or the R/W signal. But this means that all circuits (like decoders and sense amplifiers) are implemented completely statically, so a change on one of the input signals (data or address bus, R/W) will pass through subsequent circuit levels in a primary and secondary manner. Therefore, such an all-static method is not feasible for larger-capacity memories in terms of area or power consumption. Therefore, it is necessary to generate a similar clock signal to trigger some internal circuits to prepare for reading and writing.

The address transition detection circuit ATD is used to detect the change on the address line and generate a pulse signal for the internal circuit. The width of the pulse signal is an important parameter. A pulse that is too wide will lead to the completion of address decoding, the word line is ready to be connected, and the precharging of the bit line has not yet completed, which directly leads to the delay of reading and writing. A pulse that is too narrow will result in insufficient charging of the bit line, resulting in a delay in the read cycle; in the case of a pulsed word line, it may result in a read failure.

Therefore, the ATD circuit plays an important role in the structure of SRAM and PROM modules. It is the source of most timing signals and is a part of the entire critical timing path.

Figure 1 is a commonly used address transition detection circuit in the prior art. Although this traditional address transition detection circuit can meet the requirements to a certain extent, the address signal is weakened during the detection of the address transition. , so that the output address signal is weak to a large extent, which also makes the address signal weaker, which is not conducive to the use of subsequent circuits. Even if the detected address transition signal is amplified, it will also affect subsequent circuits.

Contents of the invention

The technical problem to be solved by the present invention is to provide an address transition signal detection circuit capable of outputting effective address transition signals and amplifying the output address signals.

In order to solve the above technical problems, the present invention provides an address signal transition detection circuit, which includes a delay amplifier circuit, the delay circuit delays and inverts the input address signal, and simultaneously amplifies and outputs the input address signal.

Preferably, the delay amplifying circuit includes an address signal delayer and an address signal amplifier.

Preferably, the delay amplifier circuit further includes a start-up circuit.

Preferably, the startup circuit includes a transistor M1, a transistor M2, a transistor M3, a transistor M6 and a transistor M8, and the transistor M1 and the transistor M2 form an inverter;

The gate of the transistor M1 is electrically connected to the gate of the transistor M2 and then connected to the power supply ground, the emitter of the transistor M1 is connected to the power supply, the emitter of the transistor M2 is connected to the power supply ground, and the transistor M1 The collector of the transistor M2 is electrically connected to the collector as the output terminal of the inverter;

The output terminal of the inverter is electrically connected to the gate of the transistor M6 and the gate of the transistor M8 respectively, the emitter of the transistor M6 and the emitter of the transistor M8 are connected to the power ground, and the collector of the transistor M6 and The collector of the transistor M8 is electrically connected to the delayer;

The gate of the transistor M3 is connected to the power ground, the emitter of the transistor M3 is connected to the power, and the collector of the transistor M3 is electrically connected to the delayer.

Preferably, the delayer includes a transistor M4, a transistor M5 and a transistor M7, the gate of the transistor M4, the gate of the transistor M5 and the gate of the transistor M7 are electrically connected at the same time as the input terminal of the delayer to receive The address signal is input, the collector of the transistor M4, the collector of the transistor M5 and the collector of the transistor M7 are simultaneously electrically connected as the output end of the delayer, and the emitter of the transistor M4 is connected to the transistor M3. collector, the emitter of the transistor M5 is electrically connected to the collector of the transistor M6, and the emitter of the transistor M7 is electrically connected to the collector of the transistor M8.

Preferably, the address signal amplifier includes:

The inverting amplifier inverts and amplifies the weak "0" signal to output a strong "1" signal, or inverts and amplifies the weak "1" signal to output a strong "0" signal, which is used to invert and amplify the delayed address signal.

The first inverter receives the delayed and amplified address signal, and outputs a delayed inverted address signal corresponding to the input address signal;

The second inverter receives the inverted address signal output by the first inverter, and outputs a delayed in-phase address signal corresponding to the input address signal.

Preferably, the inverting amplifier includes a transistor M9, a transistor M10, a transistor M11 and a transistor M12;

The emitter of the transistor M9 is electrically connected to the power supply, the collector of the transistor M9 is electrically connected to the output end of the delayer, the gate of the transistor M9, the gate of the transistor M10, the collector of the transistor M11 The electrode and the collector of the transistor M12 are electrically connected as the output end of the inverting amplifier;

The emitter of the transistor M10 is electrically connected to the power ground, and the collector of the transistor M10 is electrically connected to the output end of the delayer;

The emitter of the transistor M11 is electrically connected to a power supply, and the gate of the transistor M11 is electrically connected to the output terminal of the delayer;

The emitter of the transistor M12 is electrically connected to the power ground, and the gate of the transistor M12 is electrically connected to the output terminal of the delayer.

Preferably, the first inverter includes a transistor M13 and a transistor M14, the gate of the transistor M13 and the gate of the transistor M14 are electrically connected as the input terminal of the first inverter, and the emitter of the transistor M13 The pole is connected to the power supply, the emitter of the transistor M14 is connected to the power ground, and the collector of the transistor M13 and the collector of the transistor M14 are electrically connected to serve as the output end of the first inverter.

Preferably, the second inverter includes a transistor M15 and a transistor M16, the gate of the transistor M15 and the gate of the transistor M16 are electrically connected as the input terminal of the second inverter, and the emitter of the transistor M15 The pole is connected to the power supply, the emitter of the transistor M16 is connected to the power ground, and the collector of the transistor M15 and the collector of the transistor M16 are electrically connected to serve as the output end of the second inverter.

Preferably, the address signal transition detection circuit further includes an exclusive OR gate, one end of the exclusive OR gate receives the input address signal, and the other end of the exclusive OR gate receives the delayed inverted address signal output by the delay circuit, and outputs the address change signal.

By using the delay amplifier circuit, the input address signal can be delayed and inverted to ensure the accuracy of the address transition signal, and the input address signal can also be amplified and output at the same time to avoid the attenuation of the address signal and facilitate the use of subsequent circuits. .

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment the present invention will be described in further detail:

Fig. 1 is an existing address transition signal detection circuit;

Fig. 2 is the schematic diagram of the delay amplification circuit of the address transition signal detection circuit embodiment of the present invention;

FIG. 3 is a schematic diagram of the address transition of an embodiment of the address transition signal detection circuit of the present invention.

detailed description

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the specific implementation modes of the present invention will be described in detail below in conjunction with the accompanying drawings, so that the above-mentioned and other purposes, features and advantages of the present invention will be clearer. Like reference numerals designate like parts throughout the drawings. The drawings have not been drawn to scale, emphasis instead being placed upon illustrating the gist of the invention.

The present invention provides an address signal transition detection circuit, which includes a delay amplifier circuit, the delay circuit delays, reverses, amplifies and outputs the input address signal, and at the same time amplifies and outputs the input address signal.

As shown in FIG. 2, the delay amplifier circuit includes an address signal delayer, an address signal amplifier and a startup circuit. The startup circuit includes a transistor M1, a transistor M2, a transistor M3, a transistor M6 and a transistor M8. The delayer includes a transistor M4, a transistor M5 and a transistor M7.

The gate of the transistor M1 is electrically connected to the gate of the transistor M2 and then connected to the power supply ground, the emitter of the transistor M1 is connected to the power supply, the emitter of the transistor M2 is connected to the power supply ground, and the collector of the transistor M1 is electrically connected to the collector of the transistor M2. connected as the output terminal of the inverter; the output terminal of the inverter is electrically connected to the gate of the transistor M6 and the gate of the transistor M8 respectively, the emitter of the transistor M6 and the emitter of the transistor M8 are connected to the power supply ground, and the transistor M6 The collector and the collector of the transistor M8 are electrically connected to the delayer; the gate of the transistor M3 is connected to the power ground, the emitter of the transistor M3 is connected to the power supply, and the collector of the transistor M3 is electrically connected to the delayer.

Address signal amplifiers include:

The inverting amplifier inverts and amplifies the weak "0" signal to output a strong "1" signal, or inverts and amplifies the weak "1" signal to output a strong "0" signal, which is used to invert and amplify the delayed address signal.

The first inverter receives the delayed and amplified address signal, and outputs a delayed inverted address signal corresponding to the input address signal;

The second inverter receives the inverted address signal output by the first inverter, and outputs a delayed in-phase address signal corresponding to the input address signal.

In this embodiment, the inverting amplifier includes a transistor M9, a transistor M10, a transistor M11 and a transistor M12. The first inverter includes a transistor M13 and a transistor M14. The second inverter includes a transistor M15 and a transistor M16.

The emitter of the transistor M9 is electrically connected to the power supply, the collector of the transistor M9 is electrically connected to the output terminal of the delayer, the gate of the transistor M9, the gate of the transistor M10, the collector of the transistor M11 and the collector of the transistor M12 are electrically connected to serve as a reverse The output end of the phase amplifier; the emitter of the transistor M10 is electrically connected to the power supply ground, and the collector of the transistor M10 is electrically connected to the output end of the delayer; the emitter of the transistor M11 is electrically connected to the power supply, and the gate of the transistor M11 is electrically connected to the delayer. Output end; the emitter of the transistor M12 is electrically connected to the power supply ground, the gate of the transistor M12 is electrically connected to the output end of the delayer, and the gate of the transistor M13 and the gate of the transistor M14 are electrically connected as the input end of the first inverter , the emitter of the transistor M13 is connected to the power supply, the emitter of the transistor M14 is connected to the power supply ground, the collector of the transistor M13 and the collector of the transistor M14 are electrically connected as the output end of the first inverter, the gate of the transistor M15 is connected to the transistor M16 The gate of the transistor M15 is electrically connected to the input terminal of the second inverter, the emitter of the transistor M15 is connected to the power supply, the emitter of the transistor M16 is connected to the power supply ground, and the collector of the transistor M15 is electrically connected to the collector of the transistor M16 as the second inverter. output terminal of the phaser.

In this embodiment, the transistor M1 and the transistor M2 form an inverter, which inverts the input GND signal and outputs it as a high level, thereby turning on the transistor M6 and the transistor M8. The transistor M3 , the transistor M6 and the transistor M8 respectively control the conduction of the transistor M4 , the transistor M5 and the transistor M7 . That is, the conduction of the start-up circuit causes the delay to be turned on.

The delayer delays and inverts the input address signal Address and transmits it to the inverting amplifier. The inverting amplifier inverts, amplifies and outputs the delayed and inverted address signal output by the delayer. The output address signal and the original address signal are output in the same phase at this time. The first inverter then inverts the signal output by the inverting amplifier again, and at this time outputs an address signal OUT-Address-B which is the inversion of the original input address. The address signal OUT-Address-B then outputs an amplified signal of the original input address signal through the second inverter.

As shown in Figure 3, the address signal transition detection circuit also includes an exclusive OR gate, one end of the exclusive OR gate receives the input address signal, and the other end of the exclusive OR gate receives the delayed inversion address signal output by the delay circuit, and outputs Address transition signal ATD.

By using the delay amplifier circuit, the input address signal can be delayed and inverted to ensure the accuracy of the address transition signal, and the input address signal can also be amplified and output at the same time to avoid the attenuation of the address signal and facilitate the use of subsequent circuits. .

In the foregoing description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the above descriptions are only preferred embodiments of the present invention, and the present invention can be implemented in many other ways different from those described here, so the present invention is not limited by the specific implementations disclosed above. At the same time, any person skilled in the art can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention without departing from the scope of the technical solution of the present invention, or modify it into an equivalent implementation of equivalent changes example. All the content that does not deviate from the technical solution of the present invention, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention still belong to the protection scope of the technical solution of the present invention.

Claims (5)

1. Address transition signal detection circuit, it is characterized in that, comprise a delay amplifier circuit, described delay amplifier circuit carries out delay inversion output to the address signal of input, amplifies and outputs the address signal of input simultaneously; Described delay amplifier circuit comprises An address signal delayer and an address signal amplifier; the delay amplifying circuit also includes a startup circuit; the address signal transition detection circuit also includes an exclusive OR gate, one end of the exclusive OR gate receives an input address signal, and the other end of the exclusive OR gate One end receives the delayed inversion address signal output by the delay amplifier circuit, and outputs an address transition signal; The address signal amplifier includes: an inverting amplifier, a first inverter, and a second inverter; The start-up circuit enables the address signal delayer to be turned on, and the address signal delayer delays and inverts the input address signal Address and transmits it to the inverting amplifier of the address signal amplifier, and the inverting amplifier converts the address signal The delayed and inverted address signal output by the address signal delayer is then inverted and amplified for output. At this time, the output address signal and the original address signal are in-phase output, and the first inverter of the address signal amplifier Then the signal output by the inverting amplifier is inverted again, and at this time, the address signal OUT-Address-B, which is the inversion of the original input address, is output, and the address signal OUT-Address-B is passed through the address signal amplifier. The second inverter outputs an amplified signal of the original input address signal; The address signal delayer includes a transistor M4, a transistor M5 and a transistor M7, the gate of the transistor M4, the gate of the transistor M5 and the gate of the transistor M7 are simultaneously electrically connected as the input end of the address signal delayer Receive the input address signal, the collector of the transistor M4, the collector of the transistor M5 and the collector of the transistor M7 are simultaneously electrically connected as the output end of the address signal delayer, and the emitter of the transistor M4 is connected to the The collector of the transistor M3, the emitter of the transistor M5 are electrically connected to the collector of the transistor M6, and the emitter of the transistor M7 is electrically connected to the collector of the transistor M8. 2. The address transition signal detection circuit according to claim 1, wherein the startup circuit comprises a transistor M1, a transistor M2, a transistor M3, a transistor M6 and a transistor M8, and the transistor M1 and the transistor M2 form an inverter ; The gate of the transistor M1 is electrically connected to the gate of the transistor M2 and then connected to the power supply ground, the emitter of the transistor M1 is connected to the power supply, the emitter of the transistor M2 is connected to the power supply ground, and the transistor M1 The collector of the transistor M2 is electrically connected to the collector as the output terminal of the inverter; The output terminal of the inverter is electrically connected to the gate of the transistor M6 and the gate of the transistor M8 respectively, the emitter of the transistor M6 and the emitter of the transistor M8 are connected to the power ground, and the collector of the transistor M6 and The collector of the transistor M8 is electrically connected to the address signal delayer; The gate of the transistor M3 is connected to the power ground, the emitter of the transistor M3 is connected to the power, and the collector of the transistor M3 is electrically connected to the address signal delayer. 3. The address transition signal detection circuit according to claim 1, wherein the inverting amplifier comprises a transistor M9, a transistor M10, a transistor M11 and a transistor M12; The emitter of the transistor M9 is electrically connected to the power supply, the collector of the transistor M9 is electrically connected to the output end of the address signal delayer, the gate of the transistor M9, the gate of the transistor M10, the transistor M11 The collector of the transistor M12 and the collector of the transistor M12 are electrically connected as the output terminal of the inverting amplifier; The emitter of the transistor M10 is electrically connected to the power ground, and the collector of the transistor M10 is electrically connected to the output terminal of the address signal delayer; The emitter of the transistor M11 is electrically connected to a power supply, and the gate of the transistor M11 is electrically connected to the output terminal of the address signal delayer; The emitter of the transistor M12 is electrically connected to the power ground, and the gate of the transistor M12 is electrically connected to the output terminal of the address signal delayer. 4. The address transition signal detection circuit according to claim 1, wherein the first inverter comprises a transistor M13 and a transistor M14, the gate of the transistor M13 is electrically connected to the gate of the transistor M14 as the The input end of the first inverter, the emitter of the transistor M13 is connected to the power supply, the emitter of the transistor M14 is connected to the power supply ground, and the collector of the transistor M13 is electrically connected to the collector of the transistor M14 as the first output of the inverter. 5. The address transition signal detection circuit according to claim 1, wherein the second inverter comprises a transistor M15 and a transistor M16, the gate of the transistor M15 is electrically connected to the gate of the transistor M16 as the The input end of the second inverter, the emitter of the transistor M15 is connected to the power supply, the emitter of the transistor M16 is connected to the power supply ground, and the collector of the transistor M15 is electrically connected to the collector of the transistor M16 as the second inverter. output of the inverter.