CN103513176B - Test the shielding circuit of the motherboard and its shielding method - Google Patents

Abstract

The invention discloses a shielding circuit for testing a mainboard and a shielding method thereof, which are used for testing the mainboard with a built-in display chip, and a display card is inserted into a first slot of the mainboard. The shielding circuit comprises a voltage output unit and a signal shielding unit. The signal shielding unit is coupled with the voltage output unit and the power supply ready signal output end of the display card and controls the voltage of the power supply ready signal output end to be a forbidden energy level, so that the display card cannot be detected by the mainboard after the software is restarted. When the mainboard is subjected to a power-on test, the signal shielding unit is electrically connected with the power supply ready signal output end of the display card, the voltage output unit outputs a high voltage level and outputs a low voltage level after a first period, and the mainboard is subjected to software reboot. The invention can make the mainboard not detect the display card by the signal shielding mode without pulling out the display card, thereby being convenient for testing the mainboard with the built-in display chip.

Description

Test the shielding circuit of the motherboard and its shielding method

technical field

The invention relates to a shielding circuit and a shielding method, in particular to a shielding circuit and a shielding method for testing a main board with a built-in display chip.

Background technique

With the advancement of technology, computers have become an indispensable technology product in daily life, and many electronic devices in computers, such as motherboards, hard disks, compact disc-readonly memory, floppy disks, graphics cards and peripherals Devices are constantly being improved and updated.

During the design or manufacturing process of these electronic devices, these electronic devices will be tested to test whether the designed or manufactured electronic devices meet the specifications, but some electronic devices in the computer need to be equipped with other electronic devices to be tested. Taking the motherboard used in a computer as an example, in order to test whether the slot can work normally, the graphics card is usually inserted into the motherboard for testing. However, some motherboards have a built-in graphics chip, and the graphics card must be removed when testing the built-in graphics chip. However, the above-mentioned action of plugging and unplugging will increase the steps for testers to operate the testing platform, thus increasing the testing time of the motherboard, and the testing process will be interrupted due to the removal of the graphics card.

Contents of the invention

The purpose of the present invention is to provide a shielding circuit and a shielding method for testing a motherboard, which can prevent the motherboard from detecting the graphics card through signal shielding without removing the graphics card, so as to test the motherboard with a built-in display chip.

The invention proposes a shielding circuit for testing a motherboard with a built-in display chip, and the graphics card is inserted into the first slot of the motherboard. The shielding circuit includes a voltage output unit and a signal shielding unit. The voltage output unit is used to output a high voltage level or a low voltage level. The signal shielding unit is coupled to the voltage output unit and the power-ready signal output terminal of the graphics card. When the voltage output unit outputs a low voltage level, the signal shielding unit controls the voltage of the power-ready signal output terminal to be a disabled level, so that the motherboard can be turned off after the software restarts. Graphics card not detected. When the motherboard is running a power-on test, the signal shielding unit is electrically connected to the power-ready signal output terminal of the graphics card, the voltage output unit outputs a high voltage level and after the first period, the voltage output unit outputs a low voltage level, and the motherboard performs a software restart .

In an embodiment of the present invention, after the voltage output unit outputs a low voltage level for a second period, the signal shielding unit floats to the output end of the power ready signal to restore the voltage of the output end of the power ready signal to an enable level.

In an embodiment of the present invention, the signal shielding unit includes a time control unit and a voltage control unit. The time control unit is coupled to the voltage output unit. The first time signal is output after the voltage output unit outputs the high voltage level for a first period. The second time signal is output after the voltage output unit outputs the low voltage level for a second period. The voltage control unit is coupled to the voltage output unit and the time control unit. When the time control unit outputs the first time signal, the voltage control unit controls the voltage at the output terminal of the power ready signal to be a disabled level. When the time control unit outputs the second time signal, the voltage control unit floats the output terminal of the power ready signal, so that the voltage of the output terminal of the power ready signal returns to the enabling level.

In an embodiment of the present invention, the time control unit includes an RC delay circuit, and the first period is greater than or equal to the time required for the RC delay circuit to charge to a saturated state.

In an embodiment of the present invention, the time control unit determines the second period according to a time constant of discharge of the RC delay circuit.

In an embodiment of the present invention, the time control unit includes a plurality of switches for setting the impedance value of the RC delay circuit to determine the second period.

In an embodiment of the invention, the second period is longer than the device detection period of the main board.

In an embodiment of the present invention, the voltage output unit outputs a low voltage level by default.

In an embodiment of the present invention, the voltage output unit includes a general-purpose input and output port for outputting the high voltage level and the low voltage level to the signal shielding unit.

In one embodiment of the present invention, the voltage output unit includes a universal serial bus to be coupled to the main board to receive the first command and the second command, the voltage output unit outputs a high voltage level according to the first command, and outputs a low voltage level according to the second command. voltage level.

In an embodiment of the present invention, the voltage output unit is a control chip configured on the main board.

In one embodiment of the present invention, the signal shielding unit is in the form of an interface sheet and is inserted into the second slot of the motherboard, and the signal shielding unit is coupled to the power ready signal of the graphics card through the signal line shared by the first slot and the second slot. output.

In an embodiment of the present invention, the first slot and the second slot are PCI-E interfaces.

The invention also proposes a shielding method for testing the mainboard, which is used for testing the mainboard with the built-in display chip, and the graphics card is inserted into the slot of the mainboard. The shielding method includes: the signal shielding unit is electrically connected to the power ready signal output end of the graphics card. The main board performs a power-on test; the voltage output unit outputs a high voltage level to the signal shielding unit. The voltage output unit outputs a low voltage level, so that the signal shielding unit controls the voltage at the output end of the power ready signal to be at a disabled level. The motherboard performs a software reboot.

In an embodiment of the present invention, the shielding method further includes: after the voltage output unit outputs a low voltage level for a period of time, the signal shielding unit is floated to the output terminal of the power ready signal, so that the voltage of the output terminal of the power ready signal is restored to a uniform value. energy level.

The beneficial effect of the present invention is that, based on the above, the shielding circuit and shielding method of the embodiment of the present invention will lower the voltage of the power-ready signal output terminal of the graphics card when testing the motherboard with a built-in display chip, so that the motherboard can be restarted by software. Finally, the graphics card cannot be detected and the built-in graphics chip is turned on. Therefore, when testing the motherboard, it is not necessary to remove the graphics card so that the motherboard can be displayed through the built-in display chip, so as to avoid adding steps in the testing process, thereby saving testing time.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

1 is a schematic diagram of a shielding circuit coupled to a graphics card and a motherboard according to an embodiment of the present invention;

FIG. 2 is an operation timing diagram of the shielding circuit in FIG. 1 according to an embodiment of the present invention;

FIG. 3 is a flowchart of a masking method according to an embodiment of the invention.

detailed description

FIG. 1 is a schematic diagram of a shielding circuit coupled to a graphics card and a motherboard according to an embodiment of the invention. Referring to FIG. 1 , in this embodiment, assume that the motherboard 10 is configured with a built-in graphics chip, and the graphics card 20 is inserted into the PCI-EX16 slot (ie, the first slot) of the motherboard 10 to couple to the motherboard 10 . When the graphics card 20 is inserted into the slot of the motherboard 10, the voltage of the power-good signal output terminal T _PGD of the graphics card 20 will be an enable level (for example, a high voltage level), that is, output the power-good signal to the motherboard 10, To inform the motherboard 10 that there is a slot being used, and when the graphics card 20 is detected, the motherboard 10 will turn off the built-in graphics chip. When the shielding circuit 100 is coupled to the power-good signal output terminal T _PGD of the graphics card 20, when the motherboard 10 is scanning slots, the shielding circuit 100 controls the voltage of the power-good signal output terminal T _PGD to be a disabled level, such as a low-voltage voltage. flat, so that the motherboard 10 mistakenly thinks that the slot is not used and the graphics card 20 cannot be detected, and then the motherboard 10 will turn on its built-in display chip. Therefore, when the graphics card 20 is installed on the motherboard 10 with a built-in graphics chip, it is not necessary to unplug the graphics card 20 to enable the motherboard 10 to turn on its built-in graphics chip, so that the motherboard 10 can be turned on for a test.

Further, the shielding circuit 100 includes a voltage output unit 110 and a signal shielding unit 120 . The voltage output unit 110 includes, for example, a general-purpose input-output interface (GPIO), so as to output the high voltage level and the low voltage level to the signal shielding unit 120 through the general-purpose input-output interface. The voltage output unit 110 may be a control chip (such as a south bridge or a north bridge) configured on the motherboard 10 and including a general input and output interface. Alternatively, the voltage output unit 110 may be an external device, and the voltage output unit 110 includes, for example, a Universal Serial Bus (USB), so as to be coupled to the motherboard 10 through the Universal Serial Bus (USB) to receive the first command CMD1 and the second command CMD2 .

The signal shielding unit 120 may be in the form of an interface sheet, and is inserted into the PCI-EX1 slot (ie, the second slot) of the motherboard 10 . When the PCI-E slots of the motherboard share the same power ready signal line, the signal shielding unit 120 can be coupled to the power ready signal output of the graphics card 20 through the power ready signal line shared by the PCI-EX16 slot and the PCI-EX1 slot. terminal T _PGD . Otherwise, the signal shielding unit 120 can be directly coupled to the power-good signal output terminal T _PGD of the graphics card 20 through a wire.

FIG. 2 is a timing diagram of the operation of the masking circuit shown in FIG. 1 according to an embodiment of the present invention. Please refer to FIG. 1 and FIG. 2. In this embodiment, the waveform S1 is the voltage sequence output from the voltage output unit 110 to the signal shielding unit 120, and the waveform S2 is the coupling relationship between the signal shielding unit 120 and the power-good signal output terminal T _PGD . timing. When the voltage output unit 110 is not controlled, it outputs a low voltage level, that is, the voltage output unit 110 outputs a low voltage level by default. When the voltage output unit 110 receives the first command CMD1, it will output a high voltage level to the signal masking unit 120 according to the first command CMD1. The signal shielding unit 120 will be in an activated state after receiving the high voltage level and passing through the first period T1.

Then, output the second command CMD2 to the voltage output unit 110 . When the voltage output unit 110 receives the second command CMD2, it will output a low voltage level to the signal shielding unit 120 in the activated state according to the second command CMD2. At this time, the signal shielding unit 120 will control the power supply ready signal output terminal T _PGD The voltage is at a disable level, that is, the voltage at the output terminal T _PGD of the power ready signal is pulled down to a low voltage level (as shown by the solid line of the waveform S2 ). After the signal shielding unit 120 pulls down the voltage of the power good signal output terminal T _PGD , it outputs a software restart command CMDSR to the motherboard 10 to enable the motherboard 10 to perform a software restart. After the motherboard 10 is restarted by software, the signal shielding unit 120 pulls down the voltage of the power-good signal output terminal T _PGD , so that the motherboard 10 mistakenly thinks that the graphics card 20 does not exist, so the graphics card 20 cannot be detected.

In addition, in order to prevent the motherboard 10 from operating abnormally due to lowering the voltage of the power-good signal output terminal T _PGD , the signal shielding unit 120 of this embodiment is designed to be in a state after the second period T2 after the voltage output unit 110 outputs a low voltage level. Disabled. When the signal shielding unit 120 is in the closed state, the signal shielding unit 120 and the power ready signal output terminal T _PGD will be in a floating state (as shown by the dotted line of waveform S2), that is, the signal shielding unit 120 is floating connected to the power ready signal output terminal T _PGD , so the voltage at the power good signal output terminal T _PGD will return to a high voltage level. Wherein, the second period T2 includes the period during which the motherboard 10 detects the socket (ie, the device detection period), that is, the second period T2 is longer than the device detection period of the motherboard 10 , so that the motherboard 10 will not detect the graphics card 20 .

According to the above, during the period T2, the signal shielding unit 120 is in the activated state, and the signal shielding unit 120 pulls down the voltage of the power ready signal output terminal T _PGD , so the voltage of the power ready signal output terminal T _PGD will be a low voltage level; during the period Except for T2, the signal shielding unit 120 is in the closed state, and the signal shielding unit 120 and the power good signal output terminal T _PGD are in a floating state, so the voltage of the power good signal output terminal T _PGD is a high voltage level.

Further, the signal shielding unit 120 includes a voltage control unit 121 and a time control unit 123 , the voltage control unit 121 is coupled to the voltage output unit 110 and the time control unit 123 , and the time control unit 123 is coupled to the voltage output unit 110 . When the voltage output unit 110 outputs a high voltage level, the voltage control unit 121 and the power good signal output terminal T _PGD will be in a floating state, so the voltage of the power good signal output terminal T _PGD will be a high voltage level. After the voltage output unit 110 outputs a high voltage level and after the first period T1, the time control unit 123 will output the enabled time signal ST (for example, a high voltage level, that is, the first time signal); otherwise, the time control unit 123 outputs a disabled time signal ST (for example, a low voltage level, that is, a second time signal).

When the voltage output unit 110 outputs a low voltage level and the time control unit 123 outputs the enabled time signal ST, the voltage control unit 121 pulls down the voltage of the power-good signal output terminal T _PGD . When the voltage output unit 110 outputs a low voltage level and the time control unit 123 outputs a disabled time signal ST, the voltage control unit 121 and the power-good signal output terminal T _PGD are in a floating state.

In addition, the time control unit 123 can configure the RC delay circuit to determine the second period T2 according to the discharge time constant of the RC delay circuit, and the first period T1 is greater than or equal to the time required for the RC delay circuit to charge to a saturated state. Moreover, the time control unit 123 sets the impedance value of the RC delay circuit through a plurality of switches to determine the second period T2. For example, when the capacitance value is fixed, the resistance value of the resistor coupled to the capacitance can be selected through a switch, wherein the switch can be a jumper switch (jump) or other types of switches, and embodiments of the present invention do not limited to this.

According to the above-mentioned embodiments, a shielding method can be assembled to be applied to a shielding circuit coupled to a graphics card, wherein the graphics card is installed on the mainboard to be tested, and the mainboard has a built-in display chip. FIG. 3 is a flowchart of a masking method according to an embodiment of the invention. Please refer to FIG. 3 , in this embodiment, the signal shielding unit is electrically connected to the power-ready signal output end of the graphics card (step S310 ), and a power-on test is performed on the motherboard (step S320 ). Next, the voltage output unit outputs the high voltage level to the signal shielding unit (step S330 ). Then, the voltage output unit outputs a low voltage level, so that the signal shielding unit controls the voltage of the power-ready signal output end of the graphics card to be a disabled level (step S340 ), and makes the mainboard restart by software (step S350 ). Next, after the voltage output unit outputs the low voltage level for a period of time, the signal shielding unit floats the power-ready signal output end, so that the voltage of the power-ready signal output end returns to the enabling level (step S360 ). For details of the above steps, reference may be made to the description of the above embodiments, which will not be repeated here.

To sum up, the shielding circuit and shielding method of the embodiment of the present invention will lower the voltage of the power-ready signal output terminal of the graphics card when testing the motherboard with a built-in display chip, so that the motherboard cannot detect the graphics card after the software restarts. And turn on the built-in graphics chip. Therefore, when testing the motherboard, it is not necessary to remove the graphics card so that the motherboard can be displayed through the built-in display chip, so as to avoid adding steps in the testing process, thereby saving testing time. Moreover, after the device detection period, the shielding circuit floats the output terminal of the power ready signal, so that the voltage of the output terminal of the power ready signal returns to the enabling level, so as to prevent the abnormal operation of the main board from affecting the test result.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention should be defined by the claims.

Claims (14)

1. a kind of shielding circuit, is used for testing the motherboard of built-in display chip, and graphics card is inserted in the first slot of described motherboard, it is characterized in that, described shielding circuit comprises: a voltage output unit for outputting a high voltage level or a low voltage level; and The signal shielding unit is coupled to the voltage output unit and the power-ready signal output terminal of the graphics card, and when the voltage output unit outputs the low voltage level, the signal shielding unit controls the voltage of the power-ready signal output terminal to be disabled level, so that the motherboard cannot detect the graphics card after the software restarts, Wherein, when the motherboard performs a power-on test, the signal shielding unit is electrically connected to the power-ready signal output terminal of the graphics card, and the voltage output unit outputs the high voltage level and after the first period, the The voltage output unit outputs the low voltage level, and the main board performs the software restart; after the voltage output unit outputs the low voltage level for a second period, the signal shielding unit floats the the power-ready signal output terminal, so that the voltage of the power-ready signal output terminal returns to the enabling level. 2. The shielding circuit according to claim 1, wherein the signal shielding unit comprises: A time control unit, coupled to the voltage output unit, outputs a first time signal after the voltage output unit outputs the high voltage level for the first period, and outputs the low voltage after the voltage output unit outputting a second time signal after the level passes through the second period; and A voltage control unit, coupled to the voltage output unit and the time control unit, when the time control unit outputs the first time signal, the voltage control unit controls the voltage at the output terminal of the power ready signal to be the disabled level, when the time control unit outputs the second time signal, the voltage control unit floats the output terminal of the power ready signal, so that the voltage of the output terminal of the power ready signal returns to the energy level. 3. The shielding circuit according to claim 2, wherein the time control unit comprises an RC delay circuit, and the first period is greater than or equal to the time required for the RC delay circuit to charge to a saturated state. 4. The shielding circuit according to claim 3, wherein the time control unit determines the second period according to a time constant of discharge of the RC delay circuit. 5 . The shielding circuit according to claim 4 , wherein the time control unit comprises a plurality of switches for setting an impedance value of the RC delay circuit to determine the second period. 6 . The shielding circuit according to claim 1 , wherein the second period is longer than a device detection period when the motherboard is turned on. 7 . 7. The shielding circuit according to claim 1, wherein the voltage output unit outputs the low voltage level by default. 8 . The shielding circuit according to claim 1 , wherein the voltage output unit comprises a general-purpose input and output interface for outputting the high voltage level and the low voltage level to the signal shielding unit. 9. The shielding circuit according to claim 1, wherein the voltage output unit comprises a universal serial bus to couple to the main board to receive the first command and the second command, and the voltage output unit according to the The first command outputs the high voltage level, and the second command outputs the low voltage level. 10. The shielding circuit according to claim 1, wherein the voltage output unit is a control chip configured on the main board. 11. The shielding circuit according to claim 1, wherein the signal shielding unit is in the form of an interface sheet and is inserted into the second slot of the main board, and the signal shielding unit communicates with the first slot through the first slot. The signal line shared by the second slots is coupled to the power-ready signal output end of the graphics card. 12. The shielding circuit according to claim 11, wherein the first slot and the second slot are PCI-E interfaces. 13. A shielding method for testing a motherboard, for testing a motherboard with a built-in display chip, and the graphics card is inserted into the slot of the motherboard, it is characterized in that the shielding method comprises the following steps: The signal shielding unit is electrically connected to the power-ready signal output end of the graphics card; The motherboard is powered on for a test; The voltage output unit outputs a high voltage level to the signal shielding unit; The voltage output unit outputs a low voltage level, so that the signal shielding unit controls the voltage of the power-ready signal output terminal to be a disabled level; and The motherboard performs a software restart. 14. the shielding method of test motherboard according to claim 13, is characterized in that, described shielding method also comprises the following steps: After the voltage output unit outputs the low voltage level for a period of time, the signal shielding unit floats the output terminal of the power ready signal, so that the voltage of the output terminal of the power ready signal returns to an enable level.