CN103500150A - Bus framework for multiple processors to process applications concurrently - Google Patents

Abstract

The invention relates to a bus architecture for multiprocessor parallel processing applications. The bus is N sections of sub-buses arranged in parallel, and each section of sub-buses is connected to at least one CPU plug-in, and N is a natural number greater than or equal to 2. Parallel buses (that is, provide more available resources), single public bus competition, transformed into bus competition within the segment; due to the reduction in the number of CPUs in the segment, the load on the bus in the segment is improved; and mutual Independent and independent of each other, so in general, compared with the traditional single parallel bus structure, the segmented multi-bus structure significantly weakens the competition bottleneck of bus resources; the segmented multi-bus structure is the configuration of DC transmission application functions in a chassis Optimization provides a more reasonable choice.

Description

Bus Architecture for Multiprocessor Parallel Processing Applications

technical field

The invention relates to a bus architecture for multiprocessor parallel processing applications.

Background technique

The control and protection platform is the core equipment of the secondary side of the converter station of the direct current transmission project, and is the nerve center of the direct current transmission control and protection system. In HVDC power transmission projects, the control and protection platform is used in many occasions such as station control, pole control, valve group control, AC and DC protection, etc. To sum up their common characteristics, they are all multi-processor parallel processing applications, that is, according to the complexity of the application, several CPUs are configured in one chassis, and each CPU is combined with the corresponding peripheral I/O plug-in to form multiple CPUs with specific functions. processing collection. But in the traditional design, all CPUs and peripheral plug-ins in a chassis are inserted (shared) on a parallel bus backplane. In this way, when any CPU in the chassis needs to use bus resources (such as accessing its attached peripheral plug-ins or accessing other CPU data), it will exclusively occupy the backplane bus, and the tasks associated with bus access of other CPU plug-ins will be restricted. Influence.

With the promotion and in-depth popularization of digital substation technology based on IEC61850 standard, the research and equipment development of intelligent converter station system in the application of DC transmission projects have also entered a substantive stage.

At present, the mainstream DC transmission control and protection platforms mostly adopt the multi-processing architecture based on the standard high-speed parallel bus backplane. However, the parallel backplane is a competing common resource for multiple CPUs in the chassis. When multiple CPUs initiate bus access requests at the same time, bus resources must be obtained through bus arbitration and the right to use the bus must be obtained before they can occupy bus resources and complete related data access, which will have an extremely adverse impact on tasks that require high real-time performance. With the proposal and development of the concept of intelligent converter station, higher requirements are put forward for the DC transmission control and protection platform, requiring it to be able to withstand more frequent and larger data communications, so as to meet the rapid response requirements of tasks and make the control and protection platform The access bottleneck problem of the parallel bus in the platform is more prominent. Therefore, it is of great significance to develop a new parallel processing architecture and improve the bus utilization efficiency of the system.

Contents of the invention

The purpose of the present invention is to provide a bus architecture for multiprocessor parallel processing applications to solve the bus contention problem existing in the existing multiprocessor parallel processing applications.

In order to achieve the above object, the bus architecture technical scheme of the multiprocessor parallel processing application of the present invention is as follows: the bus is N sections of sub-buses arranged in parallel, each section of sub-buses is connected with at least one CPU plug-in, and N is a natural number greater than or equal to 2.

The N is set to 3.

Also be provided with the communication bus that communicates with the CPU plug-in of each sub-bus, the communication bus includes M serial channels, each CPU plug-in is provided with at least M communication interfaces, and each communication interface of each CPU plug-in is connected to each serial channel. Channels are connected in one-to-one correspondence.

One of the communication ports of each CPU plug-in is a sending port, and the other communication ports are receiving ports; the sending ports of each CPU plug-in are in one-to-one correspondence with each serial channel.

The bus architecture of the multiprocessor parallel processing application of the present invention segments the parallel bus to provide multiple parallel buses (that is, to provide more available resources), and the single public bus competition is converted into bus competition in the segment; due to the division The number of CPUs in the segment is reduced, and the load of the bus in the segment is improved; and the segments are independent of each other and do not affect each other, so that in general, compared with the traditional single parallel bus structure, the segmented multi-bus reduces bus resources. The bottleneck of the competition is significantly weakened; the segmented multi-bus structure provides a more reasonable choice for the configuration optimization of DC transmission application functions in a chassis. In this way, the phenomenon of preempting the bus between the segments is avoided, and at the same time, the functional units are well divided; the multi-transmitting node serial bus is used for data exchange between multi-processors, which not only solves the problem of arbitrary slot processing It also improves the communication efficiency between processors and satisfies the multi-task and multi-CPU parallel processing applications with high real-time requirements; it has good continuity and forward compatibility in technology, It can save subsequent research and development investment, only need to partially change the CPU and backplane, and other types of IO plug-ins do not need to be changed, so that the investment benefit can be maximized.

Description of drawings

Fig. 1 is the structural representation of segmented parallel bus embodiment;

Fig. 2 is a schematic diagram of the principle of serial bus technology with multiple transceiver nodes;

Fig. 3 is a schematic structural diagram of an embodiment of a fully switched serial bus.

Detailed ways

1. Bus architecture for multiprocessor parallel processing applications: segmented parallelism

As shown in Figure 1, in the bus architecture for multiprocessor parallel processing applications, the bus is N sections of sub-buses set in parallel, each section of sub-buses is connected to at least one CPU plug-in, N is a natural number greater than or equal to 2, and the setting of N value is the same as The number of CPU boards and I/O boards is related. Set N to 3 here.

The traditional shared parallel bus is segmented (divided into 3 segments), and each segment is a fully functional parallel bus backplane structure, forming a segmented multi-bus architecture from the perspective of the overall chassis.

In the application of HVDC power transmission system, it is most common that there are less than or equal to 3 CPUs in one chassis. Then, if a high-speed parallel bus is divided into three parallel buses, most of the application needs will be met. Of course, a spare sub-bus can also be added for use when more processors are used. Physically speaking, if the original parallel bus is segmented into multiple sub-buses, each sub-bus is the same as the original parallel bus in terms of data transmission and principle, that is, each of the N segments is a fully functional parallel bus structure , forming a segmented multi-bus architecture from the perspective of the overall chassis.

Provide multiple parallel buses (that is, provide more available resources), and convert the competition for a single common bus within a chassis into the bus contention within a segment. Since the number of CPUs in the segment is reduced, the load of the bus in the segment is improved; and the segments are independent of each other and do not affect each other, so in general, compared with the traditional single parallel bus structure, segmented multi-buses use The contention bottleneck of bus resources is significantly weakened.

The segmented multi-bus structure provides a more reasonable choice for the configuration optimization of DC transmission application functions in a chassis. For example: the communication task processing set (usually composed of a processor plug-in, two fieldbus communication plug-ins, and two Ethernet plug-ins) with field layer devices and operation monitoring layer devices can be configured into a bus segment. The communication data volume of this application is relatively large, and it is uniformly processed by one CPU. In this way, the processing of communication tasks will not be affected by other CPUs due to bus contention, and at the same time, tasks in other CPUs will not be affected.

After the bus is segmented, the situation of multi-CPU competing for the bus is significantly alleviated, and the situation of bus competition is eliminated when the number of CPUs is less than or equal to 3. But the disadvantage is: if the number of CPUs is greater than 3, then there must be more than 1 CPU in a certain segment. Then in this segment, the communication between CPUs not only needs to share the memory board, but also has bus conflicts; in addition, the CPUs in the segment will not be able to communicate through the backplane.

In order to solve this problem, a fully switched serial bus is designed on the backplane bus terminal, which solves the communication problem between multiple CPUs well.

2. Bus Architecture for Multiprocessor Parallel Processing Applications: Fully Switched Serial

Serial bus: As the speed of the parallel bus increases, the problem of crosstalk between lines becomes more prominent. In recent years, with the development of high-speed serial communication technology, from the early RS485 up to 10M to the current LVDS close to 2G, the serial communication rate has been greatly improved, and the serial communication bus has also emerged.

The serial bus of the bus architecture of the multi-processor parallel processing application adopts the serial bus technology of multiple transceiver nodes, which can realize one transmission and multiple reception, and the maximum rate can reach 500Mbps. In this structure, multiple transceivers can be connected to the same bus, as shown in Figure 2, the sending and receiving state can be controlled by controlling the sending and receiving directions, thus allowing two-way half-duplex communication.

The bus architecture for multiprocessor parallel processing applications The parallel bus is N sections of sub-buses arranged in parallel, and each section of sub-buses is connected to at least one CPU plug-in; there is also a communication bus for communicating with the CPU plug-ins of each section of sub-buses, and there are M CPU plug-ins in total , the communication bus includes M serial channels, each CPU plug-in is provided with at least M communication interfaces, and each communication interface of each CPU plug-in is connected to each serial channel in a one-to-one correspondence. One of the communication interfaces of each CPU plug-in is a sending interface, and the other communication interfaces are receiving interfaces; the sending ports of each CPU plug-in correspond to each serial channel one by one. Both M and N are natural numbers greater than or equal to 2. One-to-one correspondence means that each CPU plug-in monopolizes a communication bus to send information, and the communication line corresponding to the receiving channel is connected to the communication bus exclusively occupied by the receiving CPU plug-in to receive information.

As shown in Figure 3, there are 4 CPUs, and M=4, N=3. On the entire 21-slot backplane, there are 21 serial channels, that is, serial communication buses, and a total of 4 serial channels are used this time. The CPU in each slot can connect its sending channel to the corresponding serial channel. For example, the CPU in slot 1 connects the sending channel to the first serial channel, and the CPU in slot 17 connects the sending channel to the 17th serial channel. For the receiving channel, the CPU of each slot can receive other serial channels except its own slot number. For example, the CPU in the first slot can receive serial channels 2-21, and the CPU in slot 17 can receive serial channels 1-16 and 18-21. Since the CPU of each slot occupies one transmission channel exclusively, the serial bus with multiple transceiver nodes on the backplane belongs to the "full-duplex" communication mode. This further improves the real-time performance of the data. This is a simplified full-switching connection mode. The CPU in any slot can send data in real time without being affected by bus arbitration, and directly sends the data to the destination CPU.

For the CPU plug-in, there are 21 serial bus transceivers on each CPU, and according to the slot information, the CPU sets the corresponding number of transceivers to the sending mode. In addition, according to the receiving needs, set the transceivers of other corresponding numbers to receive mode. For example, CPU in slot 1 needs to communicate with CPUs in slot 3, 7, and 13 at the same time, and CPU in slot 3 also needs to communicate with CPUs in slot 1, 7, and 13. So for a 1-slot CPU. Set the No. 1 transceiver of the CPU in the No. 1 slot to the sending mode; set the No. 3, 7, and 13 transceivers to the receiving mode at the same time. Similarly, for the 3-slot CPU, set the No. 3 transceiver as the sending mode, and the No. 1, No. 7, and No. 13 transceivers as the receiving mode (receive information from the CPUs in slots 1, 7, and 13). Similarly, 7-slot CPUs and 13-slot CPUs also have similar settings.

Regarding the internal priority of the CPU: the 1-slot CPU shown in Figure 3 above receives data from the 3, 7, and 13-slot CPUs at the same time. By default, the data in slots 3, 7, and 13 have the same priority. For a CPU with slot 1, the first-in-first-out principle applies. If there are special needs, the priority can also be set. If the CPU in slot 1 receives the CPU data of slots 3 and 7 at the same time, and the priority of slot 7 is the highest, then the data of the CPU in slot 7 will be transmitted first.

The present bus architecture for multiprocessor parallel processing applications has the following advantages:

1) The increase cost of the bus in the present invention is low, and it is suitable for batch industrial applications such as direct current transmission projects.

2) It solves the throughput bottleneck between platform multi-CPU access under the standard parallel backplane bus structure. It not only solves the bus contention, but also solves the problem of fast communication between multiple CPUs. It meets the requirements of high real-time multi-task, multi-CPU parallel processing applications.

3) It has good continuity and forward compatibility in technology, which can save subsequent R&D investment. Only the CPU and backplane need to be changed locally, and other types of IO plug-ins do not need to be changed. This maximizes the return on investment.

4) The reduction of shared memory cards also contributes to cost reduction.

Finally, it should be noted that: the above embodiments are only used to illustrate and not limit the technical solutions of the present invention, although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand; the present invention can still be modified Or an equivalent replacement, any modification or partial replacement without departing from the spirit and scope of the present invention shall fall within the scope of the claims of the present invention.

Claims (4)

1. The bus architecture of multiprocessor parallel processing application is characterized in that: the bus is N sections of sub-buses arranged in parallel, each section of sub-buses is connected with at least one CPU plug-in, and N is a natural number greater than or equal to 2. 2 . The bus architecture for multiprocessor parallel processing applications according to claim 1 , wherein the N is set to 3. 3 . 3. the bus architecture of multiprocessor parallel processing application according to claim 1, is characterized in that: also be provided with the communication bus of the CPU plug-in communication of each section sub-bus, communication bus comprises M serial channels, each Each CPU plug-in is provided with at least M communication interfaces, and each communication interface of each CPU plug-in is connected to each serial channel in a one-to-one correspondence. 4. The bus architecture of multiprocessor parallel processing application according to claim 3, characterized in that: one of the communication interfaces of each CPU plug-in is a sending interface, and the other communication interfaces are receiving interfaces; the sending of each CPU plug-in The interface corresponds to each serial channel one by one.

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