CN103489399A - Electroluminescent pixel circuit - Google Patents

Abstract

The invention discloses an electroluminescent pixel circuit, which includes an organic light-emitting diode, a compensation unit and a switching transistor. The cathode terminal of the organic light emitting diode is electrically connected to the first voltage source. The compensation unit is electrically connected to the second voltage source and is used to receive the control signal, the first scanning signal and the second scanning signal. The pulse enabling periods of the first scanning signal and the second scanning signal are both within the pulse enabling period of the control signal. within, and the pulse enabling period of the first scanning signal is before the pulse enabling period of the second scanning signal. The switching transistor has a first terminal, a second terminal and a gate terminal. The two terminals of the switching transistor are electrically connected between the compensation unit and the anode terminal of the organic light emitting diode, and the switching transistor is turned on according to the control signal.

Description

El pixel circuit

Technical field

The invention relates to the technical field of organic light-emitting diode display, and particularly relevant for a kind of el pixel circuit of organic light emitting diode display.

Background technology

Please refer to Fig. 1, its schematic diagram that is traditional Organic Light Emitting Diode (Organic Light Emitting Diode, OLED) el pixel circuit.This kind of el pixel circuit 100 includes driving transistors 102, switching transistor 104, electric capacity 106 and Organic Light Emitting Diode 110.The first end of driving transistors 102 is electrically connected to voltage source OVDD.The gate terminal of switching transistor 104 receives sweep signal SCAN because of electrical connection, and the first end of switching transistor 104 receives data voltage Vdata because of electrical connection, and the second end is electrically connected to the gate terminal of driving transistors 102.The two ends of electric capacity 106 are connected across between the gate terminal and first end of driving transistors 102.The anode tap of Organic Light Emitting Diode 110 is electrically connected to the second end of driving transistors 102, and cathode terminal is electrically connected to another voltage source OVSS.Aforementioned dot structure produces pixel current I according to the first end of driving transistors 102 and the potential difference (PD) Vsg of gate terminal _oleddrive Organic Light Emitting Diode 110 shinny, the pixel current that flows through Organic Light Emitting Diode 110 is I _oled=K* (V _sg-| V _tH|) ².K is constant, V _sgsize be relevant to the size of voltage source OVDD and data voltage Vdata, the critical voltage that VTH is driving transistors 102.

Due to the impact of manufacturing process, the critical voltage VTH of the driving transistors 102 of each pixel is all not identical, causes between organic light emitting diode display interior pixels and pixel having pixel current I _oleddifference, make different its brightness produced of the electric current that flows through each Organic Light Emitting Diode OLED will be different, thereby cause the inhomogeneous problem of Display panel.

Summary of the invention

The present invention proposes a kind of el pixel circuit, includes OLED, compensating unit and switching transistor.Organic Light Emitting Diode has anode tap and cathode terminal, and the cathode terminal of Organic Light Emitting Diode is electrically connected to the first voltage source.Compensating unit is electrically connected to the second voltage source, and in order to reception control signal, the first sweep signal and the second sweep signal, wherein during the pulse activation of the first sweep signal and the second sweep signal all during the pulse activation of control signal in, and during the pulse activation of the first sweep signal before during the pulse activation of the second sweep signal.Switching transistor has first end, the second end and gate terminal, two ends of switching transistor are electrically connected between the anode tap of compensating unit and Organic Light Emitting Diode, and according to control signal actuating switch transistor, wherein the first voltage source and second voltage source are all fixed voltage, and the accurate position in contrast to the second voltage source, the position of the first voltage source is accurate.

The present invention reintroduces a kind of el pixel circuit, includes OLED, switching transistor, the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor and the first electric capacity.Wherein, Organic Light Emitting Diode has anode tap and cathode terminal, and the cathode terminal of Organic Light Emitting Diode is electrically connected to the first voltage source.Switching transistor has first end, the second end and gate terminal, and the second end of switching transistor is electrically connected to the anode tap of Organic Light Emitting Diode, and the gate terminal of switching transistor is in order to reception control signal, and according to control signal actuating switch transistor.The first transistor has first end, the second end and gate terminal, and wherein the first end of the first transistor is electrically connected to the second voltage source, and the gate terminal of the first transistor is in order to reception control signal.Transistor seconds has first end, the second end and gate terminal, and wherein the first end of transistor seconds is electrically connected to the second end of the first transistor, and the second end of transistor seconds is electrically connected to the first end of switching transistor.The 3rd transistor has first end, the second end and gate terminal, wherein the 3rd transistorized first end is in order to receive data voltage, the 3rd transistorized the second end is electrically connected to the first end of transistor seconds, and the 3rd transistorized gate terminal is in order to receive the second sweep signal.The 4th transistor has first end, the second end and gate terminal, wherein the 4th transistorized first end is electrically connected to the second end of transistor seconds, the 4th transistorized the second end is electrically connected to the gate terminal of transistor seconds, and the 4th transistorized gate terminal is in order to receive the second sweep signal.The 5th transistor has first end, the second end and gate terminal, and the 5th transistorized first end and the 5th transistorized gate terminal all are electrically connected to the second voltage source, and the 5th transistorized the second end is electrically connected to the gate terminal of transistor seconds.The first electric capacity, a wherein end of the first electric capacity is in order to receive the first sweep signal, and the other end of the first electric capacity is electrically connected to the gate terminal of transistor seconds.

The present invention proposes again a kind of el pixel circuit, and it comprises light-emitting component, switching transistor, the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor, the first electric capacity and the second electric capacity.Light-emitting component has anode tap and cathode terminal, and the cathode terminal of light-emitting component is electrically connected to the first voltage source.Switching transistor, switching transistor has first end, the second end and gate terminal, and the second end of switching transistor is electrically connected to the anode tap of light-emitting component, and the gate terminal of switching transistor is in order to reception control signal.The first transistor has first end, the second end and gate terminal, and the first end of the first transistor is electrically connected to the second voltage source, and the gate terminal of the first transistor is in order to reception control signal.Transistor seconds has first end, the second end and gate terminal, and the first end of transistor seconds is electrically connected to the second end of the first transistor, and the second end of transistor seconds is electrically connected to the first end of switching transistor.The 3rd transistor has first end, the second end and gate terminal, the 3rd transistorized first end is electrically connected to the second end of transistor seconds, the 3rd transistorized the second end is electrically connected to the gate terminal of transistor seconds, and the 3rd transistorized gate terminal is in order to receive the first sweep signal.The 4th transistor has first end, the second end and gate terminal, the 4th transistorized first end is in order to receive data voltage, the 4th transistorized the second end is electrically connected to the gate terminal of transistor seconds, and the 4th transistorized gate terminal is in order to receive the 3rd sweep signal.The 5th transistor has first end, the second end and gate terminal, the 5th transistorized first end is electrically connected to the second voltage source, the 5th transistorized the second end is electrically connected to the second end of transistor seconds, and the 5th transistorized gate terminal is in order to receive the first sweep signal.The first electric capacity is electrically connected between the first end of the gate terminal of transistor seconds and transistor seconds.The second electric capacity is electrically connected between the first end and the second sweep signal of transistor seconds.

For above and other purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and coordinate accompanying drawing, be described in detail below.

The accompanying drawing explanation

Fig. 1 is the schematic diagram of existing el pixel circuit.

Fig. 2 is the schematic diagram according to the el pixel circuit of one embodiment of the invention.

Fig. 3 is the schematic diagram according to the compensating unit inside of one embodiment of the invention.

The sequential chart that Fig. 4 is the part signal of el pixel circuit shown in Fig. 3.

Fig. 5 is the schematic diagram according to another compensating unit of the el pixel circuit inside of one embodiment of the invention.

Fig. 6 is the schematic diagram of a compensating unit again according to the el pixel circuit inside of one embodiment of the invention.

Fig. 7 is the schematic diagram according to the el pixel circuit of another embodiment of the present invention.

Fig. 8 is the schematic diagram according to the compensating unit inside of another embodiment of the present invention.

The sequential chart that Fig. 9 is the part signal of el pixel circuit shown in Fig. 8.

Figure 10 is the schematic diagram according to the el pixel circuit of one embodiment of the invention.

The sequential chart that Figure 11 is the part signal of el pixel circuit shown in Figure 10.

Figure 12 is the schematic diagram according to the el pixel circuit of another embodiment of the present invention.

Figure 13 is the schematic diagram according to the el pixel circuit of another embodiment of the present invention.

The sequential chart that Figure 14 is the part signal of el pixel circuit shown in Figure 13.

Wherein, Reference numeral:

100,200,300,500,600,700,800: el pixel circuit

102: driving transistors

104,220,720,1002,1302: switching transistor

106,316,517,617,816, C1, C2: electric capacity

110,230,730: Organic Light Emitting Diode

OVDD, OVSS, Vref: voltage source

SCAN: sweep signal

Vdata: data voltage

I _oled: pixel current

210,310,510,610,710,810: compensating unit

EM: control signal

S1: the first sweep signal

S2: the second sweep signal

S3: the 3rd sweep signal

311,811,1003,1303: the first transistor

312,812,1004,1304: transistor seconds

313,813,1005,1305: the three transistors

314,814,1006,1306: the four transistors

315,615,815,1007,1207,1307: the five transistors

A: node

V _a: the current potential of node A

T1～T5: time

1000,1200,1300: el pixel circuit

1001,1301: light-emitting component

Embodiment

Fig. 2 is the schematic diagram according to the el pixel circuit of one embodiment of the invention.El pixel circuit 200 includes compensating unit 210, switching transistor 220 and Organic Light Emitting Diode 230.Wherein, Organic Light Emitting Diode 230 has anode tap and cathode terminal, and the cathode terminal of Organic Light Emitting Diode 230 is electrically connected to voltage source OVSS.Compensating unit 210 is electrically connected to another voltage source OVDD, and because of electrical connection reception control signal EM, the first sweep signal S1 and the second sweep signal S2, wherein during the pulse activation of the first sweep signal S1 and the second sweep signal S2 all during the pulse activation of control signal EM in, and during the pulse activation of the first sweep signal S1 before during the pulse activation of the second sweep signal S2.Switching transistor 220 has first end, the second end and gate terminal, and the two ends of switching transistor 220 are electrically connected between the anode tap of compensating unit 210 and Organic Light Emitting Diode 230, and according to control signal EM actuating switch transistor 220.Above-mentioned voltage source OVSS and OVDD are all fixed voltage, and the accurate position in contrast to voltage source OVDD, the position of voltage source OVSS is accurate, and voltage source OVSS is for example-4.4 volts, and voltage source OVDD is for example+4.6 volts.

Specifically, please refer to Fig. 3, its schematic diagram that is compensating unit inside.In Fig. 3, indicate and be expressed as identical element, voltage source or signal with the identical person of sign in Fig. 2.Compensating unit 310 shown in Fig. 3 includes the first transistor 311, transistor seconds 312 (following alleged transistor seconds is driving transistors), the 3rd transistor 313, the 4th transistor 314, the 5th transistor 315 and electric capacity 316, and wherein the first transistor to the five transistors 311～315 all have first end, the second end and gate terminal.The first end of the first transistor 311 is electrically connected to voltage source OVDD, and the gate terminal of the first transistor 311 is because of electrical connection reception control signal EM.The first end of transistor seconds 312 is electrically connected to the second end of the first transistor 311, and the second end of transistor seconds 312 is electrically connected to the first end of switching transistor 220.The first end of the 3rd transistor 313 receives data voltage Vdata because of electrical connection, and the second end of the 3rd transistor 313 is electrically connected to the first end of transistor seconds 312, the gate terminal of the 3rd transistor 313 receives the second sweep signal S2 because of electrical connection.The first end of the 4th transistor 314 is electrically connected to the second end of transistor seconds 312, and the second end of the 4th transistor 314 is electrically connected to the gate terminal of transistor seconds 312, the gate terminal of the 4th transistor 314 receives the second sweep signal S2 because of electrical connection.The first end of the 5th transistor 315 and gate terminal all are electrically connected to voltage source OVDD, and the second end of the 4th transistor 314 is electrically connected to the gate terminal of transistor seconds 312.One end of electric capacity 316 receives the first sweep signal S1 because of electrical connection, and the other end of electric capacity 316 is electrically connected to the gate terminal of transistor seconds 312.

In the present embodiment, the first transistor 311, transistor seconds 312, the 3rd transistor 313, the 4th transistor 314, the 5th transistor 315 can be all the PMOS transistors with switching transistor 220.Below just take the PMOS transistor as example, narrate the first sweep signal S1, the second sweep signal S2 in Fig. 3 and the sequential of control signal EM.

The sequential chart that Fig. 4 is the part signal of el pixel circuit shown in Fig. 3.In Fig. 4, indicate and be expressed as identical signal with the identical person of sign in Fig. 3, and indicate the current potential that VA is the node A shown in Fig. 3.From Fig. 4, can learn, in during time T 1～T5, during the pulse activation of the first sweep signal S1 and the second sweep signal S2 all during the pulse activation of control signal EM in, and during the pulse activation of the first sweep signal S1 before during the pulse activation of the second sweep signal S2.Wherein, in time T 1 and time T 5, be used for cushioning the first sweep signal S1 the interval time of the rising edge of the rising edge of control signal EM and the first sweep signal S1 and be pulled up to the required time of high levels by low level, be used for cushioning the second sweep signal S2 the interval time of the rising edge of the falling edge of control signal EM and the second sweep signal S2 and be pulled up to the required time of high levels by low level, thus, can guarantee during the pulse activation of the first sweep signal S1 and the second sweep signal S2 all within during the pulse activation of control signal EM.

Although, in the present embodiment, the falling edge of the falling edge of the first sweep signal S1 and the second sweep signal S2 all has each other the relation overlapped, but in certain embodiments, the falling edge of the falling edge of the first sweep signal S1 and the second sweep signal S2 relation that also can non-ly overlap each other.That is to say, after the first sweep signal S1 is low level by the high levels transition, it is the low level state that the second sweep signal S2 just starts by the high levels transition.Therefore, whether the overlapping of the falling edge of the falling edge of the first sweep signal S1 and the second sweep signal S2, only want during the pulse activation of the first sweep signal S1 and the second sweep signal S2 all within during the pulse activation of control signal EM, the el pixel circuit normal operation can be made, all the present invention can be realized.And the above listed signal of enumerating is implemented the sample state, be only for example purposes, the present invention is not limited according to this.

Describe the driving process of el pixel circuit 300 in detail below in conjunction with Fig. 3 and Fig. 4, and the driving process of el pixel circuit 300 of the present invention mainly includes the operational phase of resetting, writes and compensating operation stage and light emission operation stage, drop on respectively during time T 2, time T 3 and time T 5.

Particularly, el pixel circuit 300 during the operational phase T2 that resets in, control signal EM, the first sweep signal S1 and the second sweep signal S2 all present the high levels state, making the 5th transistor 315 is conducting state, and the first transistor 311, transistor seconds 312, the 3rd transistor 313, the 4th transistor 314 and switching transistor 220 are all in closed condition.Now, voltage source OVDD just provides through the 5th transistor 315 of conducting the current potential V that makes node A to electric capacity 316 _afor OVDD+|V _tH|.

Then write with compensating operation stage T3 during in, the first sweep signal S1 and the second sweep signal S2 all present the low level state, control signal EM presents the high levels state, making the 3rd transistor 313 and the 4th transistor 314 is all conducting state, and the first transistor 311, the 5th transistor 315 and switching transistor 220 are all in closed condition.Now, because the current potential of node A can come highly than the current potential of the first end of transistor seconds 312, so transistor seconds 312 also can be in closed condition.And the electric charge originally be stored in electric capacity 316 can be released in time gradually, then work as the current potential V of node A _adrop to and compare Vdata-|V _tH| also during low current potential, transistor seconds 312 just can be switched on.

Now, at transistor seconds 312, the 3rd transistor 313 and the 4th transistor 314, it is all conducting state, and the first transistor 311, the 5th transistor 315 and switching transistor 220 are all when closed condition, and transistor seconds 312, the 3rd transistor 313 and the 4th transistor 314 that the value of data voltage Vdata just sees through conducting provide the current potential V that makes node A to electric capacity 316 _amaintain Vdata-|V _tH| position accurate.

In finally during light emission operation stage T5, the first sweep signal S1 and control signal EM all present the low level state, the second sweep signal S2 presents the high levels state, making the first transistor 311, transistor seconds 312 is all conducting state with switching transistor 220, and the 3rd transistor 313, the 4th transistor 314 and the 5th transistor 315 are all in closed condition.Thus, transistor seconds 312 (being driving transistors) just can be according to the potential difference (PD) V on now its first end and its gate terminal _sgproduce pixel current I _oleddrive Organic Light Emitting Diode 230 shinny.

Hold above-mentionedly, flow through the pixel current I of Organic Light Emitting Diode 230 _oled=K* (V _sg-| V _tH|) ².Now, the first end of transistor seconds 312 and the potential difference (PD) V on gate terminal _sgbe respectively the current potential Vdata-|V of voltage source OVDD and node A _tH|, be I therefore flow through the pixel current of Organic Light Emitting Diode 230 _oled=K*{[OVDD-(Vdata-|V _tH|)]-| V _tH| ²=K* (OVDD – Vdata) ².Can learn thus, during light emission operation stage T5 in, flow through the pixel current I of Organic Light Emitting Diode 230 _oledonly relevant with data voltage Vdata with voltage source OVDD, and with the critical voltage V of transistor seconds 312 (being driving transistors) _tHfully irrelevant.Thus, the processing procedure of Organic Light Emitting Diode on the impact of the critical voltage of driving transistors and the inhomogeneous problem of Display panel caused can effectively be improved, thereby make organic light emitting diode display can compensate critical voltage when display frame, and still can keep preferably display quality under long-time the use.

In addition, in certain embodiments, the compensating unit of el pixel circuit of the present invention inside also can be done a little improvement, with Fig. 5 and Fig. 6, it is described respectively.Fig. 5 is the schematic diagram according to another compensating unit of el pixel circuit of the present invention inside.In Fig. 5, indicate and be expressed as identical object, voltage source or signal with the identical person of sign in Fig. 3.The compensating unit 510 of the el pixel circuit 500 shown in Fig. 5 and the difference of the compensating unit 310 of the el pixel circuit 300 shown in Fig. 3, the compensating unit 510 that is these el pixel circuit 500 inside also comprises electric capacity 517, and it is electrically connected between second end and gate terminal of the 4th transistor 314.

Fig. 6 is according to the schematic diagram of the compensating unit of an el pixel circuit inside more of the present invention.In Fig. 6, indicate and be expressed as identical object, voltage source or signal with the identical person of sign in Fig. 3.The compensating unit 610 of the el pixel circuit 600 shown in Fig. 6 and the difference of the compensating unit 310 of the el pixel circuit 300 shown in Fig. 3, the compensating unit 610 that is these el pixel circuit 600 inside also comprises electric capacity 617, the first end of electric capacity 617 can be electrically connected to voltage source OVDD or voltage source V ref, and the second end of electric capacity 617 is electrically connected to a wherein end of electric capacity 316.In addition, first end and the gate terminal of the 5th transistor 615, the five transistors 615 of compensating unit 610 inside all can be electrically connected to voltage source V ref, and the second end of the 5th transistor 615 is electrically connected to the gate terminal of transistor seconds 312.In the present embodiment, voltage source OVSS, OVDD and Vref are all fixed voltage, and the accurate standard in contrast to voltage source OVDD in the position of voltage source OVSS, and the accurate position standard that is more than or equal to voltage source OVDD in the position of voltage source V ref.Above-mentioned voltage source OVSS is for example-4.4 volts, and voltage source OVDD is for example+4.6 volts, and voltage source V ref be for example be more than or equal to+4.6 volts.Above these two kinds of el pixel circuits 500 and 600 driving process, those skilled in the art can push away it from the described sequential content of Fig. 4, is therefore no longer repeated.

Fig. 7 is the schematic diagram according to the el pixel circuit of another embodiment of the present invention.This el pixel circuit 700 comprises compensating unit 710, switching transistor 720 and Organic Light Emitting Diode 730.Wherein, Organic Light Emitting Diode 730 has anode tap and cathode terminal, and the anode tap of Organic Light Emitting Diode 730 is electrically connected to voltage source OVDD.Compensating unit 710 is electrically connected to another voltage source OVSS, and because of electrical connection reception control signal EM, the first sweep signal S1 and the second sweep signal S2, wherein during the pulse activation of the first sweep signal S1 and the second sweep signal S2 all during the pulse activation of control signal EM in, and during the pulse activation of the first sweep signal S1 before during the pulse activation of the second sweep signal S2 (the rear detailed description in detail).Switching transistor 720 has first end, the second end and gate terminal, and the two ends of switching transistor 720 are electrically connected between the cathode terminal of compensating unit 710 and Organic Light Emitting Diode 730, and according to control signal EM actuating switch transistor 720.Above-mentioned voltage source OVDD and OVSS are all fixed voltage, and the accurate position in contrast to voltage source OVSS, the position of voltage source OVDD is accurate, and voltage source OVDD is for example+4.6 volts, and voltage source OVSS is for example-4.4 volts.

Specifically, please refer to Fig. 8, its schematic diagram that is compensating unit inside.In Fig. 8, indicate and be expressed as identical object, voltage source or signal with the identical person of sign in Fig. 7.Compensating unit 810 shown in Fig. 8 includes the first transistor 811, transistor seconds 812 (being driving transistors), the 3rd transistor 813, the 4th transistor 814, the 5th transistor 815 and electric capacity 816, and wherein the first transistor to the five transistors 811～815 all have first end, the second end and gate terminal.The first end of the first transistor 811 is electrically connected to second voltage source OVSS, and the gate terminal of the first transistor 811 is because of electrical connection reception control signal EM.The first end of transistor seconds 812 is electrically connected to the second end of the first transistor 811, and the second end of transistor seconds 812 is electrically connected to the first end of switching transistor 720.The first end of the 3rd transistor 813 receives data voltage Vdata because of electrical connection, and the second end of the 3rd transistor 813 is electrically connected to the first end of transistor seconds 812, the gate terminal of the 3rd transistor 813 receives the second sweep signal S2 because of electrical connection.The first end of the 4th transistor 814 is electrically connected to the second end of transistor seconds 812, and the second end of the 4th transistor 814 is electrically connected to the gate terminal of transistor seconds 812, the gate terminal of the 4th transistor 814 receives the second sweep signal S2 because of electrical connection.The first end of the 5th transistor 815 and gate terminal all are electrically connected to voltage source OVSS, and the second end of the 5th transistor 815 is electrically connected to the gate terminal of transistor seconds 812.One end of electric capacity 816 receives the first sweep signal S1 because of electrical connection, and the other end of electric capacity 816 is electrically connected to the gate terminal of transistor seconds 812.

In the present embodiment, the first transistor 811, transistor seconds 812, the 3rd transistor 813, the 4th transistor 814, the 5th transistor 815 all adopt nmos pass transistor to realize with switching transistor 720.Below just take nmos pass transistor as example, narrate the first sweep signal S1, the second sweep signal S2 in Fig. 8 and the sequential of control signal EM.

The sequential chart that Fig. 9 is the part signal of el pixel circuit shown in Fig. 8.In Fig. 9, indicate and be expressed as identical signal with the identical person of sign in Fig. 8, and indicate V _abe the current potential of the node A shown in Fig. 8.From Fig. 9, can learn, in during time T 1～T5, during the pulse activation of the first sweep signal S1 and the second sweep signal S2 all during the pulse activation of control signal EM in, and during the pulse activation of the first sweep signal S1 before during the pulse activation of the second sweep signal S2.Wherein, in time T 1 and time T 5, be to reduce to the required time of low level for cushioning the first sweep signal S1 by high levels the interval time of the falling edge of the falling edge of control signal EM and the first sweep signal S1, be to reduce to the required time of low level for cushioning the second sweep signal S2 by high levels the interval time of the falling edge of the rising edge of control signal EM and the second sweep signal S2, thus, can guarantee during the pulse activation of the first sweep signal S1 and the second sweep signal S2 all within during the pulse activation of control signal EM.

Although, in the present embodiment, the rising edge of the rising edge of the first sweep signal S1 and the second sweep signal S2 all has each other the relation overlapped, but in certain embodiments, the rising edge of the rising edge of the first sweep signal S1 and the second sweep signal S2 relation that also can non-ly overlap each other.That is to say, after the first sweep signal S1 is high levels by the low level transition, it is the high levels state that the second sweep signal S2 just starts by the low level transition.Therefore, whether the overlapping of the rising edge of the rising edge of the first sweep signal S1 and the second sweep signal S2, only want during the pulse activation of the first sweep signal S1 and the second sweep signal S2 all within during the pulse activation of control signal EM, the el pixel circuit normal operation can be made, all the present invention can be realized.And the above listed signal of enumerating is implemented the sample state, be only for example purposes, the present invention is not limited according to this.

Referring again to Fig. 9, this area has knows that the knowledgeable can be from the described sequential content of the el pixel circuit 300 of previous embodiment usually, and the sequential of the first sweep signal S1 illustrated according to Fig. 9, the second sweep signal S2 and control signal EM pushes away to obtain the driving process of el pixel circuit 800 of Fig. 8, therefore just no longer repeated.

Figure 10 is the schematic diagram according to the el pixel circuit of one embodiment of the invention.This el pixel circuit 1000 is mainly formed with light-emitting component 1001, switching transistor 1002, the first transistor 1003, transistor seconds 1004, the 3rd transistor 1005, the 4th transistor 1006, the 5th transistor 1007, capacitor C 1 and capacitor C 2.As shown in the figure, the cathode terminal of light-emitting component 1001 is electrically connected to voltage source OVSS.The second end of switching transistor 1002 is electrically connected to the anode tap of light-emitting component 1001, and the gate terminal of switching transistor 1002 is in order to reception control signal EM.The first end of the first transistor 1003 is electrically connected to voltage source OVDD, and the gate terminal of the first transistor 1003 is in order to reception control signal EM.The first end of transistor seconds 1004 is electrically connected to the second end of the first transistor 1003, and the second end of transistor seconds 1004 is electrically connected to the first end of switching transistor 1002.The first end of the 3rd transistor 1005 is electrically connected to the second end of transistor seconds 1004, and the second end of the 3rd transistor 1005 is electrically connected to the gate terminal of transistor seconds 1004, and the gate terminal of the 3rd transistor 1005 is in order to receive the first sweep signal S1.The first end of the 4th transistor 1006 is in order to receive data voltage Vdata, and the second end of the 4th transistor 1006 is electrically connected to the gate terminal of transistor seconds 1004, and the gate terminal of the 4th transistor 1006 is in order to receive the 3rd sweep signal S3.The first end of the 5th transistor 1007 is electrically connected to voltage source OVDD, and the second end of the 5th transistor 1007 is electrically connected to the second end of transistor seconds 1004, and the gate terminal of the 5th transistor 1007 is in order to receive the first sweep signal S1.Capacitor C 1 is electrically connected between the first end of the gate terminal of transistor seconds 1004 and transistor seconds 1004.Capacitor C 2 is electrically connected between the first end and the second sweep signal S2 of transistor seconds 1004.Above-mentioned voltage source OVDD and OVSS are all fixed voltage, and the accurate position in contrast to voltage source OVSS, the position of voltage source OVDD is accurate, and voltage source OVDD is for example+4.6 volts, and voltage source OVSS is for example-4.4 volts.In addition, the light-emitting component 1001 in this embodiment is realized with Organic Light Emitting Diode.

In the present embodiment, switching transistor 1002, the first transistor 1003, transistor seconds 1004, the 3rd transistor 1005, the 4th transistor 1006 and the 5th transistor 1007 all adopt the PMOS transistor to realize.Below just take the PMOS transistor as example, narrate the sequential of the first sweep signal S1, the second sweep signal S2, the 3rd sweep signal S3 and control signal EM in Figure 10.

The sequential chart that Figure 11 is the part signal of el pixel circuit shown in Figure 10.As shown in the figure, during time T 1～T4 is expressed as respectively the replacement of el pixel circuit, between the amortization period, between data during writing and light emission period.The first sweep signal S1 during resetting (being time T1) and between the amortization period (being time T2) be positioned at first standard, the first sweep signal S1 (being time T4) between data during writing (being time T3) and light emission period is positioned at the second standard.The second sweep signal S2 (being time T1) during resetting is positioned at first standard, the second sweep signal S2 between the amortization period during (being time T2) initial by first accurate transition to the second standard.The 3rd sweep signal S3 during resetting between (being time T1), amortization period between (being time T2) and light emission period (being time T4) be positioned at the second standard, the 3rd sweep signal S3 is positioned at first standard in data during writing (being time T3).Control signal EM is positioned at the second standard when (being time T2) and data during writing (being time T3) during resetting between (being time T1), amortization period, control signal EM is positioned at first standard when (being time T4) between light emission period.In this embodiment, described first standard is logic low level state, and described second criterion is the accurate state of logic high.

Specifically, during el pixel circuit 1000 is being reset when (being time T1), the first sweep signal S1 and the second sweep signal S2 all present logic low level state, and the 3rd sweep signal S3 and control signal EM all present the accurate state of logic high, make switching transistor 1002, the first transistor 1003, transistor seconds 1004 and the 4th transistor 1006 all in closed condition, and the 3rd transistor 1005 and the 5th transistor 1007 are all in opening.Now, the 5th transistor 1007 that voltage source OVDD just sees through conducting and the 3rd transistor 1005 of conducting provide the current potential that makes node A to capacitor C 1 DVDD approximately slightly.

Then, when el pixel circuit 1000 between the amortization period when (being time T2), the first sweep signal S1 presents logic low level state, and the second sweep signal S2, the 3rd sweep signal S3 and control signal EM all present the accurate state of logic high, make switching transistor 1002, the first transistor 1003 and the 4th transistor 1006 all in closed condition, and transistor seconds 1004, the 3rd transistor 1005 and the 5th transistor 1007 are all in opening.Now, the current potential of node A is DVDD approximately slightly, and the current potential of the first end of transistor seconds 1004 DVDD+|V approximately slightly _tH|, therefore in the situation that the current potential of node A comes lowly compared to the current potential of the first end of transistor seconds 1004, transistor seconds 1004 is in opening.When el pixel circuit 1000 when data during writing (being time T3), the first sweep signal S1, the second sweep signal S2 and control signal EM all present the accurate state of logic high, the 3rd sweep signal S3 presents logic low level state, make switching transistor 1002, the first transistor 1003, the 3rd transistor 1005 and the 5th transistor 1007 all in closed condition, and transistor seconds 1004 and the 4th transistor 1006 are all in opening.Now, the current potential of the node A data voltage Vdata that approximately slightly the first end of the 4th transistor 1006 receives, the current potential of the first end of transistor seconds 1004 is rough DVDD+|V _tH|+α (Vdata-DVDD).Wherein, α is the ratio between two capacitor C 1 and C2, is

$\mathrm{\&alpha;}=\frac{C1}{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="HDA00003626314900012.png,HDA00003626314900031.png"\; state="\{\{state\}\}">C</figure-callout>}1+\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="HDA00003626314900021.png,HDA00003626314900051.png"\; state="\{\{state\}\}">C</figure-callout>}2}$

Finally, when el pixel circuit 1000 between light emission period when (being time T4), the first sweep signal S1, the second sweep signal S2 and the 3rd sweep signal S3 all present the accurate state of logic high, control signal EM presents logic low level state, make switching transistor 1002, the first transistor 1003 and transistor seconds 1004 all in opening, and the 3rd transistor 1005, the 4th transistor 1006 and the 5th transistor 1007 are all in closed condition.Now, the current potential of the first end of transistor seconds 1004 is OVDD approximately slightly, and the current potential of node A is Vdata-|V approximately slightly _tH|+α (DVDD-Vdata).So, transistor seconds 1004 just can produce pixel current I according to the potential difference (PD) on its first end and its gate terminal _oleddrive light-emitting component 1001 shinny.

Hold above-mentionedly, flow through the pixel current I of light-emitting component 1001 _oled=1/2*K* (V _sg-| V _tH|) ².Now, the first end of transistor seconds 1004 and the potential difference (PD) V on gate terminal _sgbe respectively the current potential Vdata-|V of voltage source OVDD and node A _tH|+α (DVDD-Vdata) is I therefore flow through the pixel current of light-emitting component 1001 _oled=1/2*K*{OVDD-[Vdata-|V _tH|+α (DVDD-Vdata)]-| V _tH| ²=1/2*K*[(1-α) * (OVDD – Vdata)] ².Can learn thus, flow through the pixel current I of light-emitting component 1001 _oledonly relevant with data voltage Vdata with voltage source OVDD, and with the critical voltage V of transistor seconds 1004 (being driving transistors) _tHirrelevant.Thus, the processing procedure of described light-emitting component on the impact of the critical voltage of driving transistors and the inhomogeneous problem of Display panel caused can effectively be improved, thereby make the electroluminescence display pixel of this embodiment can compensate critical voltage when display frame, and still can keep preferably display quality under long-time the use.

In addition, in certain embodiments, above-mentioned electroluminescence display pixel also can be made a little improvement, with Figure 12, it is described.Figure 12 is the schematic diagram according to the el pixel circuit of another embodiment of the present invention.In Figure 12, indicate and be expressed as identical element, voltage source or signal with the identical person of sign in Figure 10.The difference of the electroluminescence display pixel 1000 shown in the electroluminescence display pixel 1200 shown in Figure 12 and Figure 10, the first end that is the 5th transistor 1207 in electroluminescence display pixel 1200 is electrically connected to voltage source OVDD, and the second end of the 5th transistor 1207 is electrically connected to the first end of the 3rd transistor 1005.As for the detailed driving process of this kind of electroluminescence display pixel 1200, those of ordinary skill in the art can push away it from the described sequential content of Figure 11, therefore repeats no more.

Figure 13 is the schematic diagram according to the el pixel circuit of another embodiment of the present invention.The difference of the electroluminescence display pixel 1000 shown in the el pixel circuit 1300 shown in Figure 13 and Figure 10, be that el pixel circuit 1300 is mainly formed with light-emitting component 1301, switching transistor 1302, the first transistor 1303, transistor seconds 1304, the 3rd transistor 1305, the 4th transistor 1306 and the 5th transistor 1307.Wherein, these transistors all adopt nmos pass transistor to realize.As shown in the figure, the anode tap of light-emitting component 1301 is electrically connected to voltage source OVDD.The first end of switching transistor 1302 is electrically connected to the cathode terminal of light-emitting component 1301, and the gate terminal of switching transistor 1302 is in order to reception control signal EM.The second end of the first transistor 1303 is electrically connected to voltage source OVSS, and the gate terminal of the first transistor 1303 is in order to reception control signal EM.The first end of transistor seconds 1304 is electrically connected to the second end of switching transistor 1302, and the second end of transistor seconds 1304 is electrically connected to the first end of the first transistor 1303.The first end of the 3rd transistor 1305 is electrically connected to the second end of transistor seconds 1304, the second end of the 3rd transistor 1305 is electrically connected to the gate terminal of transistor seconds 1304, and the gate terminal of the 3rd transistor 1305 is in order to receive the first sweep signal S1.The first end of the 4th transistor 1306 is in order to receive data voltage Vdata, and the second end of the 4th transistor 1306 is electrically connected to the gate terminal of transistor seconds 1304, and the gate terminal of the 4th transistor 1306 is in order to receive the 3rd sweep signal S3.The first end of the 5th transistor 1307 is electrically connected to voltage source OVSS, and the second end of the 5th transistor 1307 is electrically connected to the second end of transistor seconds 1004, and the gate terminal of the 5th transistor 1307 is in order to receive the first sweep signal S1.Capacitor C 1 is electrically connected between the first end of the gate terminal of transistor seconds 1304 and transistor seconds 1304.Capacitor C 2 is electrically connected between the first end and the second sweep signal S2 of transistor seconds 1304.Above-mentioned voltage source OVDD and OVSS are all fixed voltage, and the accurate position in contrast to voltage source OVSS, the position of voltage source OVDD is accurate, and voltage source OVDD is for example+4.6 volts, and voltage source OVSS is for example-4.4 volts.In addition, the light-emitting component 1301 in this embodiment is realized with Organic Light Emitting Diode.

The sequential chart that Figure 14 is the part signal of el pixel circuit shown in Figure 13.As shown in the figure, during time T 1～T4 is expressed as respectively the replacement of el pixel circuit, between the amortization period, between data during writing and light emission period.The first sweep signal S1 during resetting (being time T1) and between the amortization period (being time T2) be positioned at first standard, the first sweep signal S1 (being time T4) between data during writing (being time T3) and light emission period is positioned at the second standard.The second sweep signal S2 (being time T1) during resetting is positioned at first standard, the second sweep signal S2 between the amortization period during (being time T2) initial by first accurate transition to the second standard.The 3rd sweep signal S3 during resetting between (being time T1), amortization period between (being time T2) and light emission period (being time T4) be positioned at the second standard, the 3rd sweep signal S3 is positioned at first standard in data during writing (being time T3).Control signal EM is positioned at the second standard when (being time T2) and data during writing (being time T3) during resetting between (being time T1), amortization period, control signal EM is positioned at first standard when (being time T4) between light emission period.In this embodiment, described first standard is the accurate state of logic high, and described second criterion is logic low level state.As for the detailed driving process of this kind of electroluminescence display pixel 1300, those skilled in the art can push away it from the described sequential content of Figure 11, therefore repeats no more.

In sum, the present invention solves the major way of foregoing problems, be by the el pixel circuit structure is designed, can make and flow through Organic Light Emitting Diode or the size of the pixel current of light-emitting component is relevant to voltage source and data voltage, and fully irrelevant with the critical voltage of driving transistors.Therefore, the el pixel circuit that the embodiment of the present invention proposes can effectively improve the inhomogeneous problem of Display panel, so that high-quality display frame to be provided, and then reaches purpose of the present invention.

Although the present invention with preferred embodiment openly as above; but it is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when doing a little change and modification, so protection scope of the present invention is as the criterion when looking accompanying claims protection domain person of defining.

Claims (12)

1. An electroluminescent pixel circuit, characterized in that, comprising: An organic light emitting diode has an anode end and a cathode end, and the cathode end of the organic light emitting diode is electrically connected to a first voltage source; A compensation unit, electrically connected to a second voltage source, and used to receive a control signal, a first scan signal and a second scan signal, the pulse enabling periods of the first scan signal and the second scan signal are both within the pulse-enabled period of the control signal, and the pulse-enabled period of the first scan signal is before the pulse-enabled period of the second scan signal; and A switch transistor, the switch transistor has a first terminal, a second terminal and a gate terminal, the two terminals of the switch transistor are electrically connected between the compensation unit and the anode terminal of the organic light emitting diode, and according to the The control signal turns on the switch transistor, wherein both the first voltage source and the second voltage source are fixed voltages, and the level of the first voltage source is opposite to that of the second voltage source. 2. The electroluminescence pixel circuit according to claim 1, wherein the compensation unit comprises: A first transistor, the first transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the first transistor is electrically connected to the second voltage source, and the first transistor of the first transistor The gate terminal is used to receive the control signal; A second transistor, the second transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the second transistor is electrically connected to the second terminal of the first transistor, the second the second end of the transistor is electrically connected to the first end of the switching transistor; A third transistor, the third transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the third transistor is used to receive a data voltage, the second terminal of the third transistor is electrically Sexually connected to the first end of the second transistor, and the gate end of the third transistor is used to receive the second scan signal; A fourth transistor, the fourth transistor has a first end, a second end and a gate end, the first end of the fourth transistor is electrically connected to the second end of the second transistor, the fourth The second terminal of the transistor is electrically connected to the gate terminal of the second transistor, and the gate terminal of the fourth transistor is used for receiving the second scan signal; A fifth transistor, the fifth transistor has a first terminal, a second terminal and a gate terminal, both the first terminal and the gate terminal of the fifth transistor are electrically connected to the second voltage source, the first the second terminal of five transistors is electrically connected to the gate terminal of the second transistor; and A first capacitor, one end of the first capacitor is used to receive the first scan signal, and the other end is electrically connected to the gate end of the second transistor. 3. The electroluminescence pixel circuit according to claim 2, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the switch transistor are all the same type. 4. The electroluminescence pixel circuit according to claim 2, wherein the compensation unit further comprises a second capacitor, the second capacitor is electrically connected to the second terminal and the gate terminal of the fourth transistor between. 5. The electroluminescence pixel circuit according to claim 1, wherein during a first period, the control signal, the first scan signal and the second scan signal have a first level, During a second stage period, the first scan signal and the second scan signal have a second level, while the control signal has the first level, and during a third stage period, the first scan signal The second scan signal has the second level, while the control signal has the first level, and the polarity of the first level is opposite to that of the second level. 6. The electroluminescence pixel circuit according to claim 1, wherein the compensation unit comprises: A first transistor, the first transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the first transistor is electrically connected to the second voltage source, and the first transistor of the first transistor The gate terminal is used to receive the control signal; A second transistor, the second transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the second transistor is electrically connected to the second terminal of the first transistor, the second the second end of the transistor is electrically connected to the first end of the switching transistor; A third transistor, the third transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the third transistor is used to receive a data voltage, the second terminal of the third transistor is electrically Sexually connected to the first end of the second transistor, and the gate end of the third transistor is used to receive the second scan signal; A fourth transistor, the fourth transistor has a first end, a second end and a gate end, the first end of the fourth transistor is electrically connected to the second end of the second transistor, the fourth The second terminal of the transistor is electrically connected to the gate terminal of the second transistor, and the gate terminal of the fourth transistor is used for receiving the second scan signal; A fifth transistor, the fifth transistor has a first terminal, a second terminal and a gate terminal, both the first terminal and the gate terminal of the fifth transistor are electrically connected to a third voltage source, the first The second terminal of the fifth transistor is electrically connected to the gate terminal of the second transistor, wherein the third voltage source is a fixed voltage, and the level of the third voltage source is greater than or equal to the level of the second voltage source; a first capacitor, one end of the first capacitor is used to receive the first scan signal, and the other end of the first capacitor is electrically connected to the gate end of the second transistor; and A second capacitor is electrically connected between the second voltage source or the third voltage source and the first capacitor. 7. An electroluminescent pixel circuit, characterized in that it comprises: An organic light emitting diode has an anode end and a cathode end, and the cathode end of the organic light emitting diode is electrically connected to a first voltage source; A switch transistor, the switch transistor has a first terminal, a second terminal and a gate terminal, the second terminal of the switch transistor is electrically connected to the anode terminal of the organic light emitting diode, the gate terminal of the switch transistor is used for receiving a control signal, and turning on the switching transistor according to the control signal; A first transistor, the first transistor has a first terminal, a second terminal and a gate terminal, wherein the first terminal of the first transistor is electrically connected to a second voltage source, and the first transistor of the first transistor The gate terminal is used to receive the control signal; A second transistor, the second transistor has a first terminal, a second terminal and a gate terminal, wherein the first terminal of the second transistor is electrically connected to the second terminal of the first transistor, the first terminal the second terminal of the second transistor is electrically connected to the first terminal of the switching transistor; A third transistor, the third transistor has a first terminal, a second terminal and a gate terminal, wherein the first terminal of the third transistor is used to receive a data voltage, the second terminal of the third transistor electrically connected to the first terminal of the second transistor, and the gate terminal of the third transistor is used to receive a second scan signal; A fourth transistor, the fourth transistor has a first terminal, a second terminal and a gate terminal, wherein the first terminal of the fourth transistor is electrically connected to the second terminal of the second transistor, the first terminal The second terminal of the four transistors is electrically connected to the gate terminal of the second transistor, and the gate terminal of the fourth transistor is used for receiving the second scan signal; A fifth transistor, the fifth transistor has a first end, a second end and a gate end, the first end of the fifth transistor and the gate end of the fifth transistor are electrically connected to the second a voltage source, the second terminal of the fifth transistor is electrically connected to the gate terminal of the second transistor; and A first capacitor, one end of the first capacitor is used to receive a first scan signal, and the other end of the first capacitor is electrically connected to the gate end of the second transistor. 8. The electroluminescence pixel circuit as claimed in claim 7, further comprising a second capacitor electrically connected between the second terminal of the fourth transistor and the gate terminal. 9. An electroluminescent pixel circuit, characterized in that it comprises: A light-emitting element has an anode end and a cathode end, and the cathode end of the light-emitting element is electrically connected to a first voltage source; A switch transistor, the switch transistor has a first terminal, a second terminal and a gate terminal, the second terminal of the switch transistor is electrically connected to the anode terminal of the light emitting element, and the gate terminal of the switch transistor is used to receive a control signal; A first transistor, the first transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the first transistor is electrically connected to a second voltage source, and the first transistor of the first transistor The gate terminal is used to receive the control signal; A second transistor, the second transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the second transistor is electrically connected to the second terminal of the first transistor, and the first The second end of the second transistor is electrically connected to the first end of the switch transistor; A third transistor, the third transistor has a first end, a second end and a gate end, the first end of the third transistor is electrically connected to the second end of the second transistor, the third The second terminal of the transistor is electrically connected to the gate terminal of the second transistor, and the gate terminal of the third transistor is used to receive a first scan signal; A fourth transistor, the fourth transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the fourth transistor is used to receive a data voltage, the second terminal of the fourth transistor is electrically Sexually connected to the gate terminal of the second transistor, and the gate terminal of the fourth transistor is used to receive a third scan signal; A fifth transistor, the fifth transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the fifth transistor is electrically connected to the second voltage source, the first terminal of the fifth transistor two terminals are electrically connected to the second terminal of the second transistor, and the gate terminal of the fifth transistor is used for receiving the first scan signal; a first capacitor electrically connected between the gate terminal of the second transistor and the first terminal of the second transistor; and A second capacitor electrically connected between the first end of the second transistor and a second scan signal. 10. The electroluminescence pixel circuit according to claim 9, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the switching transistor are all of the same type transistor. 11. The electroluminescent pixel circuit according to claim 9, wherein the first voltage source and the second voltage source are both fixed voltages, and the level of the first voltage source is opposite to the second voltage source level. 12. The electroluminescent pixel circuit according to claim 9, further comprising a reset period, a compensation period, a data writing period, and a light emitting period, wherein the first scan signal is The setting period and the compensation period are at a first level, and the first scan signal is at a second level during the data writing period and the light emitting period; the second scan signal is at the first level during the reset period, and the second scan signal transitions from the first level to the second level at the beginning of the compensation period; the third scan signal is at the second level during the reset period, the compensation period and the light emitting period, and the third scan signal is at the first level during the data writing period; and The control signal is at the second level during the reset period, the compensation period and the data writing period, and the control signal is at the first level during the light emitting period.

Images