CN103487662B - Capacitive detection circuit - Google Patents

Abstract

The invention relates to a detection circuit and discloses a capacitance detection circuit. The capacitance detection circuit includes an integrating capacitor Ci, a capacitor to be detected Cs, a current source A, an operational amplifier A0 and an information processing chip; one end of the capacitor to be detected Cs, the integrating capacitor Ci and the current source A is respectively connected to the negative input terminal of the operational amplifier A0 The other end of the capacitor Cs to be detected is connected to the current source A, the other end of the integrating capacitor Ci is connected to the output terminal of the operational amplifier A0, and the positive input terminal of the operational amplifier A0 is grounded. After the circuit is connected, the capacitor Cs to be detected Part of the charge will be transferred through a current source A, and the other part of the charge will be transferred to the integral capacitor Ci, so that the voltage change at the output terminal of the operational amplifier A0 during a charge transfer process can be reduced without additionally increasing the area of the integral capacitor Ci. The size of △Vout, and then increase the detection range of capacitance value, because the detection voltage is not reduced during the detection process, it will not cause a decrease in signal-to-noise ratio.

Description

Capacitance detection circuit

technical field

The invention relates to the field of electronics, in particular to a capacitance detection circuit.

Background technique

At present, the rapid development of capacitive touch technology has brought great convenience to people's life. This technology first divides the touch detection area into a number of grid points that intersect horizontally and vertically, and then detects the change of the capacitance value of the grid points to obtain the touch point location information.

If the capacitive touch technology is classified according to the specific implementation, it includes capacitive buttons, self-inductance capacitive screens, and mutual-inductance capacitive screens. Among them, in capacitive buttons and self-inductance capacitive screens, the capacitance to be measured can vary widely. In some small touch circuit boards, the self-inductance capacitance is only a few picofarads, while in some large capacitive touch screens, or large capacitance In the button, its self-inductance capacitance value may reach hundreds of picofarads.

The detection principle of the traditional detection method is: when the integration starts, in the first stage, as shown in Figure 1, the integration capacitor Ci is reset to zero, and the capacitor Cs to be detected is charged to the reference voltage Vref. This stage can be called It is the sampling stage. In the second stage, the upper end of Cs is connected with the negative input end of operational amplifier A0 through a switch, as shown in Fig. 2 . Assuming that the operational amplifier is ideal, at the end of the second stage, the voltage at the input terminal of the operational amplifier is equal; at this time, the potential at both ends of the sampling capacitor Cs is zero, that is, all the charges on the capacitor Cs to be detected are transferred to the integrating capacitor Ci, This phase is called the charge transfer phase or the integration phase. These two stages together are called a charge transfer cycle or an integration cycle. In actual use, repeated charge transfers will be performed as needed, that is, to achieve integration. It is worth noting that the reset of the integration capacitor Ci is only Beginning of the first integration cycle occurs. According to the principle of charge conservation, it can be concluded that after each charge transfer, the change of the output voltage of the operational amplifier is:

$\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; r</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; \&Delta;</span>}\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; \&DoubleRightArrow;</span>\mathrm{<span\; class="notranslate">\; \&Delta;</span>}\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; r</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; f</span>}\frac{\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; i</span>}}$

Among them, ΔVout is the variation of the output voltage of the operational amplifier caused by a charge transfer. The magnitude of the voltage is detected by an analog-to-digital converter and sent to a digital circuit for processing, so that the capacitance value of the capacitor Cs to be detected can be determined.

However, in practical applications, in order to improve the anti-interference ability, Vref should be as high as possible. For the sake of description, it is assumed that the power supply of the capacitance detection circuit is 3.3V, and Vref is also 3.3V. This is very common in conventional applications. Suppose The capacitance to be detected is 100 picofarads, and the integrating capacitance is 20 picofarads, so the output voltage change of the operational amplifier caused by each transfer cycle is 16.5V, which seriously exceeds the power supply voltage value of 3.3V. If the output voltage change caused by each transfer is reduced by increasing the integral capacitor, an integral capacitor of more than 100 picofarads is required to ensure that a transfer will not exceed the tolerance range of the operational amplifier. However, the capacitance of 100 picofarads is achieved in A large area is required in an integrated circuit. Even the area of a 20 picofarad capacitor is quite considerable, and if the problem of too much output voltage variation is solved by increasing the integral capacitor, the circuit is applied to the case where the external capacitor Cs to be detected is small, and each transfer The change in the output voltage of the op amp will be very small, which will reduce the signal-to-noise ratio of the output of the op amp.

It can be seen that, using the traditional capacitance detection technology, the range of the capacitance value to be detected will be limited to a range of approximately 3 picofarads to 30 picofarads.

Contents of the invention

The object of the present invention is to provide a capacitance detection circuit. By adding an additional current source in the circuit, the capacitance detection circuit can detect the capacitance to be detected even when it is very large.

In order to solve the above technical problems, the present invention provides a capacitance detection circuit, which includes an integrating capacitance, a capacitance to be detected, a current source, an operational amplifier and an information processing chip;

One end of the capacitance to be detected is connected to the negative input end of the operational amplifier, and the other end is grounded;

One end of the integrating capacitor is connected to the negative input end of the operational amplifier, and the other end is connected to the output end of the operational amplifier;

One end of the current source is connected to the negative input end of the operational amplifier, and the other end is grounded;

The positive input terminal of the operational amplifier is grounded;

One end of the signal processing chip is connected to the output end of the operational amplifier, and the other end outputs the capacitance value detected by the capacitance detection circuit.

Compared with the prior art, the capacitance detection circuit in the present invention adds a current source, which can absorb or pour part of the charge on Cs, and another part of the charge on Cs is transferred to Ci, so that it can be Decrease △Vout without additionally increasing the area of the integrating capacitor Ci, thereby increasing the range of detected capacitance values. And the detection voltage is not lowered during the detection process, so the signal-to-noise ratio will not be reduced.

Preferably, the current source in the present invention can reasonably set the current size and turn-on time of the current source according to the application during the charge transfer process, so that ΔVout is always kept within the tolerance range of the operational amplifier A0, and further accurately detects wide range of capacitance values.

In addition, the present invention uses the following formula to calculate the capacitance value of the capacitor to be detected according to the charge transfer theory:

Vref*Cs=ΔVout*Ci+I*T

Wherein, the ΔVout is the magnitude of the voltage change at the output terminal of the operational amplifier after a charge transfer, the Vref is the reference voltage to which the capacitor to be detected is charged in the sampling phase, and the Cs is the voltage to be detected The capacitance value of the capacitor, the Ci is the capacitance value of the integrating capacitor, the I is the current value of the current source, and the T is the opening time of the current source.

Since ΔVout, Vref, Ci, I, and T in the above formula are all known numbers, the capacitance value of the capacitor Cs to be detected can be easily calculated.

Further, the capacitance detection circuit in the present invention has two working modes, one is the reverse integration mode in which Cs feeds charge to Ci, and the other is the forward integration mode in which Cs absorbs charge from Ci, and the scope of application is wider.

In addition, the signal processing chip in the capacitance detection circuit in the present invention also includes an analog-to-digital converter and a digital circuit processor, and the analog-to-digital converter performs analog-to-digital conversion on the output terminal voltage of the operational amplifier to obtain a digital signal of the output terminal voltage , and send the digital signal to the digital circuit processor, and the digital circuit processor calculates the capacitance value of the capacitor to be detected according to the formula Vref*Cs=ΔVout*Ci+I*T.

Description of drawings

FIG. 1 is a schematic diagram of a sampling stage according to a capacitance detection circuit in the prior art;

2 is a schematic diagram of a charge transfer stage according to a capacitance detection circuit in the prior art;

3 is a schematic diagram of a sampling stage of a capacitance detection circuit according to a first embodiment of the present invention;

4 is a schematic diagram of a capacitance detection circuit according to a first embodiment of the present invention;

FIG. 5 is a schematic diagram of a capacitance detection circuit in a forward integration mode according to a second embodiment of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, various embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that, in each implementation manner of the present invention, many technical details are provided for readers to better understand the present application. However, even without these technical details and various changes and modifications based on the following implementation modes, the technical solution claimed in each claim of the present application can be realized.

A first embodiment of the present invention relates to a capacitance detection circuit. Specifically shown in Figure 3 and Figure 4.

The capacitance detection circuit includes an integrating capacitor Ci, a capacitor to be detected Cs, a current source A, an operational amplifier A0 and an information processing chip;

One end of the capacitor Cs to be detected is connected to the negative input end of the operational amplifier A0, and the other end is grounded;

One end of the integrating capacitor Ci is connected to the negative input terminal of the operational amplifier A0, and the other end is connected to the output terminal of the operational amplifier A0;

One end of the current source A is connected to the negative input end of the operational amplifier A0, and the other end is grounded;

The positive input terminal of the operational amplifier A0 is grounded;

One end of the signal processing chip is connected to the output end of the operational amplifier A0, and the other end outputs the capacitance value detected by the capacitance detection circuit.

Specifically, the detection process of the capacitance in this embodiment is divided into two stages:

In the first stage, as shown in Figure 3, the integrating capacitor Ci is reset, and the capacitor Cs to be detected is charged to the reference voltage Vref, which is consistent with the traditional method;

In the second stage, as shown in Figure 4, one end of the capacitor Cs to be detected, the integrating capacitor Ci, and the current source A are respectively connected to the negative input terminal of the operational amplifier A0 through a switch, and the capacitor Cs to be detected and the other end of the current source A are connected to each other. One end is grounded, and the other end of the integrating capacitor Ci is connected to the output terminal of the operational amplifier A0, and the positive input terminal of the operational amplifier A0 is grounded, so that after the circuit is turned on, a part of the charge on the capacitor Cs to be detected will pass through a current source A Transfer, another part of the charge is transferred to the integral capacitor Ci, this stage is called the charge transfer stage or integration stage.

Assuming that the operational amplifier A0 is ideal, at the end of the second stage, the voltage at the input terminal of the operational amplifier A0 is equal, at this time, the potential at both ends of the capacitor Cs to be detected is zero, that is, the charges on the capacitor Cs to be detected are all transferred to the integration capacitor On Ci and current source A;

The charge transfer of the two parts in the above-mentioned second stage causes the voltage Vout of the output terminal of the operational amplifier A0 to change, which is amplified by the operational amplifier A0 and then output, and is received by the analog-to-digital converter in the information processing chip during the charge transfer process. The magnitude of the voltage change ΔVout, after analog-to-digital conversion, is sent to the digital circuit processor in the information processing chip for processing. The digital circuit processor is then based on the charge transfer theory, which is convenient by the expression Vref*Cs=ΔVout*Ci+I*T Obtain the capacitance value of the capacitor Cs to be tested.

The above-mentioned first stage and the second stage are collectively called a charge transfer cycle or an integration cycle. In actual use, repeated charge transfers are performed as required, that is, integration is realized. It is worth noting that the clearing of the integration capacitor Ci Zero occurs only at the first integration cycle at the beginning of integration.

Since a current source A is added to the capacitance detection circuit in this embodiment, the current source A can absorb or feed part of the charge on the capacitor Cs to be detected, and another part of the charge on the capacitor Cs to be detected is transferred to the integrating capacitor Ci , so that the size △Vout of the voltage change at the output terminal of the operational amplifier A0 during a charge transfer process can be reduced without additionally increasing the area of the integrating capacitor Ci, thereby increasing the capacitance value range of the capacitor Cs to be detected, and during the detection process The detection voltage is not reduced, so it will not cause a decrease in the signal-to-noise ratio.

For the convenience of description, here it is assumed that the current of the current source A is I, and the time when the current source is turned on is T. According to the charge transfer theory, the following expression is obtained:

$\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; r</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; \&Delta;</span>}\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; I</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; \&DoubleRightArrow;</span>\mathrm{<span\; class="notranslate">\; \&Delta;</span>}\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; r</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; I</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; T</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; i</span>}}$

In the expression, ΔVout represents the magnitude of the output voltage change of the operational amplifier A0 during a charge transfer process. Assuming that the capacitance Cs to be detected is 100pf, the integrating capacitance Ci is 20pf, the reference voltage Vref is 3.3V, the current value I of the current source A is 150uA, and the turn-on time T of the current source A is 2us, then we can get:

$\mathrm{<span\; class="notranslate">\; \&Delta;</span>}\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 3.3</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; 100</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; 150</span>}}{\mathrm{<span\; class="notranslate">\; 20</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1.5</span>}$

This is a reasonable voltage value. On the other hand, if the capacitance Cs to be detected is small, we can appropriately reduce the current value I of the current source A or the turn-on time T, so that △Vout is always kept within the tolerance range of the operational amplifier A0, and further accurately detect the large-scale capacitance value.

In the actual capacitance measurement process, since ΔVout, Vref, Ci, I, and T in the above formula are all known numbers, the capacitance value of the capacitance Cs to be detected can be easily calculated.

The second embodiment of the present invention relates to a capacitance detection circuit, as shown in FIG. 5 . The second embodiment is roughly the same as the first embodiment, the main difference is that: in the first embodiment, the capacitor Cs to be detected is to fill the charge to the integration capacitor Ci, which is called the reverse integration mode; and in the present invention In the second embodiment, the capacitor Cs to be detected absorbs charge from the integrating capacitor Ci, which is called the forward integrating mode. That is to say, in this embodiment, part of the charge on the integrating capacitor Ci is poured into the capacitor Cs to be tested, and the other part of the charge is shared by the current source A. Its working principle is the same as that of the first embodiment, and will not be repeated here.

Those of ordinary skill in the art can understand that the above-mentioned embodiments are specific examples for realizing the present invention, and in practical applications, various changes can be made to it in form and details without departing from the spirit and spirit of the present invention. scope.

Claims (5)

1. a capacitance detection circuit, is characterized in that, comprises integrating electric capacity Ci, electric capacity Cs to be detected, current source A, operational amplifier A0 and signal processing chip; One end of the capacitance Cs to be detected is connected to the negative input end of the operational amplifier A0, and the other end is grounded; One end of the integrating capacitor Ci is connected to the negative input end of the operational amplifier A0, and the other end is connected to the output end of the operational amplifier A0; One end of the current source A is connected to the negative input end of the operational amplifier A0, and the other end is grounded; The positive input terminal of the operational amplifier A0 is grounded; One end of the signal processing chip is connected to the output end of the operational amplifier A0, and the other end outputs the detected capacitance value of the capacitor Cs to be detected. 2. The capacitance detection circuit according to claim 1, wherein the current magnitude and turn-on time of the current source A can be adjusted in real time. 3. according to the capacitance detection circuit described in claim 1, it is characterized in that, described information processing chip calculates the capacitance value of described to-be-detected capacitance Cs according to following formula: Vref*Cs=ΔVout*Ci-I*T Wherein, the ΔVout is the output terminal voltage of the operational amplifier A0 after a charge transfer, the Vref is the reference voltage charged to the capacitor to be detected in the sampling phase, and the Cs is the voltage of the capacitor to be detected Capacitance value, the Ci is the capacitance value of the integrating capacitor, the I is the current value of the current source A, and the T is the time when the current source A is turned on. 4. The capacitance detection circuit according to claim 1 or 3, characterized in that, the capacitance detection circuit has two modes of operation, one is that the capacitance Cs to be detected is fed to the integration capacitance Ci with the opposite mode of charging. The forward integration mode, and the other is the positive integration mode in which the capacitor Cs to be detected absorbs charge from the integration capacitor Ci. 5. capacitance detection circuit according to claim 1, is characterized in that, described signal processing chip comprises analog-to-digital converter and digital circuit processor; One end of the analog-to-digital converter is connected to the output end of the operational amplifier, and the other end is connected to the input end of the digital circuit processor, and the analog-to-digital converter performs analog-to-digital conversion on the voltage output by the operational amplifier After that, output to the digital circuit processor; The digital circuit processor is used for calculating the capacitance value of the capacitor Cs to be detected according to the digital signal converted by the analog-to-digital converter.