CN103487602A - Anatomy of an integrated circuit chip - Google Patents

Abstract

The invention relates to an anatomical method for an integrated circuit chip, comprising: providing an integrated circuit chip, the integrated circuit chip includes a package layer and a wiring structure stacked in sequence, and the wiring structure includes at least one low-permittivity line-to-line dielectric Wiring layer, the at least one dielectric wiring layer between low dielectric constant lines has a target low dielectric constant dielectric wiring layer between lines; using chemical mechanical polishing method, under the pressure of greater than or equal to 3psi and less than or equal to 8psi, to greater than or equal to 8psi Polishing the integrated circuit chip at a line speed equal to 60 m/min and less than or equal to 240 m/min, removing the encapsulation layer around the edge of the integrated circuit chip to expose the wiring structure; and continuing to use the chemical mechanical polishing method, in Under a downward pressure greater than or equal to 0.1 psi and less than or equal to 3 psi, the wiring structure located around the edge of the integrated circuit chip is polished to expose the target low dielectric constant interline dielectric wiring layer.

Description

Anatomy of an integrated circuit chip

technical field

The invention relates to an anatomical method for an integrated circuit chip.

Background technique

With the development of integrated circuit technology, the integration level of circuit chips has been continuously improved, which is reflected in the increasingly dense circuit components, the width of connecting wires and the size of the entire chip are also continuously reduced. The entire device structure is developing in the direction of miniaturization, complexity and three-dimensionalization. At present, the feature size of integrated circuits has been developed to 22nm. The reduction of line width leads to severe RC transmission delay and coupling crosstalk between lines, which become the main factors limiting the transmission speed of circuit signals. In this case, metal copper with lower resistivity replaces the original metal aluminum as a new interconnection metal, and the dielectric material SiO ₂ commonly used in traditional integrated circuits is also replaced by a new metal with a dielectric constant k value less than 3.9. Dielectric material replaced. However, the mechanical strength of low-k dielectric materials is relatively low, and as the value of the dielectric constant k decreases, the mechanical strength tends to decrease further. The elastic modulus of the low-k dielectric material and the interconnection material copper is very different, and the bonding strength with the copper layer and the barrier layer is also relatively low, which leads to damage during processing and is easy to occur.

In order to solve the above problems, on the one hand, the international community has increased investment in the research of new materials, and on the other hand, has carried out research on low downforce or pressure-free flattening. Therefore, depackaging the used CPU chip to obtain the mechanical properties of the low-k dielectric layer has become an important means to study the processing performance of the low-k dielectric layer. For this reason, it was proposed to use ion etching to dissect the integrated circuit chip to obtain the low-k dielectric layer. However, this ion etching method is not only costly, but also the low-k dielectric layer samples obtained by this method have undergone large changes in mechanical properties due to high temperature and ion doping, so it is only suitable for observing wiring structures, not suitable for for mechanical performance tests.

Contents of the invention

In view of this, it is really necessary to provide an anatomical method of an integrated circuit chip in an integrated circuit, and the dielectric wiring layer between low-k lines obtained by the dissection method can be measured by AFM for the dielectric wiring layer between low-k lines Mechanical properties of the sample.

An anatomical method for an integrated circuit chip, comprising: providing an integrated circuit chip, the integrated circuit chip comprising a packaging layer, an upper layer wiring structure, a middle layer wiring structure and a lower layer wiring structure sequentially stacked, the lower layer wiring structure comprising at least A low-k inter-line dielectric wiring layer, the at least one low-k inter-line dielectric wiring layer has a target low-k inter-line dielectric wiring layer; using a chemical mechanical polishing method, under a first down pressure, with a first Removing the encapsulation layer at a one-line speed to expose the upper-layer wiring structure, the first pressing force is greater than or equal to 3 psi and less than or equal to 8 psi, and the first line speed is greater than or equal to 60 m/min and less than or equal to 240 m/min ; Using chemical mechanical polishing method, under a second downforce, remove the upper layer wiring structure to expose the middle wiring structure at a second linear speed, the second downforce is greater than or equal to 0.1psi and less than or equal to 3psi, and The second line speed is greater than or equal to 60 m/min and less than or equal to 240 m/min; the intermediate wiring structure is removed at a third line speed under a third downward pressure by chemical mechanical polishing until the lower layer is exposed For wiring structures, the third pressing force is greater than or equal to 0.1psi and less than or equal to 3psi, and the third line speed is greater than or equal to 60 m/min and less than or equal to 240 m/min; Under pressure, remove the underlying wiring structure at a third line speed to expose the target low-k interline dielectric wiring layer in the underlying wiring structure, the third pressing force is greater than or equal to 0.1psi and less than or equal to 3psi, and the The third line speed is less than or equal to 90 m/min.

A dissecting method of an integrated circuit chip, comprising: providing an integrated circuit chip, the integrated circuit chip includes a packaging layer and a wiring structure stacked in sequence, the wiring structure includes at least one low-k interline dielectric wiring layer, the At least one dielectric wiring layer between low-k lines has a target dielectric wiring layer between low-k lines; using chemical mechanical polishing method, under the downforce of greater than or equal to 3psi and less than or equal to 8psi, at a rate of greater than or equal to 60 m/min, And polishing the integrated circuit chip at a line speed of 240 m/min or less, removing the encapsulation layer around the edge of the integrated circuit chip to expose the wiring structure; and continuing to use chemical mechanical polishing at a rate greater than or equal to 0.1 psi, and Under a downward pressure of less than or equal to 3 psi, the wiring structure located around the edge of the integrated circuit chip is polished to expose the target low-k interline dielectric wiring layer.

Compared with the prior art, the present invention uses chemical mechanical polishing to dissect the integrated circuit chip to obtain the AFM sample of the low-k dielectric layer. This method can not only better preserve the dielectric wiring between the low-k lines The wiring structure of the layer structure, and can maintain the mechanical properties of the low-k dielectric layer, is more suitable as an AFM sample, and the mechanical properties of the low-k dielectric layer are measured by AFM. In addition, the method provided by the present invention mainly adopts the method of chemical polishing to obtain the AFM sample of the low-k dielectric layer, and the cost is relatively low, and the time used is relatively short.

Description of drawings

Fig. 1 is a flow chart of the method for dissecting an integrated circuit chip provided by the present invention.

FIG. 2 is a scanning electron micrograph of the CPU chip used in the embodiment of the present invention.

Fig. 3 is a scanning electron micrograph of the dielectric wiring layer between low-k lines suitable for AFM samples obtained after the CPU chip in Fig. 2 is processed by the method provided by the present invention.

Description of main component symbols

CPU chip 10 encapsulation layer 12 upper wiring structure 14 Intermediate Wiring Structure 16 underlying wiring structure 18

The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings.

Detailed ways

The method for dissecting an integrated circuit provided by the present invention to obtain a sample of the dielectric wiring layer between low-k lines measured by AFM will be further described in detail below with reference to the accompanying drawings and specific embodiments.

Please refer to Fig. 1, the present invention provides a kind of dissecting method in integrated circuit, and this method comprises the following steps:

S1, providing an integrated circuit chip, the integrated circuit chip includes a packaging layer and a lower layer wiring structure stacked in sequence, the lower layer wiring structure includes at least one low-k inter-line dielectric wiring layer, and the at least one low-k inter-line There is a target low-k interline dielectric wiring layer in the dielectric wiring layer; and

S2, using a chemical mechanical polishing method to remove the encapsulation layer until the target low-k inter-line dielectric wiring layer in the underlying wiring structure, to obtain a low-k inter-line dielectric wiring layer suitable for use as an AFM sample.

In step S1, the low-k interline dielectric wiring layer includes a low-k dielectric layer. In this paper, the dielectric constant of the dielectric wiring layer between low-k lines is less than or equal to 3. The integrated circuit chip is a bare chip, which generally includes the packaging layer and a wiring structure, and the wiring structure includes the lower layer wiring structure. The integrated circuit chip further includes a silicon base, and the lower wiring structure in the wiring structure is stacked on the silicon base. The encapsulation layer is used to protect the circuits in the integrated circuit chip. The lower wiring structure includes at least one low-k interline dielectric wiring layer, and the at least one low-k interline dielectric wiring layer includes at least two thin wires. Preferably, the distance between the at least two thin wires is less than or equal to 95 nanometers. Depending on the application of the integrated circuit chip, the structure of the integrated circuit chip is also different. Specifically, the wiring structure in the integrated circuit chip may consist of the lower layer wiring structure. The wiring structure in the integrated circuit chip may further include an upper-layer wiring structure, and the upper-layer wiring structure is stacked between the packaging layer and the at least one low-k interline dielectric wiring layer. The upper layer wiring structure includes at least one thick wiring layer, and the at least one thick wiring layer includes a plurality of thick wires, and the line width of each thick wire is larger than the line width of the thin wires. The wiring structure in the integrated circuit chip may further include an intermediate wiring structure, and the intermediate wiring structure is stacked between the upper layer wiring structure and the at least one low-k interline dielectric wiring layer. The intermediate wiring structure includes at least one middle-width wiring layer, the at least one middle-width wiring layer includes a plurality of intermediate wires, and the line width of each intermediate wire is smaller than the line width of the thick wire and larger than the line width of the thin wire . It can be understood that the lower layer wiring structure may include a multi-layered low-k inter-line dielectric wiring layer, and the target low-k inter-line dielectric wiring layer is one of the multi-layer low-k inter-line dielectric wiring layers layer or layers. The upper-layer wiring structure may include a multi-layered thick wiring layer. The intermediate wiring structure may include a multi-layer intermediate line width wiring layer stacked. Therefore, the integrated circuit chip usually has a multilayer wiring structure. Preferably, the integrated circuit chip is a VLSI chip. The integrated circuit chip may be a graphics card chip, a CPU chip, or the like.

This step S1 may include the following sub-steps: S11, providing a commercial integrated circuit chip, the integrated circuit chip including at least one pin, a circuit substrate, and the integrated circuit chip integrated circuit placed on the circuit substrate; and S12, using The strong acid removes the at least one pin and the circuit substrate at high temperature to obtain the integrated circuit chip with the encapsulation layer. Wherein, preferably, the integrated circuit is a used commercial integrated circuit.

Step S2 is mainly realized by using a chemical mechanical polishing machine. The degree of polishing of the integrated circuit chip is usually judged by an optical microscope. Wherein, the degree of polishing refers to which layer of the packaging layer and the wiring structure the integrated circuit chip is polished to. The step S2 is mainly to partially dissect the integrated circuit chip, specifically, preferentially dissect and polish to remove the encapsulation layer and wiring structure around the edge of the integrated circuit chip. Step S2 comprises the following steps:

S21, fixing the integrated circuit chip on a chemical mechanical polishing machine;

S22, using the chemical mechanical polishing machine to remove the encapsulation layer at a first linear speed under a first downward pressure until the underlying wiring structure is exposed; and

S23, using the chemical mechanical polisher to polish the underlying wiring structure at a second linear speed to expose the target low-k interline dielectric wiring layer under a second downforce, wherein the second downforce is less than The first pressing force, and the second linear speed is less than the first linear speed.

The chemical mechanical polisher includes a plurality of clamps for holding the integrated circuit. In step S21, the integrated circuit chip is first fixed on a share, and then fixed on the chemical mechanical polishing machine through a clamp, and at the same time, a plurality of share is fixed between the clamp and the integrated circuit chip to share the burden of the integrated circuit chip. The received load reduces the downward pressure on the integrated circuit chip, and it is easier to control the polishing progress and effect. Wherein, the material of the sharing object is not limited, as long as the sharing object can share the load on the integrated circuit chip. The allotment may be a resin block.

This step S21 may also be: firstly forming multiple scratches on the surface of the packaging layer of the integrated circuit chip, and the multiple scratches penetrate at least the packaging layer, preferably, the multiple scratches penetrate the The encapsulation layer is close to the silicon base, but the silicon base is not exposed; then, the integrated circuit chip formed with multiple scratches is fixed on the chemical mechanical polishing machine. The encapsulation layer and various wiring structures around the multiple scratched edges of the integrated circuit chip are relatively easy to be removed, so that it is relatively easy to expose the internal structure of the integrated circuit. In addition, the internal structure of the integrated circuit may also be exposed at the edge of the integrated circuit chip. According to the exposed internal structure of the integrated circuit chip, the encapsulation layer can be sequentially removed by chemical mechanical polishing until the target low-k inter-line dielectric wiring layer of the underlying wiring structure. In this way, it is relatively easy to control the polishing time and determine the polishing degree of each layer of the integrated circuit, making it easier and more convenient to dissect the integrated circuit chip by using the chemical mechanical polishing method.

Step S22 specifically uses the chemical mechanical polishing machine to remove the encapsulation layer by using op-s polishing fluid under the action of the first down force and the first linear speed. When the integrated circuit chip is composed of the encapsulation layer, the underlying wiring structure and a silicon substrate, that is, the encapsulation layer is directly arranged on the surface of the underlying wiring structure, step S22 may specifically be the use of the chemical mechanical polishing Under the first down force, the encapsulation layer is removed by using the first line speed and op-s polishing fluid until the underlying wiring structure is exposed, and the underlying wiring structure can be vaguely seen. Wherein, the first down force is between 3psi ~ 8psi, such as 4psi, 5psi, 6psi and so on. The first linear speed is 60 meters/minute (m/min)~240 m/min, such as 100 m/min, 120 m/min, 180 m/min, 200 m/min, 240 m/min, etc. The value of this first linear velocity is preferably not less than 60 m/min, otherwise the polishing time will be increased; the value of this first linear velocity cannot be too large, preferably not greater than 240m/min, otherwise it will be caused by the encapsulation layer at the same time If the thickness is relatively thin, severe over-throwing may occur, which may damage the target low-k inter-line dielectric wiring layer in the lower-layer wiring structure, and thus the AFM sample of the low-k inter-line dielectric wiring layer cannot be obtained. Wherein, the step S22 may use an optical microscope to observe whether the underlying wiring structure is exposed. When the underlying wiring structure is about to be exposed, an optical microscope can be used to observe whether the underlying wiring structure is exposed at intervals and whether to continue polishing. That is, an optical microscope can be used to determine whether the underlying wiring structure is exposed. It can also be said that step S22 uses an optical microscope to determine the specific polishing removal position of the integrated circuit chip.

When the integrated circuit chip further includes the upper layer wiring structure, the step S22 may be:

S221. Using the chemical mechanical polisher to remove the encapsulation layer at the first linear speed to expose the upper layer wiring structure under the first pressing force. Wherein, the step S221 may specifically be to first process the encapsulation layer at a relatively high first line speed until the upper layer wiring structure is exposed; and then continue to process the encapsulation layer at a relatively small first line speed until the exposed The upper wiring structure.

S222. Using the chemical mechanical polishing machine under the action of a third downward force and a third linear velocity, use a first polishing solution to remove the upper layer wiring structure until the lower layer wiring structure is exposed, wherein the first polishing liquid The three pressures are between 0.1psi ~ 3psi, such as 0.6psi, 1.5psi, 2psi, 2.5psi, etc. The third downforce is smaller than the first downforce. The third linear velocity is greater than or equal to 60 m/min and less than or equal to 240 m/min, and the third linear velocity is lower than the first linear velocity. Preferably, the third linear velocity is greater than or equal to 60 m/min and less than or equal to 120 m/min. The first polishing liquid may be a copper polishing liquid. An optical microscope may be used to determine whether the upper layer wiring structure is exposed.

When the integrated circuit chip includes an encapsulation layer, an upper-layer wiring structure, an intermediate wiring structure, and a lower-layer wiring structure stacked in sequence, the step S222 may be: under the action of the third pressing force and the third linear velocity , using the first polishing solution to remove the upper layer wiring structure to expose the middle wiring structure. The step S22 further includes a step S223: using the chemical mechanical polishing machine under the action of the third downward force and a fourth linear speed, using a second polishing solution to remove the intermediate wiring structure until the lower layer will be exposed wiring structure. Wherein, the fourth linear velocity is greater than or equal to 60 m/min and less than or equal to 120 m/min, and the fourth linear velocity is lower than the third linear velocity. The second polishing liquid is a barrier layer polishing liquid.

The target dielectric wiring layer between low-k lines obtained in step S23 can be used in AFM samples to measure the mechanical properties of the dielectric wiring layer between ow-k lines. The step S23 is to use the second polishing liquid to polish the low-k dielectric structure under the second pressing force and the second linear speed until the target low-k inter-line dielectric wiring with a smooth surface is exposed. layer, so as to obtain the AFM sample of the low-k dielectric layer, wherein the second downforce is less than the third downforce, and the second downforce is greater than 0.1 psi and less than or equal to 3 psi. The second linear velocity is less than the fourth linear velocity, and the second linear velocity is less than or equal to 90 m/min. Preferably, the second linear velocity is greater than or equal to 20 m/min and less than or equal to 60 m/min.

The step S23 further includes: using a scanning electron microscope to determine whether the obtained target dielectric wiring layer between low-k lines is suitable for an AFM sample. If the dielectric wiring layer between the low-k lines does not meet the requirements and is not suitable for AFM samples, continue to repeat step S23, and use the scanning electron microscope to observe the dielectric wiring layer between the target low-k lines again until a low-k layer that meets the requirements is obtained. That's it.

The first polishing liquid and the second polishing liquid in the steps S22 and S23 can be selected according to the materials of the upper wiring structure, middle wiring structure and lower wiring structure. In steps S221 to S223 and step S23 above, when the polishing time of steps S221 to S223 and step S23 is at least half, check with an optical microscope at intervals to determine whether to continue the polishing process and whether the upper layer has been removed The wiring structure, the intermediate wiring structure, and the exposed target low-k interline dielectric wiring layer.

The present invention will be explained in further detail below with specific examples.

Example

The present embodiment provides a sample preparation method for dissecting a commercial CPU chip to test the mechanical properties of a low-k dielectric layer. The method specifically includes the following steps:

1) Provide a commercial chemical mechanical polishing machine and a CPU chip 10, the CPU chip 10 is shown in Figure 2.

2) Stick the CPU chip 10 on a resin block, and then fix it on the chemical mechanical polishing machine, and fix 3 to 6 resin blocks between the fixture and the CPU chip to share the load on the CPU chip; use a diamond pen Draw two horizontal and vertical lines on the surface of the CPU chip to form four scratches.

3) Utilize the op-s polishing fluid that comes with the chemical mechanical polishing machine, adopt a line speed of 180m/min and a downforce of 3psi, the chemical mechanical polishing machine polishes the surface packaging layer 12 of the CPU chip 10, and the polishing time is 15min Reduce the line speed to 90m/min and polish for about 3 minutes. The encapsulation layer 12 in the edge area of the CPU chip 10 will be over-polished and expose the upper layer wiring structure 14, thereby removing the surface encapsulation layer 12 of the CPU chip 10.

4) Using copper polishing liquid, adopting a line speed of 90m/min and a downforce of 1psi, the chemical mechanical polishing machine continues to polish the above-mentioned CPU chip 10 with the upper layer wiring structure 14 exposed; when the polishing time is about 15min, the upper layer The edge of the scratch in the wiring structure 14 is over-polished to expose the lower wiring structure 18 , thereby removing the upper wiring structure 14 .

5) Using the barrier layer polishing liquid, the chemical mechanical polishing machine continues to polish the CPU chip 10 with the upper wiring structure 14 at the scratch removed at a line speed of 60m/min and a downforce of 1psi; when the polishing time is about 10min At this time, the scratched edge of the intermediate wiring structure 16 can faintly see the lower wiring structure 18, so the intermediate wiring structure 16 is removed.

6) Using the barrier layer polishing solution, the chemical mechanical polishing machine continues to polish the CPU chip 10 with the intermediate wiring structure 16 at the scratch removed at a line speed of 40m/min and a downforce of 0.5psi; when the polishing time is 10min On the left and right, the scratched edges of the lower layer wiring structure 18 expose the target low-k interline dielectric wiring layer with a relatively flat and smooth surface.

7) Observe the sample obtained in step 6) under a scanning electron microscope, search for a suitable structure on the edge and scratches of the CPU chip, and determine whether it meets the requirements, and it can be used as an AFM sample; if it does not meet the requirements, it cannot be used as an AFM sample , continue to repeat step 6), the polishing time is 30s, and observe again until it meets the requirements and can be used as an AFM sample. The target low-k interline dielectric wiring layer suitable for use as AFM samples is shown in Figure 3.

In addition, during the above steps 4), 5), and 6), an inspection is performed every two minutes during the second half of the polishing time to determine whether to continue polishing.

Therefore, the embodiment of the present invention adopts the chemical mechanical polishing method to dissect the CPU chip 10 to obtain the low-k inter-line dielectric wiring layer used as an AFM sample. This method can not only better retain the low-k inter-line dielectric The wiring structure of the dielectric wiring layer between the low-k lines in the wiring layer structure, and can maintain the mechanical properties of the low-k layer material, is more suitable for use as an AFM sample, and the AFM is used to measure the mechanical properties of the low-k dielectric layer characteristic. In addition, the method provided by the present invention mainly adopts the chemical mechanical polishing method to obtain the AFM sample of the low-k dielectric layer, as long as a chemical mechanical polishing machine is provided, no special equipment and instruments are needed, and the method does not require The encapsulation layer 12 in the CPU chip 10 is completely removed until each layer of the dielectric wiring layer between the target low-k lines is exposed, as long as the encapsulation layer 12 around the edge of the CPU chip 10 or around the scratch is exposed until the target low-k line is exposed. Each layer of the dielectric wiring layer between the k-lines can be removed, so the cost is relatively low, and the time used is relatively short. The inner structure of the CPU chip 10 is first exposed at the edge or scratch of the CPU chip 10 . According to the exposed internal structure of the CPU chip, the encapsulation layer located around the edge or the scratch can be sequentially removed by chemical mechanical polishing until the target low-k inter-line dielectric wiring layer of the underlying wiring structure is exposed. In this way, it is relatively easy to control the polishing time and determine the polishing degree of each layer of the integrated circuit, making it easier and more convenient to dissect the integrated circuit chip by using the chemical mechanical polishing method.

In addition, those skilled in the art can also make other changes within the spirit of the present invention, and these changes made according to the spirit of the present invention should be included in the scope of protection claimed by the present invention.

Claims (10)

1. An anatomical method for an integrated circuit chip, comprising: (1) Provide an integrated circuit chip, which includes a packaging layer, an upper-layer wiring structure, a middle-layer wiring structure, and a lower-layer wiring structure that are sequentially stacked, and the lower-layer wiring structure includes at least one low-permittivity line-to-line dielectric Wiring layer, the at least one dielectric wiring layer between low dielectric constant lines has a target low dielectric constant dielectric wiring layer between lines; (2) Using a chemical mechanical polishing method, under a first downforce, removing the encapsulation layer at a first linear speed to expose the upper layer wiring structure, the first downforce is greater than or equal to 3psi and less than or equal to 8psi, And the first linear speed is greater than or equal to 60 m/min and less than or equal to 240 m/min; (3) Using a chemical mechanical polishing method to remove the upper layer wiring structure at a second linear speed to expose the middle wiring structure under a second downforce, the second downforce is greater than or equal to 0.1psi and less than or equal to 3psi , and the second linear velocity is greater than or equal to 60 m/min and less than or equal to 240 m/min; (4) Using a chemical mechanical polishing method, under a third downforce, removing the intermediate wiring structure at a third line speed to expose the underlying wiring structure, the third downforce is greater than or equal to 0.1psi and less than or equal to 3 psi, and the third line speed is greater than or equal to 60 m/min and less than or equal to 240 m/min; and (5) Using a chemical mechanical polishing method, under a third downward pressure, removing the underlying wiring structure at a third line speed to expose the target low-permittivity line-to-line dielectric wiring layer in the underlying wiring structure, the first The third pressure is greater than or equal to 0.1 psi and less than or equal to 3 psi, and the third line speed is less than or equal to 90 m/min. 2. The method for dissecting an integrated circuit chip according to claim 1, wherein said step (2) comprises the following steps: (21) placing a plurality of apportionments between the integrated circuit chip and a chemical mechanical polisher, holding the integrated circuit chip in the chemical mechanical polisher, to share the load on the integrated circuit chip; and (22) Under the first down force, the chemical mechanical polisher uses op-s polishing liquid at the first linear speed to remove the encapsulation layer to expose the upper layer wiring structure. 3. The method for dissecting an integrated circuit chip according to claim 1, further comprising: forming a plurality of scratches on the surface of the packaging layer before the step (2), and the plurality of scratches At least the encapsulation layer is penetrated so as to determine the degree of polishing of the integrated circuit chip according to the internal structure of the integrated circuit chip exposed at the scratch. 4. The dissection method of an integrated circuit chip according to claim 1, characterized in that, said step (5) further comprises the step of: using a scanning electron microscope to determine whether the obtained target low dielectric constant dielectric wiring layer is suitable for atomic force microscope sample. 5. the dissecting method of the integrated circuit chip of sample preparation as claimed in claim 4, it is characterized in that, when the dielectric wiring layer between the target low dielectric constant line that obtains is not suitable for doing atomic force microscope sample, continue to repeat described step (5. ) Polishing the dielectric wiring layer between low dielectric constant lines and observing the target dielectric wiring layer between low dielectric constant lines with a scanning electron microscope until a low dielectric constant dielectric wiring layer suitable for atomic force microscope samples is obtained. 6 . The method for dissecting an integrated circuit chip according to claim 1 , wherein the step (2) to step (4) uses an optical microscope to determine the degree of polishing of the integrated circuit chip. 7 . 7. A method for dissecting an integrated circuit chip, comprising: (1) Provide an integrated circuit chip, the integrated circuit chip includes a packaging layer and a wiring structure stacked in sequence, the wiring structure includes at least one dielectric wiring layer between low dielectric constant lines, and the at least one low dielectric constant line There is an inter-dielectric wiring layer with a target low dielectric constant in the inter-dielectric wiring layer; (2) Using a chemical mechanical polishing method, under a downforce greater than or equal to 3 psi and less than or equal to 8 psi, the integrated circuit chip is polished at a line speed greater than or equal to 60 m/min and less than or equal to 240 m/min, removing the the encapsulation layer around the edge of the integrated circuit chip to expose the wiring structure; and (3) Continue to use the chemical mechanical polishing method to polish the wiring structure located around the edge of the integrated circuit chip until the target low dielectric constant line is exposed under a downforce of greater than or equal to 0.1psi and less than or equal to 3psi Dielectric wiring layer. 8. The method for dissecting an integrated circuit chip according to claim 7, wherein in step (1), the wiring structure is composed of a lower-layer wiring structure, and the lower-layer wiring structure includes multiple layers of low-dielectric For a constant line-to-line dielectric wiring layer, the step (3) is: using a chemical mechanical polishing machine to polish the The underlying wiring structure located around the edge of the integrated circuit chip exposes the target low dielectric constant interline dielectric wiring layer. 9. The method for dissecting an integrated circuit chip according to claim 7, wherein in step (1), the wiring structure includes an upper layer wiring structure and a lower layer wiring structure, and the upper layer wiring structure is stacked on the between the encapsulation layer and the underlying wiring structure; the step (3) includes the following steps: (31) Remove the upper layer wiring structure around the edge of the integrated circuit chip at a linear speed greater than or equal to 60 m/min and less than or equal to 240 m/min to expose the lower layer wiring structure; and (32) Polishing the underlying wiring structure located around the edge of the integrated circuit chip at a line speed of less than or equal to 90 m/min to expose the target low-permittivity interline dielectric wiring layer. 10. The method for dissecting an integrated circuit chip according to claim 7, characterized in that before the step (2), it further comprises the step of: forming a plurality of scratches on the surface of the packaging layer, and the plurality of scratches At least the encapsulation layer is penetrated so as to determine the degree of polishing of the integrated circuit chip according to the internal structure of the integrated circuit chip exposed at the scratch.

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