CN103474402A - Semiconductor package structure - Google Patents

Abstract

A semiconductor package structure comprises a semiconductor substrate, a welding pad layer, a polymer layer and a convex metal layer. The semiconductor substrate and the welding pad layer are covered by the polymer layer, an opening where the surface of one part of the welding pad layer is exposed is formed in the polymer layer, a plurality of separated polymer columns are arranged on the surface of the welding pad layer in the opening, and the convex lower metal layer is arranged on the surface of one part of the polymer layer outside the welding pad layer, the polymer columns and the opening. The semiconductor package structure is higher in reliability.

Description

Semiconductor Package Structure

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor packaging structure.

Background technique

Today, with the rapid development of information technology, the market prospect of integrated circuits is getting wider and wider. Correspondingly, the industries of integrated circuit design, chip manufacturing and integrated circuit packaging are all developing rapidly. In my country, the IC packaging industry has become an important economic growth point of the IC industry. In order to meet the needs of high-speed processing, multi-function, integration, miniaturization and low price of integrated circuit components, integrated circuit packaging technology also needs to be developed towards miniaturization and high density. Currently commonly used integrated circuit packaging technologies include Ball Grid Array (BGA), Chip-Scale Package (CSP) and Multi-Chip Module (MCM). In the packaging technology of integrated circuits, the packaging density of integrated circuits refers to the number of pins (Pins) contained in a unit area. For high-density integrated circuit packaging, shortening the length of wiring helps to improve signal The transmission speed, so the application of bump (Bump) has become the mainstream of high-density packaging.

Referring to FIG. 1 , FIG. 1 is a schematic cross-sectional structure diagram of a bump packaging structure in the prior art. The bump packaging structure includes: a semiconductor substrate 101, on which a pad layer 102 is formed; a passivation layer 103 covering the surface of the semiconductor substrate 101 and part of the pad layer 102, and the passivation layer 103 There is a first opening that exposes part of the surface of the pad layer 102; the metal layer 105 located on the surface of the pad layer 102 in the first opening and the part of the passivation layer 103 outside the first opening; the metal layer 105 located on the surface of the metal layer 105 bump 104 .

However, the reliability of the existing bump packaging structure still needs to be improved.

Contents of the invention

The problem solved by the invention is to improve the reliability of the semiconductor packaging structure.

In order to solve the above problems, the present invention provides a semiconductor packaging structure, comprising: a semiconductor substrate, a pad layer positioned on the semiconductor substrate; a polymer layer covering the semiconductor substrate and the pad layer, wherein the polymer layer has An opening exposing a portion of the surface of the pad layer with discrete polymeric posts on the surface of the pad layer within the opening; a raised metal layer on the portion of the surface of the polymeric layer outside the pad layer, polymeric posts, and opening .

Optionally, the material of the polymer column is the same as that of the polymer layer.

Optionally, the material of the polymer layer is a photosensitive organic substance.

Optionally, the photosensitive organic compound is photosensitive epoxy resin, polyimide, benzocyclobutene, polybenzoxazole.

Optionally, the number of the polymer columns is greater than or equal to one.

Optionally, the dimensions of the polymer posts are smaller than the dimensions of the openings.

Optionally, the thickness of the protruding metal layer is smaller than the height of the polymer column on the surface of the pad layer.

Optionally, the under-convex metal layer is a single-layer or multi-layer stacked structure.

Optionally, it also includes: a bump on the metal layer under the bump on the opening.

Optionally, it also includes: a metal column on the metal layer under the protrusion on the opening.

Compared with the prior art, the technical solution of the present invention has the following advantages:

The semiconductor package structure includes a polymer layer covering the semiconductor substrate and part of the pad layer, the polymer layer has an opening exposing the surface of the pad layer, and the surface of the pad layer in the opening has several discrete a polymer post; a raised metal layer on the surface of the pad layer, the polymer post and a portion of the polymer layer outside the opening. The presence of the polymer pillars increases the surface area of the under-convex metal layer in the opening, and when a bump or metal post is formed on the under-convex metal layer in the opening, the contact between the bump or the metal post and the under-protrusion metal layer The area is increased, thereby enhancing the adhesion between the bump or metal pillar and the metal layer under the protrusion, and preventing the bump or metal pillar from falling off the surface of the metal layer under the protrusion when the bump or metal pillar is subjected to external pressure or internal stress Or prevent crack defects from being generated at the contact interface between the two.

Further, the material of the polymer layer and the polymer column is the same, and the material of the polymer layer is a photosensitive organic substance, so after the polymer layer is formed, an opening can be formed in the polymer layer through exposure and development processes and is located in the opening The unique polymer column saves process steps.

Further, the thickness of the raised metal layer is less than the height of the polymer pillar on the surface of the pad layer, so that the surface of the formed raised metal layer rises and falls with the surface of the polymer pillar, increasing the formed raised metal layer. layer surface area.

Description of drawings

FIG. 1 is a schematic cross-sectional structure diagram of a bump packaging structure in the prior art;

2 to 7 are schematic cross-sectional structure diagrams of the formation process of the semiconductor package structure of the present invention.

Detailed ways

After research, the bumps of the existing packaging structure are located on the surface of the metal layer under the bumps, and when subjected to external pressure or internal stress, the bumps are easy to fall off from the surface of the metal layer under the bumps or between the bumps and the bumps. The contact interface of the metal layer produces crack defects, which affects the reliability of the packaging structure.

The present invention provides a semiconductor packaging structure and a method for forming the same. The semiconductor packaging structure includes a polymer layer covering the semiconductor base and a part of the pad layer, and the polymer layer has a surface exposed to the pad layer. There are several discrete polymer pillars on the surface of the welding pad layer inside the opening; and a raised metal layer on the surface of the welding pad layer, polymer pillars and part of the polymer layer outside the opening. The presence of the polymer pillars increases the surface area of the under-convex metal layer in the opening, and when a bump or metal post is formed on the under-convex metal layer in the opening, the contact between the bump or the metal post and the under-protrusion metal layer The area is increased, thereby enhancing the adhesion of the bump or metal pillar to the underlying metal layer.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present invention in detail, for convenience of explanation, the schematic diagrams will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which shall not limit the protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

2 to 7 are schematic cross-sectional structure diagrams of the formation process of the semiconductor package structure of the present invention.

First, referring to FIG. 2 , a semiconductor substrate 201 is provided, and a pad layer 202 is formed on the semiconductor substrate 201 .

Several internal chips (not shown in the figure) are formed in the semiconductor substrate 201, the pad layer 202 is connected to the internal chips in the semiconductor substrate 201, and the pad layer 202 is connected to an external chip as an internal chip Interface.

The semiconductor base 201 is a single-layer or multi-layer stack structure. When the semiconductor base 201 is a multi-layer stack structure, it includes a semiconductor substrate and at least one dielectric layer on the semiconductor substrate. The semiconductor substrate material can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon on insulator (SOI), germanium on insulator (GOI); or It can be other materials, such as group III-V compounds such as gallium arsenide.

The material of the pad layer 202 may be one or a combination of aluminum, copper, silver, gold, nickel, and tungsten. The bonding pad layer 202 is used to connect internal chips and external packaging components in the semiconductor substrate.

It should be noted that for the formation process of the pad layer 202 and the internal chip, please refer to the prior art, and the present invention does not limit it.

Next, referring to FIG. 3 , a polymer layer 203 covering the semiconductor substrate 201 and the pad layer 202 is formed, the polymer layer 203 has an opening 204 exposing part of the pad layer 202 surface, and the pad layer in the opening 204 Several discrete polymer pillars 205 are formed on the surface of 202 .

Before forming the polymer layer 203 , a passivation layer (not shown in the figure) may also be formed on the semiconductor substrate 201 and part of the pad layer 202 , the passivation layer is used to protect devices formed in the semiconductor substrate. The material of the passivation layer may be one or more of silicon nitride, silicon oxynitride, silicon oxide, borosilicate glass, phosphosilicate glass or borophosphosilicate glass. Because the passivation layer has a high hardness, and its material is relatively brittle, it is easy to be damaged, and it is easy to generate a large stress. Therefore, after forming the passivation layer, it is necessary to form a polymer layer 203 on the passivation layer. The texture of the polymer layer 203 Relatively soft, can effectively buffer the stress generated by the passivation layer, and the polymer layer 203 material has better heat resistance stability, high dielectric strength, low stress, low moisture absorption and metal base Excellent adhesion between materials, etc.

The polymer layer 203 is made of the same material as the polymer column 205, and the material of the polymer layer 203 in this embodiment is a photosensitive organic substance, so after the polymer layer is formed, it can be exposed and developed in the polymer layer. Forming the opening 204 and the polymer post 205 inside the opening 204 saves process steps.

The material of the polymer layer 203 is a photosensitive organic substance, and the photosensitive organic substance is a photosensitive epoxy resin, polyimide, benzocyclobutene, polybenzoxazole, and can be formed by exposing and developing the polymer layer 203. The opening 204 and the polymer pillar 205, and the remaining polymer layer 203 covering the semiconductor substrate 201 and part of the pad layer 202 can also serve as an isolation layer between the semiconductor package structure and the external environment. It should be noted that, the polymer layer 203 or the polymer column 205 may also use other suitable materials.

The forming process of the opening 204 and the polymer column 205 is as follows: forming a polymer layer 203 covering the surface of the semiconductor substrate 201 and the pad layer 202; exposing and developing to form a part of the surface of the pad layer exposed in the polymer layer 203. The opening 204 is formed, and several discrete polymer pillars 205 are formed on the surface of the pad layer 202 inside the opening 204 . In this embodiment, the height of the polymer column 205 is equal to the thickness of the polymer layer 203 on the surface of the pad layer 202 .

The number of the polymer column 205 is greater than or equal to 1, such as 1, 2, 3, 4, 5, 6, etc., and the size of the polymer column 205 is smaller than the size of the opening. In a specific embodiment, the number of polymer pillars 205 can be 2 to 5, which can not only increase the surface area of the subsequently formed under-convex metal layer, but also ensure that the formed under-convex metal layer is compatible with the solder joint. The pad layer 202 has electrical contact performance.

In a specific embodiment, the shape of the polymer column 205 may be cylindrical, truncated, cubic, or irregular.

In a specific embodiment, when there are multiple polymer pillars 205, the polymer pillars 205 can be arranged in a symmetrical figure (the figure formed by connecting the center points of each polymer pillar 205) in the middle area of the opening, so that the subsequent formation The increased surface area of the under-convex metal layer also has a certain line of symmetry, so that the adhesion between the bumps or metal pillars formed on the under-convex metal layer and the under-convex metal layer is the same in different directions, improving the Uniformity of resistance to compression or stress of bumps or metal pillars. Specifically, the symmetrical figures may be straight lines, circles, concentric rings, regular polygons (including triangles, quadrilaterals, pentagons, etc.), array structures, and the like. In other embodiments, the polymer pillars 205 may be arranged in an irregular pattern. It should be noted that the arrangement, quantity and shape of the polymer pillars cannot limit the protection scope of the present invention.

In a specific embodiment, the width of the bottom of the polymer column 205 is greater than the width of the top. When the metal layer under the protrusion is subsequently formed, it is prevented from blocking the opening between the polymer columns 205 between the metal layers under the protrusion, so that the protrusion under the metal layer can be prevented. The surface of the metal layer undulates with the polymer pillars 205, thereby forming a raised metal layer with an increased surface area.

In a specific embodiment, when the number of polymer pillars 205 is greater than two, the distance between adjacent polymer pillars 205 should be greater than twice the thickness of the subsequently formed under-convex metal layer, so that the subsequently formed under-convex metal layer The openings between the polymer pillars 205 are not filled, thereby forming a raised metal layer with increased surface area.

In the present invention, due to the existence of the polymer pillar 205, when forming the metal layer under the protrusion covering the solder pad layer 202 exposed in the opening 204, the polymer pillar 205 and part of the polymer layer 203, the protrusion formed in the opening 204 The surface of the lower metal layer is undulating, thereby increasing the size of the surface area of the lower metal layer. When bumps or metal pillars are formed on the surface of the lower metal layer on the opening 204, the bumps or metal pillars are in contact with the lower metal layer. The contact area of the layer increases, thereby increasing the adhesion between the bump or the metal pillar and the metal layer under the bump, and when the bump or the metal pillar is subjected to external pressure or internal stress, it prevents the bump or the metal pillar from being under the bump. The surface of the metal layer falls off or prevents crack defects from being generated at the contact interface between the two.

Next, please refer to FIG. 4 , forming a protruding metal layer 206 covering the pad layer 202 inside the opening 204 , the polymer column 205 and part of the surface of the polymer layer 203 outside the opening 204 .

The protruding metal layer 206 is used as a conductive layer or a seed layer for subsequent electroplating to form metal pillars, and as an adhesion layer between the metal pillars and the pad layer.

The under-convex metal layer 206 may be one or more of aluminum, nickel, copper, titanium, chromium, tantalum, gold, and silver.

The under-protrusion metal layer 206 may be a single-layer or multi-layer stack structure, for example, the under-protrusion metal layer 206 may be a double-layer stack structure of nickel-copper, titanium-gold, and nickel-aluminum.

The formation process of the under-raised metal layer 206 is sputtering or physical vapor deposition, etc., and the thickness of the under-raised metal layer 206 is less than the height of the polymer column 205 on the surface of the pad layer 202, so that the formed under-raised metal layer The surface of 206 undulates with the surface of polymer pillar 205, increasing the surface area of the metal layer formed under the protrusion.

Next, referring to FIG. 5 , a solder layer 207 is formed on the under-protruded metal layer 206 inside the opening and part of the under-protruded metal layer 206 outside the opening.

The material of the solder layer 207 is tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin zinc, tin bismuth indium, tin indium, tin gold, tin copper, tin zinc indium or tin silver antimony and other metals. One or more. A subsequent reflow process is performed on the solder layer 207 to form bumps.

The formation process of the solder layer 207 may be electroplating or screen printing. In this embodiment, the formation process of the solder layer 207 is electroplating, and the specific process is: forming a mask layer (such as a photoresist layer) covering the under-convex metal layer 206, and the mask layer has exposed The upper portion of the pad layer protrudes from the second opening on the surface of the lower metal layer 206; the lower metal layer 206 is used as a conductive layer during electroplating, and a solder layer 207 is formed in the second opening; finally, the mask layer is removed.

Referring to FIG. 6 , using the solder layer 207 (refer to FIG. 5 ) as a mask, remove the raised metal layer 206 on both sides of the solder layer 207; reflow the solder layer 207 to form bumps (or bumps or solder dots or solder balls) 208.

A wet or dry etching process may be used to remove the protruding metal layer 206 on both sides of the solder layer 207 .

For the reflow of the solder layer 207 , please refer to the existing reflow process, which will not be repeated here.

In other embodiments of the present invention, please refer to FIG. 7 , after the metal layer 206 is formed, an electroplating process may also be used to form metal pillars 209 on the metal layer 206 on the pad layer 202 . 209 forming a solder layer on the top surface; removing the metal layer protruding from both sides of the metal pillar 209 ; annealing the solder layer to form bumps (or bumps or solder points or solder balls) 210 on the top surface of the metal pillar 209 .

The metal pillar 209 is made of copper or a copper alloy containing other metals. The other metals may be one or more of tantalum, indium, tin, zinc, manganese, chromium or nickel. The metal pillar 209 can also be other suitable metal materials.

An embodiment of the present invention also provides a semiconductor package structure formed by the above method, please refer to FIG. 6 , including:

A semiconductor substrate 201, a pad layer 202 located on the semiconductor substrate 201;

The polymer layer 203 covering the semiconductor substrate 201 and the pad layer 202 has an opening in the polymer layer 203 that exposes part of the surface of the pad layer 202, and the pad layer 202 in the opening has several discrete polymer column 205;

The pad layer 202 , the polymer column 205 inside the opening, and the metal layer 206 protruding from the surface of the part of the polymer layer 203 outside the opening.

Specifically, the material of the polymer column 205 is the same as that of the polymer layer 203 . The material of the polymer layer 203 is a photosensitive organic substance, and the photosensitive organic substance is a photosensitive epoxy resin, polyimide, benzocyclobutene, and polybenzoxazole.

The number of the polymer column 205 is greater than or equal to one, and the size of the polymer column 205 is smaller than the size of the opening.

The thickness of the protruding metal layer 206 is smaller than the height of the polymer column 205 on the surface of the pad layer 202 .

The raised metal layer 206 is a single-layer or multi-layer stacked structure.

Also included is a bump 208 on the raised metal layer 206 over the opening.

In other embodiments of the present invention, please refer to FIG. 7 , which further includes: forming a metal post 209 on the metal layer 206 above the opening; and a bump 210 on the top surface of the metal post 209 .

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (10)

1. A semiconductor packaging structure, characterized in that, comprising: A semiconductor substrate, a pad layer located on the semiconductor substrate; A polymer layer covering the semiconductor substrate and the pad layer, the polymer layer has an opening exposing part of the surface of the pad layer, and there are several discrete polymer columns on the surface of the pad layer in the opening; The raised metal layer is located on the part of the surface of the polymer layer outside the pad layer, the polymer pillar and the opening. 2. The semiconductor package structure according to claim 1, wherein the material of the polymer pillar is the same as that of the polymer layer. 3. The semiconductor package structure according to claim 1, wherein the material of the polymer layer is a photosensitive organic substance. 4 . The semiconductor packaging structure according to claim 3 , wherein the photosensitive organic compound is photosensitive epoxy resin, polyimide, benzocyclobutene, or polybenzoxazole. 5 . The semiconductor package structure according to claim 1 , wherein the number of the polymer pillars is greater than or equal to one. 6. The semiconductor package structure of claim 5, wherein a size of the polymer pillar is smaller than a size of the opening. 7 . The semiconductor package structure according to claim 1 , wherein the thickness of the metal layer under protrusion is smaller than the height of the polymer column on the surface of the pad layer. 8 . 8 . The semiconductor package structure according to claim 1 , wherein the under-convex metal layer is a single-layer or multi-layer stacked structure. 9 . The semiconductor package structure according to claim 1 , further comprising: a bump on the metal layer above the opening. 10 . 10 . The semiconductor package structure according to claim 1 , further comprising: a metal post located on the metal layer above the opening. 11 .

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