CN103473213A - System for loading and extracting parallel information of optical vector-matrix multiplier - Google Patents

Abstract

The invention provides a system for loading and extracting parallel information of an optical vector-matrix multiplier. As an organic whole that operates independently and has its own system, the system gets rid of the shackles of discrete devices such as signal generators, oscilloscopes, and optical amplifiers, and can perform optical vector-matrix multipliers conveniently, intuitively, flexibly, and accurately. Test and analyze.

Description

System for Parallel Information Loading and Extraction in Optical Vector-Matrix Multipliers

technical field

The invention relates to the technical field of optical information processing, in particular to a system for loading and extracting parallel information of an optical vector-matrix multiplier. the

Background technique

The optical information processing method has the advantages of large bandwidth, strong parallelism, and small crosstalk. The vector-matrix multiplier based on the optical information processing method is suitable for completing intensive vector-matrix multiplication (Vector Matrix Multiplication, VMM) tasks and realizing high-speed multiplication and accumulation. (Multiplication and Accumulation, MAC) operation. The MAC operation is the core operation process in the process of digital signal processing. The study of optical digital signal processing technology based on optical vector-matrix multiplier can break through the bottleneck of electronic computing and realize high-speed optical computing. This technology can be widely used in massive data processing fields such as radar and sonar systems, image and voice recognition, password generation and cracking, resource detection and data analysis, and has attracted widespread attention from researchers at home and abroad. the

Oak Ridge National Laboratory in the United States discussed the application of optical digital signal processing technology in coastal sonar in the document "SENSOR DATA PROCESSING FOR TRACKING UNDERWATER THREATS USING TERASCALE OPTICAL CORE DEVICES." The time difference of arrival algorithm is designed, and the advantages of using optical vector-matrix multiplier to complete this kind of algorithm are analyzed. British BAE System company in the document "Digital Partitioning for Increased Dynamic Range in a Hybrid Optoelectronic Vector Matrix Processor." (4th EMRS DTC Technical Conference. Edinburgh: 2007: A14.) and the document "Optical Testbed for Hybrid Optoelectronic Vector Matrix for Optoelectronic Vect Processing." (3rd EMRS DTC Technical Conference. Edinburgh: 2006: B28.), the optical structure model of the vector-matrix multiplier is designed, and the array spot pattern of the designed optical system under the static signal is given. The M.Gruber group of Hagen University in Germany discussed the optical vector-matrix multiplication based on planar integration in the document "Planar-integrated optical vector-matrix multiplier." (Applied optics, 2000, 39(29): 5367-5373.) The research group used microfabrication methods such as multi-mask lithography and reactive ion etching to integrate the VMM structure on quartz glass, making the free-space optical vector-matrix multiplier compatible with electrical VLSI technology. Domestically, the National University of Defense Technology realized the physical link and static signal loading of the 4-way optical vector-matrix multiplier in 2009; the Suzhou Nano Institute of the Chinese Academy of Sciences explored the embedded structure of the spatial light modulator and the optical VMM core; China The Institute of Semiconductors of the Academy of Sciences realized the physical link of 16 optical vector-matrix multipliers in 2010, and completed the silicon-based integrated optical vector-matrix multiplier design and experimental verification at the end of 2011. the

The above documents are based on the optical vector-matrix multiplier itself, the simulation and design of the optical structure are carried out, and discrete standard instruments or equipment such as lasers, optical modulation modules, signal generators, and photoelectric detection modules are used to design the VMM. The unit is tested to verify the rationality of the designed optical structure. the

FIG. 1 is a schematic diagram of an information loading and extracting system for an optical vector-matrix multiplier in the prior art. Please refer to Figure 1. The system is based on commercial test equipment such as a pattern generator, laser light source, and real-time oscilloscope. The connection relationship between each device and device is as follows: pattern generator (1) and modulator matrix (2) through The cables are connected, and the modulator matrix (2) and the optical vector matrix multiplier are connected through optical fibers. The optical vector matrix multiplier is connected with the photodetector (4) through the optical fiber, and the photodetector (4) is connected with the real-time oscilloscope (5) through the cable. The light source part is a plurality of parallel sub-modules, each sub-module is represented by a dotted line box, each dotted line box represents a generation module of a vector element, in this module, the laser light source is connected to the electro-optic modulator through an optical fiber, and the pattern generator is passed through The cable is connected with the electro-optic modulator, and the output end of each electro-optic modulator is connected with the optical vector matrix multiplier through the optical fiber. As shown in Figure 1, arrows in dotted lines are optical port connections, and arrows in solid lines are electrical port connections. the

Based on the above device, for an n-way optical vector matrix multiplier, the information loading and extraction process of the existing system is as follows:

(1) Turn on the pattern generator and assign a value to the modulator matrix;

(2) Turn on module (6), module (7) ... module (6+n-1) in turn to adjust the input excitation of the vector matrix multiplier; the adjustment process for each module is as follows:

2.1 Turn on the laser light source and pattern generator, make the pattern generator generate a pseudo-random sequence, and obtain the waveform on the real-time oscilloscope; 

2.2 Adjust the intensity of the light source and the bias of the electro-optic modulator so that the voltage amplitude obtained on the real-time oscilloscope is between V _L and V _H.

(3) For module (6), module (7) ... module (6+n-1), the adjustment process as described in step (2) is carried out, so that each module can be obtained on the oscilloscope with an amplitude at V For the voltage signal between _L and V _H , record the parameters such as the intensity of the laser light source and the bias of the electro-optic modulator when the amplitude of the voltage signal between V _L and V _H is obtained on the oscilloscope. These parameters are collectively referred to as P _i (i=6, 7, ..., 6+n-1):

(4) Assign parameters P _i to modules (6), modules (7)...modules (6+n-1) respectively, so that n laser light sources, n code generators, and n electro-optic modulators are turned on simultaneously, Assign pseudo-random sequence codes with the same period length to each pattern generator in module (6), module (7) ... module (6+n-1), and keep a fixed phase difference between each signal ;

(5) Observe and record the waveform obtained on the oscilloscope at this time, and analyze the consistency between the waveform and the theoretical calculation result. the

In the process of realizing the present invention, the applicant found that the existing system for optical vector-matrix multiplier parallel information loading and extraction has the following defects:

(1) The information loading and extraction process is carried out on the test system built by existing discrete equipment or instruments, which is bulky, poor in flexibility and expandability;

(2) In the process of information loading and extraction, it is necessary to manually adjust each light source and electro-optic modulator repeatedly, and judge whether the excitation source parameters are appropriate by observing the waveform of the real-time oscilloscope. The adjustment process is very cumbersome and error-prone;

(3) The information loading and extraction process only stops at testing the function of the optical vector matrix multiplier computing core itself, without forming a photoelectric hybrid computing system with its own system, and it is difficult to adapt to the later algorithm research and put it into application. the

Contents of the invention

(1) Technical problems to be solved

In view of the above technical problems, the present invention provides a system for parallel high-speed information loading and extraction of optical vector-matrix multipliers. the

(2) Technical plan

In order to achieve the above object, the present invention is used for optical vector-matrix multiplier parallel information loading and extraction system comprising:

The input vector data cache module is used to cache the input vector original data;

Input matrix data cache module, used to cache the input matrix original data;

The data preprocessing module is used to: (a) adjust the resolution of the vector original data and the matrix original data respectively, so that the number of bits of the two matches the performance of the optical vector-matrix multiplier; (b) adjust the resolution of the original vector-matrix multiplier; The above vector data and matrix data are divided into blocks, so that the order of the vector data and matrix data matches the number of input channels of the optical vector-matrix multiplier;

The vector data loading module array is used to receive the vector data output by the front-end data preprocessing module, and convert each data element in the vector data into a current signal, which is respectively supplied to the corresponding lasers in the laser array;

A laser array, including several lasers, each of which is used to receive the modulation current switch signal output by the corresponding vector data loading module at the front end, and provide an array light source vector operator for the optical vector-matrix multiplier;

The matrix data loading module is used for: (a) receiving the low-resolution and low-order matrix data output in the front-end data preprocessing module, and converting each data element in the matrix data into DVI video encoding format data ; (b) receiving DVI video encoding format data, completing the loading of each pixel data of the spatial light modulator, and providing a matrix operator for the optical vector-matrix multiplier;

The detector array is used to receive the array optical signal from the output of the vector-matrix multiplier to represent the operation result. A single detector unit in the detector array converts the received optical signal into a photocurrent signal, and converts the photocurrent signal to Output to the operation result information extraction module;

The operation result information extraction module array is used to receive n-channel photocurrent signals of the front-end detector array, convert each channel photocurrent signal into a digital signal, and output it to the data post-processing module;

The data post-processing module is used for: (a) receiving the digital signal generated by the operation result information extraction module array, filtering the digital signal, removing noise in the digital signal, and forming a smooth discrete digital quantity; (b) filtering the digital signal Gaussian average of the smooth discrete digital quantity in each clock cycle to obtain the characteristic quantity representing the operation result in a certain period; (c) compare the characteristic quantity representing the operation result in a certain period with the set gray scale threshold and judgment, to obtain the grayscale value of the result of characterization vector-matrix multiplication;

Extract the information memory space, which is used to temporarily store the intermediate temporary data involved in operations such as data filtering, Gaussian averaging, and grayscale discrimination by the data post-processing module;

The result vector data cache module is used to cache the grayscale value of the representation vector-matrix multiplication result obtained by the data post-processing module, and send it out through the RapidIO high-speed serial interface. the

(3) Beneficial effects

As can be seen from the above technical solutions, the present invention is used for optical vector-matrix multiplier parallel information loading and extraction system has the following beneficial effects:

(1) The system for parallel high-speed information loading and extraction of the optical vector matrix multiplier proposed by the present invention, as an organic whole that operates independently and has its own system, gets rid of the need to use signal generators, oscilloscopes, optical amplifiers, etc. The shackles of discrete devices allow convenient, intuitive, flexible and accurate testing and analysis of optical vector-matrix multipliers;

(2) The system for parallel high-speed information loading and extraction of the optical vector matrix multiplier proposed by the present invention combines the peripheral detector information extraction module, laser module, and FPGA information processing unit to form a closed feedback system, which can Automatically adjust the excitation of each laser to the computing core to achieve self-calibration and correction;

(3) The system for parallel high-speed information loading and extraction of the optical vector matrix multiplier proposed by the present invention combines functions such as electrical information loading, raw data preprocessing, operation result postprocessing, system data synchronization and control with the optical computing core (that is, optical vector-matrix multiplier) organically combined to form a set of optical digital signal processing system with high-speed MAC core, which can meet the requirements of large-scale data processing in the fields of sonar, radar, cryptography, voice, image, etc. Real-time processing requirements for large-scale data. the

Description of drawings

FIG. 1 is a schematic diagram of a prior art information loading and extraction system for an optical vector-matrix multiplier. the

FIG. 2 is a schematic diagram of a system architecture for parallel high-speed information loading and extraction of an optical vector-matrix multiplier according to an embodiment of the present invention. the

Fig. 3 is a schematic diagram of a control bus structure for dynamically adjusting the output of a laser in a specific embodiment of the present invention. the

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be noted that, in the drawings or descriptions of the specification, similar or identical parts all use the same figure numbers. Implementations not shown or described in the accompanying drawings are forms known to those of ordinary skill in the art. Also, while this article may provide examples of parameters that include specific values, it should be understood that the parameters need not be exactly equal to the corresponding values, but rather may approximate the corresponding values within acceptable error margins or design constraints. In addition, the directional terms mentioned in the following embodiments, such as "upper", "lower", "front", "rear", "left", "right", etc., are only referring to the directions of the drawings. Accordingly, the directional terms are used to illustrate and not to limit the invention. the

The invention provides a system for parallel high-speed information loading and extraction of an optical vector-matrix multiplier, through the input vector data cache module, input matrix data cache module, data preprocessing module, vector data loading module array, matrix data loading module, vector-matrix multiplier, laser array, detector array, operation result information extraction module array, data post-processing module, extracted information memory space, result vector data cache module, etc. Optical digital signal processing system integration problem of operation core. the

In an exemplary embodiment of the present invention, a system for parallel high-speed information loading and extraction of an optical vector-matrix multiplier is provided, as shown in FIG. 2 . The system includes: input vector data cache module 1, input matrix data cache module 2, data preprocessing module 3, vector data loading module array 4 (including 4.1, 4.2...4.n and other submodules), matrix data loading module 5 , laser array 6, vector-matrix multiplier 7, detector array 8, operation result information extraction module array 9 (including submodules such as 9.1, 9.2...9.n), data post-processing module 10, and information extraction memory space 11 , the result vector data cache module 12 . in:

(1) Input vector data cache module

The input vector data cache module is used to cache the input vector original data, and it is realized by CY7C009 dual-port RAM. the

The input vector raw data is sent to the CY7C009 dual-port RAM through the RapidIO high-speed serial interface, and the real-time transmission of the vector raw data is completed through the CY7C009 dual-port RAM cache, and the cached data is sent to the data preprocessing module 3 middle. the

At the same time, the intermediate temporary data in the vector data preprocessing process is also temporarily stored in this module, so as to facilitate the preprocessing algorithm. the

(2) Input matrix data cache module

The input matrix data cache module is used to cache the input matrix original data, and it is realized by CY7C009 dual-port RAM. the

The original data block of the input matrix is sent to the CY7C009 dual-port RAM through the RapidIO high-speed serial interface, and the real-time transmission of the original data of the matrix is completed through the dual-port RAM cache, and the cached data is sent to the data formed by the XC5VLX50T FPGA device In preprocessing module 3. the

At the same time, the intermediate temporary data in the vector data preprocessing process is also temporarily stored in this module, so as to facilitate the preprocessing algorithm. the

(3) Data preprocessing module

Data preprocessing module for:

(a) Segment each element in the vector raw data and the matrix raw data so that its resolution is reduced, and the number of bits of the reduced-resolution vector data elements and matrix data elements matches the optical vector-matrix multiplier performance , for example: the optical vector-matrix multiplier requires 2 bits of input data, then the original vector data elements need to be divided into basic data units with 2 bits;

(b) Block the vector data and matrix data so that the order of the vector data and matrix data matches the number of input channels of the optical vector-matrix multiplier, for example: the number of input channels of the optical vector-matrix multiplier If it is 8-way, the order of vector data and matrix data will be divided into 8 orders at most. the

(4) Vector data loading module array

The vector data loading module array is used to receive the low-resolution and low-order vector data (each vector data contains n elements) output by the front-end data preprocessing module, and convert each data element in the vector data into The current signals are respectively supplied to corresponding lasers in the laser array. the

The vector data loading module array includes: n identical vector data loading modules arranged side by side, each vector data loading module provides current signal excitation for one laser, if the number of lasers is n, the corresponding data loading modules are respectively (4.1), (4.2)...(4.n). the

The vector data loading module includes: MAX9371 level conversion chip, MAX3669 current output driver chip, MAX5497 digital potentiometer chip, MAX5496 digital potentiometer chip, and MAX1978 temperature control chip. the

MAX9371 level conversion chip, used to receive the low-resolution and low-order vector data output by the front-end data preprocessing module, and convert it into a logic level signal that can be recognized by the input terminal of the MAX3669 current output driver chip;

The MAX3669 current output driver chip is used to generate a switch signal to control the modulation current of the corresponding laser according to the logic level signal generated by the MAX9371 to excite the corresponding laser. the

The MAX5497 digital potentiometer chip contains two variable resistors, which are respectively connected to the bias current and modulation current control terminals of the MAX3669. The MAX5497 is used to receive the control word generated by the FPGA in the front-end data preprocessing module. command, through which the size of the two internal variable resistors is controlled, and the output bias current and modulation current value of the MAX3669 are controlled by adjusting the size of the two resistance values. the

A variable resistor inside the MAX5496 digital potentiometer chip is connected to the automatic power control terminal of MAX3669. MAX5496 is used to receive the control word instruction generated by the FPGA in the front-end data preprocessing module, and control the internal variable resistor through this instruction. Size, by adjusting the resistance value to control the output power of MAX3669. the

Another variable resistor inside the MAX5496 digital potentiometer chip is connected to the temperature control terminal of the MAX1978 temperature control chip. The size of the variable resistance is controlled by adjusting the resistance value to control the temperature control point of MAX1978. MAX1978 controls the cooling module inside the laser through the PID feedback output feedback current to realize the temperature control of the laser. the

The MAX1978 temperature control chip is used to receive the temperature control point signal provided by MAX5496, output the feedback current through PID feedback, and transmit the feedback current to the laser to control the cooling module inside the laser to realize the temperature control of the laser. the

(5) Matrix data loading module

The matrix data loading module is composed of a CH7301C DVI encoding chip and a LC-R720 spatial light modulator. the

CH7301C DVI encoding chip, used to receive low-resolution and low-order matrix data (including n×n elements) output from the front-end data preprocessing module, and convert each data element in the matrix data into DVI Data in video encoding format is input to LC-R720 through the DVI interface. the

LC-R720C spatial light modulator is used to receive the DVI video encoding format data output by the CH7301C DVI encoding chip, complete the loading of each pixel data of the spatial light modulator, and realize providing matrix operators for the optical vector-matrix multiplier . the

(6) Laser array

The laser array is formed by coupling multiple 6001A DFB lasers with fiber arrays. the

Each laser in the laser array is used to receive the modulation current switch signal output by the MAX3669 in the front-end corresponding vector data loading module, and provide the array light source vector operator for the optical vector-matrix multiplier. At the same time, it also needs to receive the feedback current output by MAX1978 in the corresponding vector data loading module of the front end to complete its own cooling control. the

(7) Vector-matrix multiplier

The vector-matrix multiplier is realized by an optical system formed by a cylindrical lens, a circular lens, etc., and is used to receive the vector operator of the array light source from the laser array, and at the same time receive the matrix operator from the matrix data loading module to complete the multiplication and sum of signals in the optical domain. After the accumulation operation, an array optical signal representing the operation result is output. the

(8) Detector array

The detector array is composed of multiple RPD3000-FA photodetectors coupled with an optical fiber array. It is used to receive the array optical signal from the output of the vector-matrix multiplier to represent the operation result, and a single detector unit in the detector array converts the received optical signal into a photocurrent signal, and then outputs the photocurrent signal to the backend Corresponding operation result information extraction module. the

(9) Operation result information extraction module array

The operation result information extraction module array is used to receive n photocurrent signals from the front-end detector array, convert each photocurrent signal into a digital signal, and output it to the back-end data post-processing module. the

The operation result information extraction module array includes: n identical operation result information extraction modules are arranged side by side, and each operation result information extraction module receives one photocurrent signal. For example, the number of array optical signal channels output by the detector array is n, Then the corresponding operation result information extraction modules are (9.1), (9.2)...(9.n). the

The operation result information extraction module includes: OPA847 type transimpedance amplifier, THS4508 type secondary amplifier, ADS5474 type analog-to-digital converter. the

The OPA847 transimpedance amplifier is used to receive the photocurrent signal output by the corresponding detector at the front end, and convert it into a grayscale analog voltage signal representing the operation result after being amplified by transimpedance. the

The THS4508 secondary amplifier is used to receive the gray-scale analog voltage signal output by the front-end OPA847 transimpedance amplifier, amplify and shape it, and convert it into an amplified signal whose dynamic range and drive capability match the performance of the ADS5474 input terminal. Gray scale analog voltage signal. the

ADS5474 analog-to-digital converter is used to receive the amplified gray-scale analog voltage signal output by the front-end THS4508, convert it into a digital signal representing the operation result, and send the digital signal to the data post-processing module through the LVDS interface. the

(10) Data post-processing module

The data post-processing module is used for:

(a) Receive the digital signal generated by the ADS5474 analog-to-digital converter, filter the digital signal, remove the noise in the digital signal, and form a smooth discrete digital quantity;

(b) Perform Gaussian averaging on the smoothed discrete digital quantity after filtering in each clock cycle to obtain the characteristic quantity representing the operation result in a certain period;

(c) Comparing and judging the feature quantity of the characterization operation result in a certain period with the set gray-scale threshold, and obtaining the gray-scale value of the characterization vector-matrix multiplication result. the

The data post-processing module 10 and the data pre-processing module 3 use the same FPGA device, and the data pre-processing process and the data post-processing process are implemented in the same FPGA device through parallel hardware language. the

(11) Extract information memory space

The extracted information memory space is composed of IS61NLP25636A SRAM memory, and the extracted information memory space is connected with the post-processing module through an address bus and a data bus. The post-processing module performs operations such as filtering, Gaussian averaging, and gray-scale discrimination on the data, temporarily storing the intermediate temporary data in the extracted information memory space. the

(12) Result vector data cache module

The result vector data cache module is composed of CY7C009 dual-port RAM memory, which is used to cache the gray scale value of the vector-matrix multiplication result obtained by the data post-processing module, and send it through the RapidIO high-speed serial interface. the

In addition, the parallel information loading and extraction system of this embodiment also requires a power management module and a clock management module to provide power and clocks for the entire system. the

The working process and signal conversion relationship of the system are as follows:

First, the data preprocessing module accesses the input vector and matrix data cached in the dual-port RAM through the address bus. When the bit width of the input vector data element is k, the frequency of the system clock is multiplied so that the operating clock frequency of the VMM is the system K ² times the clock frequency, that is, one system clock cycle contains k ² VMM work cycles; when the vector order is 1×N and the matrix order is N×N, the number of vector data loading modules is N, for In the continuous VMM working cycle, the vector data loading module array receives the k-bit non-0 or 1 switching modulation signal from the data preprocessing module, converts it into a current signal and loads it on the corresponding laser.

At the same time, the matrix data loading module loads the matrix data to the vector-matrix multiplier through the DVI interface. the

Set the optical modulator matrix in the optical vector-matrix multiplier to be fully transparent, turn on each laser in turn, adjust the bias current and modulation current of the laser, so that for a certain detector, each laser can be in the The same signal excitation is obtained on the detector, the calibration of each laser is completed, and the calibration values of the bias current and the modulation current are recorded in the extracted information memory space. the

Then, the calibration value of the bias current and modulation current is used to apply the working current to the laser, the optical vector-matrix multiplier performs multiplication according to the loaded vector and matrix data, and the multiplication result vector passes through the detector array in the form of an optical signal output. the

The output signal of each detector in the 1×N detector array carries an element information in the result vector, and the output signal of each detector is read and analyzed through N operation result information extraction modules. the

For a single detector, the output signal is photocurrent, the current signal is amplified by a transimpedance amplifier and converted into an analog voltage signal, and then the analog voltage signal is amplified by a secondary amplifier to improve its driving ability and adjust its The dynamic range is matched to the input of the analog-to-digital converter. The back end of the analog-to-digital converter can obtain a series of discrete digital quantities representing the operation results. A series of discrete digital quantities obtained above are sent to the data post-processing module, and the post-processing module performs digital filtering on these digital quantities to obtain a smoothed gray scale curve. Gaussian averaging is performed on the smoothed data to obtain the feature quantity representing the operation result, and the feature quantity is compared and judged with the set gray scale threshold to obtain the gray scale value representing the vector-matrix multiplication result. the

Finally, load the gray scale value representing the vector-matrix multiplication result into the result vector data buffer module, and output the result through the output interface. the

FIG. 3 is a schematic diagram of the structure of the control bus for dynamically adjusting the laser bias current and modulation current in the system proposed by the present invention. The SPI bus signal is constructed by the data preprocessing module 3, after the signal is passed through the SN74LVTH241 type bus driver chip, an SPI signal bus with sufficient driving capability is formed, and the MAX5497 type (14, 16, 19, 21) and MAX5496 type (15, 17, 18, 20) The digital potentiometer is connected to the SPI bus as a slave, and the MAX3669 type (22, 24, 27, 29) laser power supply and the MAX1978 type (23, 25, 26, 28) temperature control chip are respectively controlled. control, so as to adjust the modulation current, bias current, working temperature and other parameters of the laser (30, 31, 32, 33). Turn on each laser in turn, and dynamically adjust and control the working parameters of each laser according to the readout signal of the detector, so that each laser generates an excitation signal with the same dynamic range for the same detector. the

So far, the system for parallel high-speed information loading and extraction of optical vector-matrix multipliers in this embodiment has been described in detail with reference to the accompanying drawings. Based on the above description, those skilled in the art should have a clear understanding of the present invention. the

In addition, the above-mentioned definitions of each element and method are not limited to the various specific structures, shapes or methods mentioned in the embodiments, and those of ordinary skill in the art can easily and well-known replace them, for example:

(1) The CY7C009 dual-port RAM device can also be realized by the dual-port RAM in the FPGA device;

(2) IS61NLP25636A RAM can be replaced by SST38VF6403;

(3) The OPA847 transimpedance amplifier can be replaced by ADA4817. the

In summary, the present invention provides a system for parallel high-speed information loading and extraction of optical vector-matrix multipliers. This system gets rid of the shackles of multiple separate devices in the traditional method, and forms an optical digital signal processing system that operates independently and has an autonomous system, self-calibration and adjustment functions, and can be widely used in cryptography, speech recognition, Radar systems, sonar systems and many other massive data processing fields. the

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention. the

Claims (10)

1. a system that loads and extract for the optical vector-matrix multiplier parallel information, is characterized in that, comprising:

The input vector data cache module, for the vectorial raw data of buffer memory input;

The input matrix data cache module, for the matrix raw data of buffer memory input;

Data preprocessing module, for: (a) resolution of described vectorial raw data and matrix raw data is adjusted respectively, both figure places and optical vector-matrix multiplier performance are complementary; (b) described vector data and matrix data are carried out to piecemeal, the exponent number of vector data and matrix data and the input end port number of optical vector-matrix multiplier are complementary;

Vector data load-on module array, for receiving the vector data of described front end data pretreatment module output, and be converted to current signal by each data element in vector data, is supplied to respectively corresponding laser instrument in laser array;

Laser array, comprise several laser instruments, and wherein each laser instrument is for the modulating current switching signal of the corresponding vector data load-on module output of receiving front-end, for optical vector-matrix multiplier provides the array light source vectorial operator;

The matrix data load-on module, for: (a) receive low resolution that described front end data pretreatment module exports and the matrix data of low exponent number, and convert each data element in matrix data to DVI video code model data; (b) receive DVI video code model data, complete the loading of each pixel data of spatial light modulator, for optical vector-matrix multiplier provides matrix operator;

Detector array, for receiving the array light signal from the sign operation result of Vector-Matrix Multiplier output, single detector unit in detector array, after the light signal received is converted to photo-signal, output to photo-signal in the operation result information extraction modules;

Operation result information extraction modules array, for the n road photo-signal of receiving front-end detector array, Bing Jiangmei road photo-signal is converted to digital signal, exports in the Data Post module;

The Data Post module, for: (a) receive the digital signal that operation result information extraction modules array produces, digital signal is carried out to filtering, remove the noise in digital signal, form level and smooth discrete digital amount; (b) filtered level and smooth discrete digital amount is carried out to Gauss in each clock period average, obtain characterizing in certain cycle the characteristic quantity of operation result; (c) characteristic quantity of the sign operation result in certain cycle and the gray scale rank thresholding set are compared and adjudicate, obtain characterizing the gray scale rank value of vector-matrix multiplication result;

The information extraction memory headroom, carry out the related middle ephemeral datas of computing such as filtering, Gauss are average, the differentiation of gray scale rank to data for the temporal data post-processing module;

The result vector data cache module, the gray scale rank value of the sign obtained for data cached post-processing module vector-matrix multiplication result, and it is sent through the RapidIO HSSI High-Speed Serial Interface.

2. system according to claim 1, is characterized in that, described Data Post module and data preprocessing module are realized by a slice XC5VLX50T type FPGA device and peripheral prom memory thereof, the hardware language realization of both functions in this FPGA device.

3. system according to claim 1, is characterized in that, described input vector data cache module and input matrix data cache module are realized by corresponding CY7C009 type dual port RAM respectively.

4. system according to claim 1, is characterized in that, described vector data load-on module array comprises: the n be set up in parallel a vector data load-on module; Each vector data load-on module, for a road laser instrument provides the current signal excitation, comprising:

MAX9371 type level transferring chip, for the low resolution of receiving front-end data preprocessing module output and the vector data of low exponent number, and be converted into the logic level signal that the MAX3669 current-output type drives the chip input end to identify;

The MAX3669 current-output type drives chip, for the logic level signal produced according to MAX9371 type level transferring chip, produces the switching signal of controlling corresponding laser modulation current, encourages corresponding laser instrument.

MAX5497 type digital regulation resistance chip, include two variable resistors, these two adjustable resistances are connected with the modulating current control end with the bias current of MAX3669 respectively, this MAX5497 type digital regulation resistance chip is for receiving the control word instruction that data preprocessing module FPGA produces, control its inner two variable-resistance sizes by this instruction, by the size of regulating these two resistance values, control output offset electric current and the modulation electric flow valuve that the MAX3669 current-output type drives chip;

MAX5496 type digital regulation resistance chip, a variable resistor of its inside drives the automated power control end of chip to be connected with the MAX3669 current-output type, the control word instruction that this MAX5496 type digital regulation resistance chip produces for receiving front-end data preprocessing module FPGA, control its inner variable-resistance size by this instruction, by regulating this resistance value, control the output power that the MAX3669 current-output type drives chip.

5. system according to claim 1, is characterized in that, in described vector data load-on module array, each vector data load-on module also comprises: MAX1978 type temperature control chip, wherein:

Described MAX5496 type digital regulation resistance chip, another inner variable resistor is connected with the temperature control end of MAX1978 type temperature control chip, the control word instruction that this MAX5496 type digital regulation resistance chip produces for the receiving front-end pretreatment module, control its inner variable-resistance size by this instruction, control the temperature control point of MAX1978 type temperature control chip by regulating this resistance value;

Described MAX1978 type temperature control chip, for receiving the temperature control point signal that MAX5496 type digital regulation resistance chip provides, feed back the output feedback current by PID, send this feedback current to laser instrument, control the refrigeration module of laser instrument inside, realize the temperature of laser instrument is controlled.

6. system according to claim 1, is characterized in that, described matrix data load-on module consists of CH7301C type DVI coding chip and LC-R720 type spatial light modulator, wherein:

Described CH7301C type DVI coding chip, the low resolution of exporting from the front end data pretreatment module for reception and the matrix data of low exponent number, and convert each data element in matrix data to DVI video code model data, by the DVI interface, input in LC-R720 type spatial light modulator;

Described LC-R720 type spatial light modulator, the DVI video code model data of exporting for receiving CH7301C type DVI coding chip, complete the loading of each pixel data of spatial light modulator, and being embodied as optical vector-matrix multiplier provides matrix operator.

7. system according to claim 1, is characterized in that, described laser array is formed by a plurality of 6001A type Distributed Feedback Lasers and fiber array coupling; Described detector array is coupled to form by a plurality of RPD3000-FA type photodetectors and fiber array.

8. system according to claim 1, is characterized in that, described operation result information extraction modules array comprises: the n be set up in parallel an identical operation result information extraction modules; Each operation result information extraction modules receives a road photo-signal, comprising:

OPA847 type trans-impedance amplifier, the photo-signal of exporting for the corresponding detector of receiving front-end, after amplifying across resistance, convert the gray scale rank analog voltage signal that characterizes operation result to;

THS4508 type secondary amplifier, the gray scale rank analog voltage signal of exporting for receiving front-end OPA847 type trans-impedance amplifier, it is amplified and shaping after, convert the gray scale rank analog voltage signal after the amplification that dynamic range and driving force and ADS5474 input end performance be complementary to;

The ADS5474 analog to digital converter, gray scale rank analog voltage signal after the amplification of exporting for receiving front-end THS4508 type secondary amplifier, be converted into the digital signal that characterizes operation result, and this digital signal is sent into to the Data Post module by the LVDS interface.

9. system according to claim 1, is characterized in that, described information extraction memory headroom is realized by IS61NLP25636A type SRAM storer; Described result vector data cache module consists of CY7C009 type RAM.

10. according to the described system of any one in claim 1 to 9, it is characterized in that, its course of work and signal transformational relation are as follows:

At first, data preprocessing module is by input vector and the matrix data of address bus access cache in input vector data cache module and input matrix data cache module, when the bit wide of input vector data element is k, system clock is carried out to frequency multiplication, and the working clock frequency that makes VMM is the k of system clock frequency ²doubly; When vectorial exponent number is 1 * N, when the matrix exponent number is N * N, vector data load-on module number is N, for the continuous VMM work period, vector data load-on module array received, from non-zero i.e. 1 the switch modulation signal in the k position of data preprocessing module, is converted into current signal and is loaded on corresponding laser instrument; Meanwhile, the matrix data load-on module is loaded into Vector-Matrix Multiplier by the DVI interface by matrix data;

Secondly, light modulator matrix in optical vector matrix multiplier is set to full impregnated, open successively each road laser instrument of laser array, regulate bias current and the modulating current of laser instrument, make for the detector of a certain road, each laser instrument all can obtain identical signal excitation on this detector, completes the demarcation to each laser instrument, and the calibration value of bias current and modulating current is recorded in the information extraction memory headroom;

Then, adopt the calibration value of bias current and modulating current to apply working current to laser instrument, optical vector-matrix multiplier carries out multiplying according to loaded vector sum matrix data, by the multiplication result vector by detector array the formal output with light signal;

In detector array, the output signal of each detector has been carried an element information in the result vector, by N operation result information extraction modules, respectively the output signal of each detector is read and analyzes; For single detector, its output signal is photocurrent, by trans-impedance amplifier, this current signal amplified and be converted to analog voltage signal, then by the secondary amplifier, this analog voltage signal is amplified, the dynamic range that promotes its driving force and regulate it makes it the input end coupling with analog to digital converter; The rear end of analog to digital converter obtains characterizing the series of discrete digital quantity of operation result; The above series of discrete digital quantity obtained is sent into to the Data Post module, after post-processing module is carried out digital filtering to these digital quantities, obtain the gray scale rank curve after level and smooth; Data after level and smooth are carried out to Gauss average, obtain characterizing the characteristic quantity of operation result, this characteristic quantity and the gray scale rank thresholding set are compared and adjudicate, obtain characterizing the gray scale rank value of vector-matrix multiplication result;

Finally, the gray scale rank value that characterizes vector-matrix multiplication result is written into to the result vector data cache module, and by output interface, result is exported.

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