CN103441791A - A launcher for satellite-borne data transmission and a method for selecting input signals thereof - Google Patents

Abstract

The invention discloses a satellite-borne data transmission transmitting device and a selection method of input signals thereof. The invention has the following beneficial effects: the data transmission transmitting device is not influenced by the cold backup single machine when receiving the source signal of the information source processor, so that the stability and the reliability of the system are improved; the complexity of hardware implementation is controlled as much as possible, a judging circuit for judging whether a clock signal exists or not is not required to be additionally added, an original hardware platform is kept basically unchanged, and only the FPGA unit is adjusted; the OC door signal is sent by current system of observing and controling branch, does not increase new hardware structure, make full use of existing equipment, realizes and practices thrift the cost easily.

Description

A launcher for satellite-borne data transmission and a method for selecting input signals thereof

technical field

The invention belongs to the technical field of data transmission, and in particular relates to a transmitting device for selecting an input signal through command control and a method for selecting the input signal, which can be commonly used in the field of satellite data transmission.

Background technique

In the satellite data transmission system, the function of the data transmission transmitter is to receive the effective data from the source processor, complete the channel coding and modulation functions, send the signal to the power amplification device, and finally send it to the ground through the antenna. In practical applications, in order to ensure the reliability of the whole star, the data transmission system usually adopts the form of main backup, and some key stand-alone machines also adopt the form of cross backup. When the cross-backup form is adopted between the source processor and the data transmission transmitter, one data transmission transmitter needs to receive two sets of source signals from two source processors, so it needs to select between the two sets of source signals. A set of input signals used as a data transmission transmitter.

In the case of limited satellite resources, the backup form of the source processor usually adopts a cold backup method, that is, one is turned on and the other is turned off. Therefore, the current common data transmission device will come from two source processors. The source signals are simply connected together to realize the "wire-AND" function, and then sent to the FPGA unit for channel coding and modulation.

This method of selecting cross-backup signals through "wire and" is very simple to implement, but the biggest disadvantage is that the quality of the input signal cannot be guaranteed, and then bit errors occur, because the signal source processor and the data transmission transmitter are used between It is a high-speed serial LVDS signal. When the source processor is not turned on, the signal received by the data transmission transmitter will be interfered, and the interference signal will be transmitted to the useful signal through the "wire and" method. As a result, the quality of the input signal deteriorates, and even a bit error occurs at the output end.

Contents of the invention

In order to overcome the defects existing in the prior art, the present invention provides a transmitting device for selecting an input signal through command control and a method for selecting an input signal thereof. The specific technical solutions are as follows:

A spaceborne data transmission and launching device, including an FPGA module, and two LVDS interface circuits and one instruction interface circuit respectively connected to it, each of the two LVDS interface circuits receives a group of source signals, and each group of source signals includes a data signal and a clock signal; the FPGA module is provided with a channel coding unit;

The FPGA module is provided with an instruction interface logic unit, a logic state judgment unit and a signal selection unit connected in sequence, wherein the instruction interface logic unit is connected to the instruction interface circuit, and the signal selection unit is respectively connected to two LVDS interface circuits and a channel coding unit;

The instruction interface circuit is used to receive two OC gate instructions, and then input the two OC gate instructions into the instruction interface logic unit respectively; the instruction interface logic unit processes the two OC gate instructions to generate corresponding logic states; the logic state judgment unit The state is judged, and the control signal is output to the signal selection unit; the signal selection unit receives two sets of source signals from the two LVDS interface circuits, and selects a set of source signals according to the control signal and sends them to the channel coding unit for processing.

As an optimized solution, the instruction interface logic unit includes two inverters and a D flip-flop, and the two inverters are respectively connected to the D flip-flop; each inverter corresponds to an OC gate instruction, and the two OC gate instructions pass through the After the corresponding inverter, the D flip-flop is input, and the D flip-flop generates the corresponding logic state according to the two OC gate instructions.

As an optimized solution, the signal selection unit includes a data selector and a clock selector, the data selector respectively receives two data signals in two sets of source signals, and the clock selector receives two clock signals in two sets of source signals respectively; the control signal The data selector and the clock selector are respectively input, the data selector selects a data signal according to the control signal and sends it to the channel coding unit for processing, and the clock selector selects a clock signal according to the control signal and sends it to the channel coding unit for processing.

As an optimization scheme, two OC gate commands are output by the measurement and control subsystem.

As an optimization scheme, two sets of source signals are respectively output by two source processors.

A method for selecting an input signal of a satellite-borne data transmission transmitter is used to select one group from two groups of source signals as an input signal of the satellite-borne data transmission transmitter; comprising the following steps:

Send two OC gate commands to the on-board data transmission transmitter, each OC gate command corresponds to a set of source signals;

Send two OC gate instructions to the FPGA unit in the spaceborne data transmission launcher;

In the FPGA unit, an instruction interface logic unit, a logic state judgment unit and a signal selection unit are generated, and the interface logic unit is used to process two OC gate instructions to generate corresponding logic states; the logic state judgment unit is used to judge the logic state and generate Corresponding control signals; use the signal selection unit to receive two groups of source signals, and select a group of source signals to output according to the control signals.

Compared with the prior art, the present invention has the following beneficial effects:

(1) The present invention prevents the data transmission transmitting device from being affected by the cold backup stand-alone when receiving the source signal of the source processor, thereby improving the stability and reliability of the system;

(2) The present invention controls the complexity of hardware implementation as far as possible, does not need additional judging circuits for the presence or absence of clock signals, keeps the original hardware platform basically unchanged, and only adjusts the FPGA unit;

(3) The OC gate signal is sent by the existing measurement and control subsystem, without adding a new hardware structure, making full use of existing equipment, easy to implement and cost-saving.

Description of drawings

Fig. 1 is a structural block diagram of the present invention;

Fig. 2 is a schematic circuit diagram of the OC gate instruction processing part of the present invention. the

Detailed ways

The present invention will be described in detail below by means of embodiments in conjunction with the accompanying drawings.

Example 1:

As shown in FIG. 1 , an on-board data transmission and launching device includes an FPGA module, and two LVDS interface circuits and one instruction interface circuit respectively connected to it. Each of the two LVDS interface circuits receives a set of source signals. The two sets of source signals are respectively output by two source processors. Each set of source signals includes a clock signal and a data signal with a bit width of 2 bits; the FPGA module is equipped with a channel A coding unit, the channel coding unit is used to perform channel coding processing on the source signal. the

The FPGA module is provided with an instruction interface logic unit, a logic state judgment unit and a signal selection unit connected in sequence, wherein the instruction interface logic unit is connected to the instruction interface circuit, and the signal selection unit is respectively connected to two LVDS interface circuits and a channel coding unit. FPGA (Field-Programmable Gate Array) refers to the Field Programmable Gate Array, which uses a circuit design written in HDL language (Hardware Description Language, Hardware Description Language), and is quickly burned to the FPGA after simple synthesis and layout. carry out testing. The instruction interface logic unit, the logic state judgment unit and the signal selection unit are all written and generated by HDL language in the FPGA module.

The instruction interface circuit is used to receive two OC gate instructions, and then input the two OC gate instructions into the instruction interface logic unit respectively; the instruction interface logic unit processes the two OC gate instructions to generate corresponding logic states; the logic state judgment unit The state is judged, and the control signal is output to the signal selection unit; the signal selection unit receives two sets of source signals from the two LVDS interface circuits, and selects a set of source signals according to the control signal and sends them to the channel coding unit for processing.

The LVDS interface circuit is existing on the original hardware platform, using the LVDS interface chip; usually the LVDS interface chip is a high-impedance output when it is not working, but in actual work, the state of the interface level is related to the pull-up and pull-down resistors. related to the value of . In order to prevent the influence on the normal data due to the uncertain level of the LVDS data interface, the data transmission and launching device selects the data input of the main and standby two source processors through the remote control command issued by the measurement and control subsystem. That is, the OC gate instruction. The OC gate command is output by the measurement and control subsystem, and the measurement and control subsystem is connected to the data transmission transmitter through the command line. Among them, the OC gate (Open Collector) command refers to the open collector gate command. When the command is not active, the OC gate output It is in a high-impedance state, and the command line is pulled up to +3.3V by a resistor inside the data transmission transmitter device; when the command is active, the command line and the ground wire are in a low-impedance state, and a command input terminal inside the data transmission transmitter device generates a Negative pulse with a pulse width of 160±10ms.

The command interface circuit is existing on the original hardware platform, and the CMOS reverse Schmitt trigger 54HC14 is used as the interface chip to perform (reverse) shaping on the received OC gate command and eliminate glitches.

In this embodiment, the instruction interface logic unit includes two inverters and a D flip-flop, and the two inverters are respectively connected to the D flip-flop; each inverter corresponds to an OC gate instruction, and two OC gate instructions After passing through the corresponding inverters, the D flip-flops are input, and the D flip-flops generate corresponding logic states according to the two OC gate instructions.

The working principle of the instruction interface logic unit is as follows:

Suppose two source processors are source processor A and source processor B respectively, source processor A outputs source signal A, and source processor B outputs source signal B; set the OC gate corresponding to source signal A The instruction is selection instruction A, and the OC gate instruction corresponding to source signal B is selection instruction B.

The selection command A and selection command B input to the FPGA module are respectively connected to the asynchronous set terminal (pin S) and asynchronous reset terminal (pin R) of the D flip-flop (active low) after passing through the inverter, and the D trigger The D input terminal of the device and the CP terminal maintain a "0" state. When the negative pulse of a certain OC gate instruction arrives, the output terminal Q of the D flip-flop enters the corresponding logic state. The truth table of the specific logic state is shown in Table 1. For indefinite states of Q, the FPGA does nothing.

1 OC gate instruction logic state truth table

S R

1 1 x x 0 1 1 0 1 0 0 1 0 0 x x

As shown above, the state of the output terminal Q will be related to the two OC gate instructions. When the selection instruction A is received, R=“0” and Q=“0”, and then the signal selection unit is controlled to output the source signal A, send subsequent channel coding and modulation, when receiving selection command B, S=“0”, Q=“1”, then control the signal selection unit, output source signal B, send subsequent channel coding and modulation .

The signal selection unit includes a data selector and a clock selector. The data selector receives two data signals from two sets of source signals respectively, and the clock selector receives two clock signals from two sets of source signals respectively. The control signals are respectively input to the data selector. The data selector selects a data signal according to the control signal and sends it to the channel coding unit for processing, and the clock selector selects a clock signal according to the control signal and sends it to the channel coding unit for processing.

A method for selecting an input signal of a satellite-borne data transmission transmitter is used to select one group from two groups of source signals as an input signal of the satellite-borne data transmission transmitter; comprising the following steps:

Send two OC gate commands to the on-board data transmission transmitter, each OC gate command corresponds to a group of source signals;

Send two OC gate instructions to the FPGA unit in the spaceborne data transmission launcher;

In the FPGA unit, an instruction interface logic unit, a logic state judgment unit and a signal selection unit are generated, and the interface logic unit is used to process two OC gate instructions to generate corresponding logic states; the logic state judgment unit is used to judge the logic state and generate Corresponding control signals; use the signal selection unit to receive two groups of source signals, and select a group of source signals to output according to the control signals.

The command line of the measurement and control subsystem and the data transmission transmitter can be connected in a cross-backup mode, as shown in Figure 2, that is, each command line of the measurement and control subsystem is connected to two data transmission transmitters (A machine and B machine) , to simultaneously control the input signal required for the selection of two data transmission transmitters.

The above disclosures are only a few specific embodiments of the present application, but the present application is not limited thereto. Any changes conceivable by those skilled in the art should fall within the protection scope of the present application.

Claims (6)

1. a spaceborne transfer of data emitter, comprise the FPGA module, and coupled two-way LVDS interface circuit and the road instruction interface circuit of difference, described two-way LVDS interface circuit respectively receives one group of source signal, and every group of source signal comprises data-signal and clock signal; Be provided with the chnnel coding unit in described FPGA module; It is characterized in that,

Be provided with the instruction interface logical block, logic state judging unit and the signal selected cell that connect successively in described FPGA module, wherein said instruction interface logical block is connected with described instruction interface circuit, and described signal selected cell is connected with described two-way LVDS interface circuit and described chnnel coding unit respectively;

Described instruction interface circuit is used for receiving the instruction of two OC doors, then the instruction of described two OC doors is inputted respectively to described instruction interface logical block; Described instruction interface logical block to described two OC doors instruction process and generate corresponding logic state; Described logic state judging unit is judged described logic state, outputs a control signal to described signal selected cell; Described signal selected cell receives two groups of source signals from described two-way LVDS interface circuit respectively, and according to described control signal, selects one group of source signal to send to described chnnel coding unit and processed.

2. a kind of spaceborne transfer of data emitter according to claim 1, is characterized in that, described instruction interface logical block comprises two inverters and a d type flip flop, and described two inverters are connected with described d type flip flop respectively; The corresponding OC door instruction of each inverter, the instruction of two OC doors by after corresponding inverter, is inputted described d type flip flop respectively, and according to described two OC doors, instruction generates corresponding logic state to described d type flip flop.

3. a kind of spaceborne transfer of data emitter according to claim 1 and 2, it is characterized in that, described signal selected cell comprises data selector and clock selector, described data selector receives respectively two groups of two paths of data signals in source signal, and described clock selector receives respectively two groups of two-way clock signals in source signal; Described control signal is inputted respectively described data selector and described clock selector, described data selector is selected a circuit-switched data signal to send to described chnnel coding unit according to described control signal to be processed, and described clock selector is selected a road clock signal to send to described chnnel coding unit according to described control signal to be processed.

4. a kind of spaceborne transfer of data emitter according to claim 1, is characterized in that, the instruction of described two OC doors is exported by tracking-telemetry and command subsystem.

5. a kind of spaceborne transfer of data emitter according to claim 1, is characterized in that, described two groups of source signals are respectively by two message source process machine outputs.

6. the input signal system of selection of a spaceborne transfer of data emitter, for selecting one group of input signal as described spaceborne transfer of data emitter at two groups of source signals; It is characterized in that, comprise the steps:

Send the instruction of two OC doors to spaceborne transfer of data emitter, every corresponding one group of source signal of OC door instruction;

The instruction of described two OC doors is sent into to the FPGA unit in described spaceborne transfer of data emitter;

Generate instruction interface logical block, logic state judging unit and signal selected cell in described FPGA unit, utilize described interface logic unit to described two OC doors instruction processes the corresponding logic state of generation; Utilize described logic state judging unit to be judged described logic state, and generate corresponding control signal; Utilize described signal selected cell to receive described two groups of source signals, and select one group of source signal output according to described control signal.

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