CN103441763A - Infrared focal-plane array and analog-digital converter of reading circuit thereof - Google Patents

Abstract

The embodiment of the present invention discloses an analog-to-digital converter for an infrared focal plane array readout circuit, including a comparator, a bias circuit, a linear ramp generator, a latch, and a nonlinear compensation counter. The nonlinear compensation The counter counts a counting clock sequence with unequal periods, wherein the counting clock sequence with unequal periods includes at least two counting clock subsequences, and the counting clock periods in each counting clock subsequence are different. In the analog-to-digital converter of the embodiment of the present invention, the nonlinear compensation counter can effectively compensate the nonlinearity between the digital output and the target temperature, eliminate the output nonlinearity caused by nonlinear radiation, and improve the linearity of the voltage response rate degrees, extending the linear temperature response range. Moreover, the non-linear compensation counter of the analog-to-digital converter has the function of adjustable start time, which improves the effective utilization rate of digital codes and improves the effective resolution.

Description

An Infrared Focal Plane Array and Its Readout Circuit Analog-to-Digital Converter

technical field

The invention relates to the field of uncooled infrared focal plane array detectors, in particular to an analog-to-digital converter of an infrared focal plane array readout circuit and an infrared focal plane array thereof.

Background technique

With the continuous development of CMOS VLSI technology, infrared focal plane technology and digital integrated circuit technology, people have gradually realized that converting the analog output signal of the infrared focal plane into a digital signal output can improve the anti-interference of the signal during transmission. The ability to improve the signal-to-noise ratio of the signal is also the development trend of the third-generation infrared focal plane technology's continuous miniaturization and continuous improvement of integration.

Infrared focal plane on-chip analog-to-digital converter (ADC) technology is a very key technology for converting the infrared focal plane analog signal output into digital signal output. The on-chip ADC of the readout circuit is very important in the digitization of the infrared focal plane readout circuit. The key device plays a decisive role in the final performance of the digital infrared focal plane. There are many types and structures of ADCs, so that many choices are often encountered in the design process of the readout circuit.

Uncooled infrared focal plane detectors work at room temperature and have the advantages of low cost, low power consumption, miniaturization and high reliability, and are widely used in military and civilian fields. When it is used, it is hoped to obtain a large temperature response range and a voltage response rate with good linearity through the readout circuit, and most of the subsequent non-uniformity correction algorithms assume that the response characteristic of the detection unit to the target temperature is linear carried out on the basis of By changing the incident black body radiation to investigate the relationship between the responsivity and the incident radiation, it is obtained that the output voltage of the infrared detector and the radiation flux radiated to the photosensitive element present a non-negligible nonlinear relationship.

According to Planck's law and the relationship between the temperature change of the detector sensitive unit caused by the target temperature change, the temperature of the sensitive unit changes nonlinearly with the target temperature, and the nonlinear radiation makes the voltage response of the bias circuit also nonlinear. The target temperature causes the analog output to change non-linearly, and the infrared radiation sensed by the sensitive unit is converted through the traditional readout circuit ADC, and the obtained digital output is also non-linear with the target temperature. Therefore, it is of great significance to study an on-chip ADC with uncooled infrared focal plane readout circuit with nonlinear radiation compensation function.

Contents of the invention

One of the objects of the present invention is to provide an analog-to-digital converter of an infrared focal plane array readout circuit and its infrared focal plane array with nonlinear radiation compensation function, so as to realize the linearization of the output signal of the readout circuit.

The technical solutions disclosed in the embodiments of the present invention include:

An analog-to-digital converter of an infrared focal plane array readout circuit is provided, which is characterized in that it includes: a comparator, the comparator includes a non-inverting input terminal, an inverting input terminal and an output terminal; a bias circuit, the bias circuit The output end of setting circuit is connected to the described inverting input end of described comparator; Linear ramp generator, the output end of described linear ramp wave generator is connected to the described non-inverting input end of described comparator; Latch device, the latch includes a control input terminal and a latch data input terminal, the output terminal of the comparator is connected to the control input terminal of the latch; a non-linear compensation counter, the non-linear compensation counter The count data output end of the latch is connected to the latch data input end of the latch; the non-linear compensation counter counts the unequal cycle count clock sequence and outputs the count data to the latch; wherein the The unequal period counting clock sequence includes at least two counting clock subsequences, and the counting clock period in at least one counting clock subsequence is different from the counting clock period in the remaining counting clock subsequences.

In one embodiment of the present invention, the nonlinear compensation counter includes: a basic clock; a clock generator with unequal periods, the output terminal of the basic clock is connected to the input terminal of the clock generator with unequal periods, and the The equal-period clock generator generates the unequal-period counting clock sequence according to the clock signal provided by the basic clock; the counter, the output end of the unequal-period clock generator is connected to the counting clock input end of the counter, and the The output terminal of the counter is the counting data output terminal of the nonlinear compensation counter; wherein the counter counts the unequal period counting clock sequence.

In an embodiment of the present invention, the counting clock sequence with unequal periods includes an initial clock subsequence and at least two counting clock subsequences.

In an embodiment of the present invention, the clock signal in the initial clock subsequence is kept at a low level.

表示向上取整，M为满足

的最小值，其中为控制因子，ψ_i为线性逼近所述锁存器的数字输出与所述比较器的比较时间之间的函数关系曲线的第i个直线段，ψ为所述锁存器的数字输出与所述比较器的比较时间之间的函数关系曲线，表示第i个时间段内上述两个函数的范数。 In one embodiment of the present invention, the counting clock sequence with unequal periods includes m counting clock subsequences, wherein ,

Indicates rounding up, and M is satisfied

The minimum value of , wherein is the control factor, ψ _i is the i-th straight line segment of the function relationship curve between the digital output of the linear approximation to the comparison time of the comparator and the comparator, and ψ is the latch The function curve between the digital output and the comparison time of the comparator, Indicates the norm of the above two functions in the i-th time period.

In an embodiment of the present invention, the number of counting clocks in each counting clock subsequence is the same.

An embodiment of the present invention also provides an infrared focal plane array, including a readout circuit, characterized in that the readout circuit includes any analog-to-digital converter described above.

In the analog-to-digital converter of the embodiment of the present invention, the nonlinear compensation counter can effectively compensate the nonlinearity between the digital output and the target temperature, eliminate the output nonlinearity caused by nonlinear radiation, and improve the linearity of the voltage response rate degrees, extending the linear temperature response range. Moreover, the non-linear compensation counter of the analog-to-digital converter has the function of adjustable start time, which improves the effective utilization rate of digital codes and improves the effective resolution.

The analog-to-digital converter of the embodiment of the present invention is very suitable for application in low-power and small-volume infrared detectors, and has great market development potential.

Description of drawings

FIG. 1 is a schematic diagram of a circuit structure of an existing analog-to-digital converter.

FIG. 2 is a schematic diagram of the relationship between the output of the conventional analog-to-digital converter and the target temperature.

FIG. 3 is a schematic diagram of a circuit structure of an analog-to-digital converter according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of the relationship between the output of the analog-to-digital converter and the target temperature according to an embodiment of the present invention.

FIG. 5 is a timing diagram of a non-linear compensation counter according to an embodiment of the present invention.

Detailed ways

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

An analog-to-digital converter (ADC) of an infrared focal plane array readout circuit in the prior art usually includes a bias circuit 10 , a linear ramp generator 12 , a comparator 15 , a latch 16 and a counter 18 . Its schematic diagram of circuit structure is shown in Figure 1, and will not be described in detail here.

In the analog-to-digital converter of the prior art infrared focal plane array readout circuit shown in FIG. 1, a conventional counter 18 is used. The analog output voltage Vout obtained in this circuit is:

     （1）。

(1).

In the formula, V _REF is the reference voltage, Vs is the bias voltage of the sensitive unit, I _b is the reference current; R _s0 is the initial resistance of the sensitive unit, α is the temperature coefficient of resistance (TCR); t _INT is the integration time, C _INT is the integrating capacitor. It can be simplified by Taylor expansion to:

     （2）。

(2).

When ignoring the change of TCR with temperature, it can be seen that because the thermal radiation of the detection target of the infrared focal plane array is nonlinear, the voltage response of the infrared focal plane array is also nonlinear. As the temperature of the target increases, the thermal radiation of the focal plane array The output voltage gradually increases, and changes slowly at low temperatures, and rapidly at high temperatures, so the detection details of low-temperature objects are not clear, while high-temperature objects over-response.

The schematic diagram of the change of the output caused by the change of the target temperature is shown in Fig. 2 . From (a) to (d) in Figure 2 are the relationship curves of analog output voltage and target temperature, the relationship curves of analog output voltage and comparison time, the relationship curves of digital output and comparison time, and the relationship curves of digital output and target temperature.

It can be seen from Fig. 2(a) that the target temperature makes the analog output V _out change nonlinearly. Figure 2(b) corresponds to the influence of the ramp generator in the ADC on the output, and Figure 2(c) corresponds to the influence of the counter in the ADC on the output.

At the same time, it can be seen from Figure 2(d) that due to the low low temperature response, there is almost no response output voltage from 0V to 1V, that is, the lower digital code is almost not output in actual use, which reduces the effective resolution.

FIG. 3 is a schematic structural diagram of an analog-to-digital converter of an infrared focal plane array readout circuit according to an embodiment of the present invention. As shown in Figure 3, in this embodiment, the analog-to-digital converter of the infrared focal plane array readout circuit includes a comparator bias circuit 10, a linear ramp generator 12, a comparator 15, a latch 16 and a nonlinear compensation Counter 28.

The comparator 15 includes a non-inverting input terminal, an inverting input terminal and an output terminal, and the output terminal of the bias circuit 10 is connected to the inverting input terminal of the comparator. Here, the specific structure of the bias circuit 10 may be the same as that of the bias circuit in the analog-to-digital converter of the infrared focal plane array readout circuit commonly used in the art, and will not be described in detail here.

The output of the linear ramp generator 12 is connected to the non-inverting input of a comparator 15 . The linear ramp generator 12 is used to generate a linear ramp, and its specific structure may be the same as that of a common linear ramp generator in the art, and will not be described in detail here.

The latch 16 includes a control input and a latched data input. The output of comparator 15 is connected to the control input of latch 16 . The number of bits of the latch can be N. Here, N is an integer greater than zero.

The count data output of the nonlinear compensation counter 28 is connected to the latch data input of the latch 16 .

In the embodiment of the present invention, the non-linear compensation counter 28 counts the unequal-period count clock sequence and outputs the count data to the latch 15 . Wherein, in the embodiment of the present invention, the unequal cycle counting clock sequence includes at least two counting clock subsequences, and wherein the counting clock period in at least one counting clock subsequence is different from the counting clock period in the remaining counting clock subsequences .

In this article, the "counting clock sequence" refers to a series of clock pulse signals, wherein the counter counts these clock pulse signals; the "counting clock sub-sequence" refers to the sub set or part.

It can be seen from Fig. 3 that the linear output ramp V _ramp generated by the linear ramp generator 12 is connected to the non-inverting input terminal of the comparator 15, and the analog output voltage V _out generated by the bias circuit 10 which has a nonlinear relationship with the target temperature is connected to The inverting input terminal of the comparator 15, the comparator 15 flips when V _out = V _ramp ; the output terminal of the comparator 15 is connected to the N-bit latch 16, wherein N is an integer greater than zero, and the N-bit latch 16 The N-bit digital output signal D _-out is output under the control of the comparator 15 .

In the embodiment of the present invention, a non-linear compensating counter 28 is used instead of the conventional counter. As shown in FIG. 3 , the non-linear compensation counter 28 includes a basic clock 282 , a clock generator 286 with unequal periods and a counter 280 .

The output terminal of the basic clock 282 is connected to the input terminal of the variable-period clock generator 286 to provide the basic clock signal for the variable-period clock generator 286 . The basic clock 282 here may be a commonly used clock source, such as a crystal oscillator and the like.

The unequal period clock generator 286 generates the aforementioned unequal period count clock sequence (detailed below) according to the clock signal provided by the basic clock 282 .

The output terminal of the unequal period clock generator 286 is connected to the counting clock input terminal of the counter 280 , where the output terminal of the counter 280 is the counting data output terminal of the non-linear compensation counter 28 . Here, the counter 280 counts the unequal period count clock sequence provided by the unequal period clock generator 286 . In an embodiment of the present invention, the counter 280 may be a conventional counter.

The counting sequence diagram of an example of counter 280 is as shown in Figure 5, wherein clk is a basic clock, namely the clock signal of basic clock 282 output, that is, the counting clock of conventional counter; clk _out is the aforementioned unequal period counting clock sequence An example of , that is, an example of the count clock of the nonlinear compensation counter 28 .

The unequal period counting clock sequence and its generation process are described in detail below.

In the structure of the analog-to-digital converter of the embodiment of the present invention, the change of the output caused by the change of the target temperature is shown in FIG. 4 . The non-linear compensation counter will be further described in detail in conjunction with FIG. 4 and FIG. 5 .

，图4（b）为模拟输出电压V_out与比较时间t的关系，表示为，为了使图4（d）中数字输出信号D-_out与目标温度T_t成线性关系

，可以从图4（c）中数字输出信号D-_out与比较时间t的关系着手，求得满足条件的函数表达式。求解方法可以如下： Figure 4(a) shows the relationship between the analog output voltage V _out and the target temperature T _t , assuming that the functional relationship between the two is

, Figure 4(b) shows the relationship between the analog output voltage V _out and the comparison time t, expressed as , in order to make the digital output signal D- _out in Figure 4(d) linearly related to the target temperature T _t

, can start from the relationship between the digital output signal D- _out and the comparison time t in Figure 4(c), and obtain the function expression that satisfies the condition. The solution method can be as follows:

，再将图4（b）中、图4（d）中

代入上式，即得到数字输出信号D-_out与比较时间t的函数关系为

，记为

。 First find out in Figure 4(a) inverse function of

, and then in Figure 4(b) , Figure 4(d)

Substituting into the above formula, the functional relationship between the digital output signal D- _out and the comparison time t is obtained as

, denoted as

.

来进行计数。由该函数可知，数字输出与比较时间的关系曲线为非线性曲线，可由m段直线线性逼近而成，每段直线记为ψ_i，其中1≤i≤m。为满足上述非线性关系，不同段中的计数时钟周期应不等；为实现非线性补偿功能，每段直线中计数器的计数个数应相等。 The unequal period counting clock sequence in the embodiment of the present invention can be based on the function

to count. It can be seen from this function that the relationship curve between digital output and comparison time is a nonlinear curve, which can be formed by linear approximation of m straight lines, and each straight line is marked as ψ _i , where 1≤i≤m. In order to satisfy the above-mentioned nonlinear relationship, the counting clock cycles in different segments should be different; in order to realize the nonlinear compensation function, the counting numbers of the counters in each straight line should be equal.

的最小M值来确定，

，其中是控制因子，用来控制直线段向曲线的逼近程度，可以根据需要选定，越小，M值越大，直线段向曲线的拟合效果越好；求解泛函问题，确定M时，已将时间轴划分为M段；ψ_i为线性逼近锁存器16的数字输出V_out与比较器15的比较时间t之间的函数关系曲线的第i个直线段。 The m value of the division number is satisfied by solving

The minimum value of M to determine,

, where is the control factor, which is used to control the degree of approximation of the straight line to the curve. It can be selected according to the needs. The smaller the value of M, the better the fitting effect of the straight line to the curve; to solve the functional problem, when determining M , the time axis has been divided into M segments; ψ _i is the ith straight line segment of the function relationship curve between the digital output V _out of the linear approximation latch 16 and the comparison time t of the comparator 15 .

。非线性补偿计数器在划分的m个时间段内，按不同的时间周期进行计数，每段各计n个数。这m+1个时间段内的所有时钟脉冲即构成了前述的不等周期计数时钟序列，也就是非线性补偿计数器28的计数时钟序列。 In Figure 4(b) and Figure 4(c), the time axis is divided into m+1 segments according to the calculated value of m. The specific division is based on solving the functional problem. When M is determined, the divided M segments are properly approximated and divided. They are sequentially recorded as T ₀ time period, T ₁ time period, ..., T _m time period. In the T ₁ ~T _m time period, each segment should count the same number of numbers, assuming that there are n, the output range of the N-bit ADC is 0 to 2 ^N -1, and the maximum counting value of the corresponding counter is 2 ^N , then

. The non-linear compensation counter counts according to different time periods within the divided m time periods, and counts n numbers in each period. All the clock pulses in these m+1 time periods constitute the aforementioned counting clock sequence with unequal periods, that is, the counting clock sequence of the non-linear compensation counter 28 .

During the T ₀ time period, the count output clock clk _out of the non-linear radiation compensation counter has been kept at a low level, waiting for the start of counting. Because of the waiting time in the T ₀ time period, the nonlinear radiation compensation counter has the function of adjusting the counting start time, so that the counting does not start from the zero point of the time axis, corresponding to the digital output in Figure 4 (d) and In the target temperature graph, there is a responsive output voltage from 0V, making full use of all digital codes.

的时间计1次数，这里，运算“

”表示四舍五入运算，使

为基本时钟clk的整数倍。则输出时钟clk_out在T₁时间段内的时钟周期clk1为

，从高电平开始，经过一个clk1计数加1，直到T1时间段结束，一共计了n个数。 For example, in the T1 time period, to count n numbers, every

The time is counted 1 times, here, the operation "

"Indicates a rounding operation, so that

It is an integer multiple of the basic clock clk. Then the clock cycle clk1 of the output clock clk _out in the T ₁ time period is

, starting from the high level, after a clk1 count plus 1, until the end of the T1 time period, a total of n numbers.

的时间计1次数，则输出时钟clk_out在T₂时间段内的时钟周期clk2为

，从高电平开始，经过一个clk2计数加1，直到T₂时间段结束，又计了n个数，此时一共计了2n个数。 Similarly, in the T _{+ 2} time period, n numbers are also counted, every

The time counts 1 times, then the clock cycle clk2 of the output clock clk _out in the T ₂ time period is

, starting from the high level, after a clk2 count plus 1, until the end of the T ₂ time period, n numbers are counted, and a total of 2n numbers are counted at this time.

，…，在T_m时间段里clk_out的计数周期为

，每个时间段计n个数，划分了m+1个时间段，除去第一个时间段为等待时间段，共有m个时间段在计数，则总共计了

个数，由此可知本发明中片上ADC的精度为

bit，其中

表示向上取整。 By analogy, the counting cycle of clk _out in the T ₃ time period is

,..., the counting cycle of clk _out in the T _m time period is

, each time period counts n numbers, divides m+1 time periods, removes the first time period as the waiting time period, and there are m time periods counting, then the total

number, thus it can be known that the precision of ADC on chip in the present invention is

bit, where

Indicates rounding up.

According to this counting sequence, the relationship between the digital code and the counting time is shown in Figure 4(c). The relationship between the counting code and time is no longer the linear relationship of a conventional counter, but a piecewise linear relationship. T ₁ ~ T _m are not equal, so the counting periods clk1 ~ clk m of the nonlinear compensation counter in each time period are also not equal, and they increase sequentially. The denser the division of the time period, the smoother the curve corresponding to Figure 4(c), and the closer the relationship between the count number and time is to the nonlinear relationship with the characteristics of the gamma curve. It is the transmission model of this gamma curve that enables the non-linear compensation counter in the present invention to have the function of gamma correction, and gamma correction is a non-linear compensation process. Corresponding to the relationship between digital output and target temperature in Figure 4(d), it can be seen that through the nonlinear curve of the nonlinear compensation counter, the nonlinearity of the output signal is eliminated, and the nonlinearity between the digital output D _out and the target temperature Compensation is performed so that the relationship of the digital output signal to the target temperature becomes linear.

In this paper, the clock pulse sequence in this T ₀ time period is called "initial clock subsequence", and the counting clock pulse sequence in other time periods is called "counting clock subsequence". Therefore, it can be seen from the foregoing that in an embodiment of the present invention, the counting clock sequence with unequal periods may include an initial clock subsequence and at least two counting clock subsequences.

In an embodiment of the present invention, an infrared focal plane array may also be provided, and the infrared focal plane array includes a readout circuit, and the readout circuit includes any analog-to-digital converter described above.

In the analog-to-digital converter of the embodiment of the present invention, the nonlinear compensation counter can effectively compensate the nonlinearity between the digital output and the target temperature, eliminate the output nonlinearity caused by nonlinear radiation, and improve the linearity of the voltage response rate degrees, extending the linear temperature response range. Moreover, the non-linear compensation counter of the analog-to-digital converter has the function of adjustable start time, which improves the effective utilization rate of digital codes and improves the effective resolution.

The present invention has been described above through specific examples, but the present invention is not limited to these specific examples. Those skilled in the art should understand that various modifications, equivalent replacements, changes, etc. can also be made to the present invention. As long as these changes do not deviate from the spirit of the present invention, they should all be within the protection scope of the present invention. In addition, "one embodiment" described in many places above represents different embodiments, and of course all or part of them may be combined in one embodiment.

Claims (7)

1. the analog to digital converter of an infrared focal plane array reading circuit, is characterized in that, comprising:

Comparator, described comparator comprises in-phase input end, inverting input and output;

Biasing circuit, the output of described biasing circuit is connected to the described inverting input of described comparator;

Linear ramp generator, the output of described linear ramp generator is connected to the said in-phase input end of described comparator;

Latch, described latch comprises control input end and latch data input, the output of described comparator is connected to the described control input end of described latch;

The nonlinear compensation counter, the enumeration data output of described nonlinear compensation counter is connected to the described latch data input of described latch;

Described nonlinear compensation counter arrives described latch to not waiting cycle counting clock sequence to count also output count data;

The wherein said cycle counting clock sequence that do not wait comprises at least two counting clock subsequences, and wherein the counting clock cycle at least one counting clock subsequence different from the counting clock cycle in all the other counting clock subsequences.

2. analog to digital converter as claimed in claim 1, is characterized in that, described nonlinear compensation counter comprises:

Fundamental clock;

Do not wait the cycle clock generator, the output of described fundamental clock is connected to the described input that does not wait the cycle clock generator, and the described clock signal that does not wait the cycle clock generator to provide according to described fundamental clock generates the described cycle counting clock sequence that do not wait;

Counter, the described output that does not wait the cycle clock generator is connected to the counting clock input of described counter, and the output of described counter is the enumeration data output of described nonlinear compensation counter;

Wherein said counter is counted the described cycle counting clock sequence that do not wait.

3. as claim 1 or 2 described analog to digital converters, it is characterized in that:

The described cycle counting clock sequence that do not wait comprises an initial clock subsequence and at least two counting clock subsequences.

4. analog to digital converter as described as any one in claims 1 to 3 is characterized in that:

Clock signal in described initial clock subsequence remains low level.

5. analog to digital converter as described as any one in claims 1 to 3 is characterized in that:

The described cycle counting clock sequence that do not wait comprises m counting clock subsequence, wherein , expression rounds up, and M is for meeting minimum value, be wherein controlling elements, ψ _ifor i straightway of the function relation curve between the comparison time of the output of the numeral of the described latch of linear approximation and described comparator, the numeral that ψ is described latch is exported and the function relation curve between comparison time of described comparator,

the norm that means i time period inner function.

6. analog to digital converter as described as any one in claims 1 to 3 is characterized in that:

The number of the counting clock in each described counting clock subsequence is identical.

7. an infrared focal plane array, comprise reading circuit, it is characterized in that: described reading circuit comprises the described analog to digital converter of any one in claim 1 to 6.

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