CN103441125A - Surge protection circuit based on bidirectional thyristor and method for manufacturing same - Google Patents

Abstract

The invention relates to electronic circuit and semiconductor technologies, in particular to a surge protection circuit based on a bidirectional thyristor. The surge protection circuit based on the bidirectional thyristor is characterized by comprising the bidirectional thyristor, an NPN-type triode and a PNP-type triode. The emitting electrode of the NPN-type triode is connected with a P-type door of the bidirectional thyristor, and the base electrode of the NPN-type triode leads to a first electrode; the emitting electrode of the PNP-type triode is connected with a N-type door of the bidirectional thyristor, and the base electrode of the PNP-type triode leads to a second electrode; one end of the bidirectional thyristor leads to a third electrode, and the other end of the bidirectional thyristor, the collector electrode of the NPN-type triode and the collector electrode of the PNP-type triode are grounded. The surge protection circuit based on the bidirectional thyristor has the advantages of being capable of protecting bidirectional and programmable surge of a single circuit, greatly reducing chip area and reducing production cost.

Description

A kind of surge protection circuit based on bidirectional thyristor and its manufacturing method

technical field

The invention relates to electronic circuits and semiconductor technologies, in particular to a surge protection circuit based on bidirectional thyristors. the

Background technique

Electronic circuits are often impacted by surge currents caused by voltage transients during use, which will adversely affect the normal operation of the entire circuit and even cause damage to the electronic circuit system. The main sources of surges are: inductive load voltage transients, electrostatic discharges, lightning discharges, and discharges within or between clouds. In order to prevent the impact of the transient surge voltage on the entire circuit system and improve the reliability of the electronic system, surge protection has become a problem that must be considered in modern electronic circuits. The thyristor type surge protection circuit has the superior performance of precise conduction, infinite repetition, wide voltage range (several volts to thousands of volts) and fast response (ns level), so it is widely used in the field of power electronics technology, communication field and various Protection of electronic circuits. the

Common thyristor-type surge protection circuits are shown in Figure 1 and Figure 2. Figure 1 is a bidirectional two-wire programmable surge protection circuit. This circuit structure can set the voltage value of electrode G1 and electrode G2 to set the surge protection circuit. Surge protection range, when a positive (negative) surge occurs at the Line end, the pnp (npn) transistor is turned on, and the emitter current of the triode triggers the thyristor to turn on, thereby discharging the surge current and realizing surge protection for the line; Figure 2 shows a dual-way bidirectional programmable surge protection circuit. When in use, this circuit is connected in parallel at both ends of the circuit to be protected. When K1 and K2 have a positive overvoltage greater than about 0.7V, the diode conducts, and K1, K2 The voltage of the K2 electrode is clamped at 0.7V, and the surge current is released at the same time; when K1 and K2 have a negative overvoltage about 0.7V lower than the G terminal voltage, the npn transistor is turned on, and its emitter current triggers the p-type The gate thyristor is turned on to discharge the surge current, and the voltage range of the negative surge protection can be set by programming the voltage value of the G electrode. Therefore, in order to ensure a sufficiently large surge current discharge capability in the existing protection circuit, there is a problem that the chip area of the surge protection circuit is large, which is not conducive to the current demand for circuit miniaturization and economy. the

Contents of the invention

The technical problem to be solved by the present invention is to propose a bidirectional thyristor-based surge protection circuit and a manufacturing method thereof for the problem that the chip area of the current surge protection circuit is relatively large. the

The technical solution adopted by the present invention to solve the above technical problems is: a surge protection circuit based on a bidirectional thyristor, which is characterized in that it includes a bidirectional thyristor, an NPN triode and a PNP triode, and the emitter of the NPN triode and the bidirectional The P-type gate of the thyristor is connected, the base leads to the first electrode, the emitter of the PNP-type triode is connected to the N-type gate of the bidirectional thyristor, and the base leads to the second electrode, one end of the bidirectional thyristor leads to the third electrode, and the other One end is grounded to the collector of the NPN transistor and the collector of the PNP transistor. the

Specifically, the bidirectional thyristor includes a first N-type semiconductor substrate 3, one end of the first N-type semiconductor substrate 3 is provided with a first P well 4 and an N-type diffusion ring 5, and the N-type diffusion ring 5 It is a pair and is respectively arranged on both sides of the first P well 4, a first N well 7 and a P-type gate 6 are formed in the first P well 4, and the P-type gate 6 is arranged on the first N well 7 On the left side of the first N well 7, a second P well 9 and an N-type gate 8 are formed, and the N-type gate 8 is arranged on the right side of the second P well 9, and the second P well 9 The short-circuit hole 10 is formed by N-type implantation, the surface of the second P well 9 leads to the third electrode 2, and the other end of the first N-type semiconductor substrate 3 is provided with a plurality of alternate first P regions 11 and the first P well. - N zone 12. the

Specifically, the NPN transistor includes a second N-type semiconductor substrate 13, and one end of the second N-type semiconductor substrate 13 is provided with a third P well 14, and the third P well 14 includes a first emitter region 15 and the first base region 16, the first emitter region 15 is connected to the P-type gate 6, the first base region 16 leads to the first electrode 17, and the other end of the second N-type semiconductor substrate 13 passes through N-type diffusion forms the first collector region 19, and the second N-type semiconductor substrate 13 also includes a second P region 18, and the second P region 18 connects one end and the other end of the second N-type semiconductor substrate 13 . the

Specifically, the PNP transistor includes a third N-type semiconductor substrate 20, and one end of the third N-type semiconductor substrate 20 is provided with a fourth P well 21, and the fourth P well 21 is a second emitter region. , connected to the N-type gate 8, the right side of the fourth P well forms a second base region 22 through N-type diffusion, the second base region 22 leads to the second electrode 25, and the third N-type semiconductor lining The other end of the bottom 20 forms a second collector region 23 through P-type diffusion. The third N-type semiconductor substrate 20 also includes a third P region 24, and the third P region 24 is connected to the third N-type semiconductor substrate. One end of 20 is separated from the other end, the first electrode 17 , the third electrode 2 and the second electrode 25 by an oxide layer 1 . the

A method for manufacturing a surge protection circuit based on a bidirectional thyristor, characterized in that it comprises:

Step 1: Select a monocrystalline silicon wafer with a thickness of 300 μm and a resistivity of 15-25 Ω cm, mark, clean and dry it for use;

The second step: the single crystal silicon wafer obtained in the first step is subjected to the surface growth field oxide layer treatment of the silicon wafer, and the first photolithography is performed, specifically the double sides of the second P region 18 and the third P region 24 of the isolation region Photolithography, followed by boron diffusion, boron-aluminum dual diffusion or gallium-aluminum dual diffusion in double-sided isolation regions;

Step 3: Carry out the second photolithography and three photolithography, and then perform boron diffusion in the first P well 4 and the first P region 11. The diffusion conditions are: pre-deposition temperature 1050°C-1060°C, time 5h, redistribution Temperature 1250°C, time 20h~25h, O ₂ flow rate 700mL/min, N ₂ flow rate 300mL/min;

Step 4: Carry out the fourth photolithography _{, and} then carry out 7-phosphorus diffusion in the first N well. 2~3h, redistribution conditions are temperature 1300℃~1310℃, time 18h~20h, O ₂ flow rate 500mL/min, N ₂ flow rate 700mL/min;

Step 5: Carry out the fifth photolithography, and then perform boron ion implantation in the second P well 9, NPN transistor base region 14, and PNP transistor emitter region 21. The ion implantation conditions are: dose 5e14cm ^-2 , energy 80KeV, and redistribution conditions The temperature is 1250°C, the time is 10h~15h, the flow rate of O ₂ is 700mL/min, and the flow rate of N ₂ is 300mL/min;

Step 6: Carry out the sixth photolithography, and then perform 10N-type ion implantation in the gate short-circuit hole. The ion implantation conditions are: dose 1e15cm ^-2 , energy 50KeV, and redistribution conditions are temperature 1310°C, time 8h-12h, O ₂ The flow rate is 700mL/min, and the _N2 flow rate is 300mL/min;

Step 7: Carry out the seventh photolithography, carry out the contact photolithography of the front P-type gate 6 area, the NPN triode base area 16, carry out the eighth photolithography, carry out the photolithography of the second collector area 23 on the back of the PNP triode, and carry out Boron ion implantation, implantation conditions: dose 5e14cm ^-2 , energy 50KeV, redistribution conditions: temperature 1250°C, time 2h-4h, O ₂ flow rate 700mL/min, N ₂ flow rate 300mL/min;

Step 8: Carry out the ninth photolithography, carry out the front N-type gate 8 regions, the PNP transistor base region 22 contacts, the N-type diffusion ring 5 photolithography, carry out the tenth photolithography, and carry out the first N region 12 photolithography , perform phosphorus ion implantation, implantation conditions are: dose 5e15cm ^-2 , energy 60KeV, redistribution conditions are temperature 1310°C, time 3h-5h, O ₂ flow rate 500mL/min, N ₂ flow rate 700mL/min;

Step 9: Carry out the eleventh photolithography to etch out the contact holes;

Step 10: Carry out metal evaporation, twelfth photolithography and reverse etching of aluminum;

The eleventh step: alloy, conditions: furnace temperature 550°C, vacuum degree 10 ^-3 Pa, time 10-30min, passivation;

The twelfth step: Carry out the thirteenth photolithography to etch out the solder joints;

The thirteenth step: low temperature annealing, temperature 500 ℃ ~ 510 ℃, constant temperature 10min;

Step 14: Preliminary testing of silicon wafers, cutting, racking, sintering, packaging and testing. the

Specifically, gallium-aluminum dual-mass diffusion is carried out after the photolithography described in the second step, which specifically includes the following steps:

，预烘后将硅片推入扩散炉恒温区，在1300℃～1310℃、N2保护下预淀积8h～10h，  a. Evenly coat the silicon dioxide latex source prepared by aluminum nitrate on both sides of the silicon wafer, the thickness

, after pre-baking, push the silicon wafer into the constant temperature zone of the diffusion furnace, and pre-deposit at 1300 ℃ ~ 1310 ℃ under the protection of N2 for 8h ~ 10h,

b. Carry out Ga pre-deposition, the Ga source is Ga ₂ O ₃ powder, the deposition conditions are: sheet temperature 1250°C-1260°C, source temperature 980°C-1000°C, H ₂ flow rate 200-300mL/min, N ₂ The flow rate is 80-100mL/min, and the power-on time is 60-80min;

c. Perform impurity redistribution at 1330°C under the protection of N ₂ for 50-55 hours, and take out the silicon wafer at below 400°C.

The beneficial effect of the invention is that the bidirectional programmable surge protection for a single line can be realized, and at the same time, the chip area can be greatly reduced, thereby reducing the production cost. the

Description of drawings

Figure 1 is a schematic diagram of a common thyristor-based surge protection circuit;

Figure 2 is a schematic structural diagram of another common thyristor-based surge protection circuit;

Fig. 3 is the equivalent structure schematic diagram of the surge protection circuit based on bidirectional thyristor of the present invention;

Fig. 4 is the sectional schematic view of the surge protection circuit based on bidirectional thyristor of the present invention;

Fig. 5 is a schematic diagram of a photolithography mask plate of the surge protection circuit manufacturing method of the present invention;

Fig. 6 is a schematic diagram of a secondary photolithography mask of the surge protection circuit manufacturing method of the present invention;

Fig. 7 is a schematic diagram of three photolithography mask plates of the surge protection circuit manufacturing method of the present invention;

Figure 8 is a schematic diagram of four photolithography mask plates of the surge protection circuit manufacturing method of the present invention;

9 is a schematic diagram of five photolithography mask plates of the surge protection circuit manufacturing method of the present invention;

Fig. 10 is a schematic diagram of six photolithographic mask plates of the surge protection circuit manufacturing method of the present invention;

Fig. 11 is a schematic diagram of seven photolithography mask plates of the surge protection circuit manufacturing method of the present invention;

Fig. 12 is a schematic diagram of eight photolithography mask plates of the surge protection circuit manufacturing method of the present invention;

Fig. 13 is a schematic diagram of nine photolithography mask plates of the surge protection circuit manufacturing method of the present invention;

Fig. 14 is a schematic diagram of ten photolithography mask plates of the surge protection circuit manufacturing method of the present invention;

Fig. 15 is a schematic diagram of eleven photolithography mask plates of the surge protection circuit manufacturing method of the present invention;

FIG. 16 is a schematic diagram of a twelve-pass photolithography mask of the surge protection circuit manufacturing method of the present invention. the

Detailed ways

Below in conjunction with accompanying drawing and embodiment, describe technical scheme of the present invention in detail:

The bidirectional thyristor has two kinds of gates, and three electrodes are drawn out to the outside, which is equivalent to the antiparallel connection of two unidirectional thyristors. As long as a trigger pulse is added to the gate of the thyristor, no matter what the polarity of the pulse is, it can be used. The bidirectional thyristor turns on. the

As shown in Figure 1, it is the equivalent circuit schematic diagram of the surge protection circuit based on the thyristor of the present invention, including bidirectional thyristor, NPN type triode and PNP type triode, the emitter of NPN type triode and the P type gate connection of bidirectional thyristor, The base leads to the first electrode G1, the emitter of the PNP triode is connected to the N-type gate of the bidirectional thyristor, and the base leads to the second electrode G2, one end of the bidirectional thyristor leads to the third electrode Line, and the other end is connected to the NPN triode. Both the collector and the collector of the PNP transistor are grounded, and the P-type gate and N-type gate of the bidirectional thyristor are respectively connected to the emitters of the NPN transistor and the PNP transistor. According to the characteristics of the bidirectional thyristor, by controlling the on-off of the triode The conduction direction of the bidirectional thyristor can be controlled so that the bidirectional surge current can be discharged. the

The working principle of the present invention is: add a set negative bias voltage to the first electrode G1 end, add a set positive bias voltage to the second electrode G2 end, if the third electrode Line end appears negative Surge current, when the voltage difference between the first electrode G1 and the third electrode Line terminal is greater than about 0.7V, the NPN triode will be turned on, and its emitter current will be used as the P-type gate current of the bidirectional thyristor to trigger the thyristor to turn on, and the surge will be turned on. The current is discharged to the ground, thus realizing the surge protection for the user line; when the third electrode Line terminal has a positive surge current, and the voltage difference between the third electrode Line terminal and the second electrode G2 is greater than about 0.7V , the PNP triode is turned on, and its emitter current is used as the N-type gate current of the bidirectional thyristor to trigger the thyristor to turn on. After the thyristor is turned on, it has the ability to discharge the surge current, so that the back-end electronic circuit is free from the impact of the surge. ; There is no surge or after the surge, the thyristor current will be less than its maintenance current, the thyristor will be in the off state, and there is only a small leakage current, which will not affect the normal operation of the back-end electronic circuit. The present invention can realize the surge protection of subscriber lines relatively easily, and if it is necessary to perform surge protection for multiple subscriber lines, it only needs to use multiple circuit chips of the present invention at the same time. the

As shown in Figure 4, it is a schematic cross-sectional view of a surge protection circuit based on a bidirectional thyristor according to the present invention, wherein the bidirectional thyristor includes a first N-type semiconductor substrate 3, and one end of the first N-type semiconductor substrate 3 is provided with The first P well 4 and the N-type diffusion ring 5, the N-type diffusion ring 5 is a pair and is respectively arranged on both sides of the first P well 4, and the first P well 4 includes the first N well 7 and the P-type Gate 6, the P-type gate 6 is arranged on the left side of the first N well 7, the first N well 7 includes a second P well 9 and an N-type gate 8, and the N-type gate 8 is set On the right side of the second P well 9, a short hole 10 is formed by N-type implantation in the second P well 9, and the third electrode 2 is drawn from the surface of the second P well 9, and the first N-type semiconductor substrate The other end of 3 is provided with a plurality of alternate first P regions 11 and first N regions 12 . The NPN transistor includes a second N-type semiconductor substrate 13, and one end of the second N-type semiconductor substrate 13 is provided with a third P well 14, and the third P well 14 includes a first emitter region 15 and a first base region 16, the first emitter region 15 is connected to the P-type gate 6, the first base region 16 leads to the first electrode 17, and the other end of the second N-type semiconductor substrate 13 is formed by N-type diffusion. A collector region 19 , the second N-type semiconductor substrate 13 further includes a second P region 18 , and the second P region 18 connects one end and the other end of the second N-type semiconductor substrate 13 . PNP type transistor comprises the 3rd N-type semiconductor substrate 20, and one end of described 3rd N-type semiconductor substrate 20 is provided with the 4th P well 21, and described 4th P well 21 is the second emitter region, and N-type gate The right side of the fourth P well forms a second base region 22 through N-type diffusion, and the second base region 22 leads to a second electrode 25. The other end of the third N-type semiconductor substrate 20 The second collector region 23 is formed by P-type diffusion, and the third N-type semiconductor substrate 20 also includes a third P region 24, and the third P region 24 connects one end of the third N-type semiconductor substrate 20 to the other end. At one end, the first electrode 17 , the third electrode 2 and the second electrode 25 are separated by the oxide layer 1 . It can be seen that compared with the traditional structure using two single-gate thyristors, the new structure is more compact and the chip area is smaller, and the surge discharge capability of the protection circuit can be greatly improved after the optimized design. the

The substrate in this circuit can be an N-type substrate or a P-type substrate. In addition to triodes, devices such as MOSFETs, SCRs, diodes, and SITs can also be used to control the conduction of bidirectional thyristors. the

The present invention also provides a manufacturing method of a surge protection circuit based on bidirectional thyristors, the main process steps include:

Step 1: Select a monocrystalline silicon wafer with a thickness of about 300 μm, a resistivity of 15-25Ω·cm and fewer defects, mark, clean and dry it before use;

The second step: the single crystal silicon wafer obtained in the first step is subjected to the surface growth field oxide layer treatment of the silicon wafer, and the first photolithography is performed, specifically the double sides of the second P region 18 and the third P region 24 of the isolation region Photolithography, the mask pattern is shown in Figure 5 (front and back), and then perform boron diffusion, boron-aluminum dual diffusion or gallium-aluminum dual diffusion in double-sided isolation regions;

The third step: carry out the second photolithography, the pattern of the mask plate is as shown in Figure 6, carry out three photolithography, the pattern of the mask plate is shown in Figure 7, and then carry out boron diffusion in the first P well 4 and the first P region 11, Diffusion conditions are: pre-deposition temperature 1050°C-1060°C, time 5h, redistribution temperature 1250°C, time 20h-25h, O ₂ flow rate 700mL/min, N ₂ flow rate 300mL/min;

The fourth step: carry out the fourth photolithography, the pattern of the mask plate is shown in Figure 8, and then carry out the first N well 7 phosphorus diffusion, the conditions are: pre-deposition temperature 980 ° C ~ 1020 ° C, O ₂ flow rate 200 mL/min, The flow of N ₂ is 700mL/min, the time is 2~3h, the redistribution conditions are temperature 1300℃~1310℃, time 18h~20h, the flow of O ₂ is 500mL/min, and the flow of N ₂ is 700mL/min;

Step 5: Carry out the fifth photolithography, the pattern of the mask plate is shown in Figure 9, and then perform boron ion implantation in the second P well 9, NPN transistor base region 14, and PNP transistor emitter region 21, and the ion implantation conditions are: dose 5e14cm ^-2 . Energy 80KeV, redistribution conditions are temperature 1250℃, time 10h~15h, O ₂ flow rate 700mL/min, N ₂ flow rate 300mL/min;

Step 6: Carry out the sixth photolithography, the pattern of the mask plate is shown in Figure 10, and then perform 10N type ion implantation of the gate short hole, the ion implantation conditions are: dose 1e15cm ^-2 , energy 50KeV, redistribution condition is temperature 1310 ℃, time 8h～12h, O ₂ flow rate is 700mL/min, N ₂ flow rate is 300mL/min;

The seventh step: carry out the seventh photolithography, carry out the contact photolithography of the front P-type gate 6 area, the NPN transistor base area 16, the mask pattern is shown in Figure 11, carry out the eighth photolithography, and carry out the PNP transistor backside 16 The second collector area 23 is photolithography, the mask pattern is shown in Figure 12, boron ion implantation is carried out, the implantation conditions are: dose 5e14cm ^-2 , energy 50KeV, redistribution conditions are temperature 1250°C, time 2h~4h, O ₂ flow 700mL/min, N ₂ flow rate is 300mL/min;

Step 8: Carry out the ninth photolithography, carry out the front N-type gate 8 regions, the PNP transistor base region 22 contacts, and the N-type diffusion ring 5 photolithography, the mask pattern is shown in Figure 13, and perform the tenth photolithography , carry out photolithography of the first N region 12, the mask pattern is as shown in Figure 14, carry out phosphorus ion implantation, the implantation conditions are: dose 5e15cm ^-2 , energy 60KeV, redistribution conditions are temperature 1310°C, time 3h-5h, O ₂ flow rate is 500mL/min, N ₂ flow rate is 700mL/min;

Step 9: Carry out the eleventh photolithography, etch out the contact holes, and the mask pattern is shown in Figure 15;

Step 10: Carry out metal evaporation, twelfth photolithography and anti-etching of aluminum, the mask pattern is shown in Figure 16;

The eleventh step: alloy, conditions: furnace temperature 550°C, vacuum degree 10 ^-3 Pa, time 10-30min, passivation;

The twelfth step: Carry out the thirteenth photolithography to etch out the solder joints;

The thirteenth step: low temperature annealing, temperature 500 ℃ ~ 510 ℃, constant temperature 10min;

Step 14: Preliminary testing of silicon wafers, cutting, racking, sintering, packaging and testing. the

When performing gallium-aluminum dual-mass diffusion after photolithography in the second step, it specifically includes the following steps:

，预烘后将硅片推入扩散炉恒温区，在1300℃～1310℃、N2保护下预淀积8h～10h，  a. Evenly coat the silicon dioxide latex source prepared by aluminum nitrate on both sides of the silicon wafer, the thickness

, after pre-baking, push the silicon wafer into the constant temperature zone of the diffusion furnace, and pre-deposit at 1300 ℃ ~ 1310 ℃ under the protection of N2 for 8h ~ 10h,

b. Carry out Ga pre-deposition, the Ga source is Ga ₂ O ₃ powder, the deposition conditions are: sheet temperature 1250°C-1260°C, source temperature 980°C-1000°C, H ₂ flow rate 200-300mL/min, N ₂ The flow rate is 80-100mL/min, and the power-on time is 60-80min;

c. Perform impurity redistribution at 1330°C under the protection of N ₂ for 50-55 hours, and take out the silicon wafer at below 400°C.

Claims (6)

1. A surge protection circuit based on bidirectional thyristor, characterized in that, comprises bidirectional thyristor, NPN type triode and PNP type triode, the emitter of said NPN type triode is connected with the P-type gate of bidirectional thyristor, and the base draws the first One electrode, the emitter of the PNP triode is connected to the N-type gate of the bidirectional thyristor, the base leads to the second electrode, one end of the bidirectional thyristor leads to the third electrode, and the other end is connected to the collector of the NPN triode and the PNP type The collectors of the transistors are grounded. 2. A surge protection circuit based on a bidirectional thyristor according to claim 1, characterized in that, the bidirectional thyristor comprises a first N-type semiconductor substrate (3), and the first N-type semiconductor substrate ( 3) is provided with a first P well (4) and an N-type diffusion ring (5) at one end, the N-type diffusion rings (5) are a pair and are respectively arranged on both sides of the first P well (4), the A first N well (7) and a P-type gate (6) are formed in the first P well (4), the P-type gate (6) is arranged on the left side of the first N well (7), and the first A second P well (9) and an N-type gate (8) are formed in an N well (7), and the N-type gate (8) is arranged on the right side of the second P well (9), and the second A short-circuit hole (10) is formed in the P well (9) by N-type implantation, the surface of the second P well (9) leads to the third electrode (2), and the other end of the first N-type semiconductor substrate (3) A plurality of alternate first P regions (11) and first N regions (12) are provided. 3. A surge protection circuit based on a bidirectional thyristor according to claim 2, characterized in that, the NPN-type transistor comprises a second N-type semiconductor substrate (13), and the second N-type semiconductor substrate One end of (13) is provided with a third P well (14), the third P well (14) includes a first emitter region (15) and a first base region (16), and the first emitter region (15) It is connected to the P-type gate (6), the first base region (16) leads to the first electrode (17), and the other end of the second N-type semiconductor substrate (13) forms a first collection through N-type diffusion. An electrode region (19), the second N-type semiconductor substrate (13) further includes a second P region (18), and the second P region (18) is connected to one end of the second N-type semiconductor substrate (13) and the other end. 4. A surge protection circuit based on a bidirectional thyristor according to claim 3, characterized in that, the PNP transistor comprises a third N-type semiconductor substrate (20), and the third N-type semiconductor substrate One end of (20) is provided with a fourth P well (21), the fourth P well (21) is the second emitter region, connected to the N-type gate (8), and the right side of the fourth P well passes through N-type diffusion forms a second base region (22), the second base region (22) leads to a second electrode (25), and the other end of the third N-type semiconductor substrate (20) forms a second base region (22) through P-type diffusion. Two collector regions (23), the third N-type semiconductor substrate (20) further includes a third P region (24), and the third P region (24) is connected to the third N-type semiconductor substrate (20) One end and the other end, the first electrode (17), the third electrode (2) and the second electrode (25) are separated by an oxide layer (1). 5. A method for manufacturing a surge protection circuit based on a bidirectional thyristor, characterized in that it comprises: Step 1: Select a monocrystalline silicon wafer with a thickness of 300 μm and a resistivity of 15-25 Ω·cm, mark it, clean it, and dry it before use; The second step: the single crystal silicon wafer obtained in the first step is treated with a field oxide layer on the surface of the silicon wafer, and the first photolithography is performed, specifically the second P area (18) and the third P area (24) of the isolation area. ), followed by boron diffusion, boron-aluminum dual diffusion or gallium-aluminum dual diffusion in double-sided isolation regions; Step 3: Carry out the second photolithography and three photolithography, and then perform boron diffusion in the first P well (4) and the first P region (11). The diffusion conditions are: pre-deposition temperature 1050°C-1060°C, time 5h, redistribution temperature 1250℃, time 20h~25h, O ₂ flow rate 700mL/min, N ₂ flow rate 300mL/min; Step 4: Carry out the fourth photolithography, and then carry out phosphorus diffusion in the first N well (7), the conditions are: pre-deposition temperature 980°C ~ 1020°C, O ₂ flow rate 200mL/min, N ₂ flow rate 700mL/min , time 2~3h, redistribution conditions are temperature 1300℃~1310℃, time 18h~20h, O ₂ flow rate 500mL/min, N ₂ flow rate 700mL/min; Step 5: Carry out the fifth photolithography, and then perform boron ion implantation in the second P well (9), NPN triode base region (14), PNP triode emitter region (21). The ion implantation conditions are: dose 5e14cm ^-2 , Energy 80KeV, redistribution conditions are temperature 1250°C, time 10h~15h, O ₂ flow rate 700mL/min, N ₂ flow rate 300mL/min; Step 6: Carry out the sixth photolithography, and then perform N-type ion implantation in the gate short hole (10). The ion implantation conditions are: dose 1e15cm ^-2 , energy 50KeV, redistribution conditions are temperature 1310°C, time 8h-12h , O ₂ flow rate is 700mL/min, N ₂ flow rate is 300mL/min; Step 7: Carry out the seventh photolithography, carry out the contact photolithography of the front P-type gate (6) area and the NPN triode base area (16), carry out the eighth photolithography, and perform the second collector area on the back of the PNP triode ( 23) Photolithography, boron ion implantation, implantation conditions: dose 5e14cm ^-2 , energy 50KeV, redistribution conditions: temperature 1250°C, time 2h-4h, O ₂ flow rate 700mL/min, N ₂ flow rate 300mL/min ; Step 8: Carry out the ninth photolithography, carry out the front N-type gate (8) region, the PNP transistor base region (22) contact, N-type diffusion ring (5) photolithography, carry out the tenth photolithography, and carry out the first Phosphorus ion implantation is carried out in the N region (12), the implantation conditions are: dose 5e15cm ^-2 , energy 60KeV, redistribution conditions are temperature 1310°C, time 3h~5h, O ₂ flow rate 500mL/min, N ₂ flow rate 700mL/min; Step 9: Carry out the eleventh photolithography to etch the contact holes; Step 10: Carry out metal evaporation, twelfth photolithography and reverse etching of aluminum; The eleventh step: alloy, conditions: furnace temperature 550°C, vacuum degree 10 ^-3 Pa, time 10-30min, passivation; Step 12: Carry out the thirteenth photolithography to etch out the pads; The thirteenth step: low temperature annealing, the temperature is 500 ℃ ~ 510 ℃, constant temperature for 10 minutes; Step 14: Preliminary testing of silicon wafers, cutting, racking, sintering, packaging and testing. 6. A method for manufacturing a surge protection circuit based on a triac according to claim 5, wherein the photolithography in the second step is followed by gallium-aluminum dual-mass diffusion, specifically comprising the following steps: a. Evenly coat the silicon dioxide latex source prepared by aluminum nitrate on both sides of the silicon wafer, the thickness

After pre-baking, the silicon wafer is pushed into the constant temperature zone of the diffusion furnace, and pre-deposited at 1300 ° C ~ 1310 ° C under the protection of N2 for 8 h ~ 10 h, b. Carry out Ga pre-deposition, the Ga source is Ga ₂ O ₃ powder, the deposition conditions are: sheet temperature 1250°C-1260°C, source temperature 980°C-1000°C, H ₂ flow rate 200-300mL/min, N ₂ The flow rate is 80-100mL/min, and the power-on time is 60-80min; c. Perform impurity redistribution at 1330°C under the protection of N ₂ for 50-55 hours, and take out the silicon wafer at below 400°C.

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