[go: up one dir, main page]

CN103441078B - First it is honored as a queen and loses three-dimensional systematic chip formal dress stack package structure and process - Google Patents

First it is honored as a queen and loses three-dimensional systematic chip formal dress stack package structure and process Download PDF

Info

Publication number
CN103441078B
CN103441078B CN201310340418.2A CN201310340418A CN103441078B CN 103441078 B CN103441078 B CN 103441078B CN 201310340418 A CN201310340418 A CN 201310340418A CN 103441078 B CN103441078 B CN 103441078B
Authority
CN
China
Prior art keywords
photoresist film
metal substrate
metal
conductive
remove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310340418.2A
Other languages
Chinese (zh)
Other versions
CN103441078A (en
Inventor
梁志忠
王亚琴
王孙艳
林煜斌
廖小景
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangyin Xinzhilian Electronics Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangyin Xinzhilian Electronics Technology Co ltd filed Critical Jiangyin Xinzhilian Electronics Technology Co ltd
Priority to CN201310340418.2A priority Critical patent/CN103441078B/en
Publication of CN103441078A publication Critical patent/CN103441078A/en
Application granted granted Critical
Publication of CN103441078B publication Critical patent/CN103441078B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明涉及一种先封后蚀三维系统级芯片正装堆叠封装结构及工艺方法,它包括基岛(1)和引脚(2),所述引脚(2)正面设置有导电柱子(3),所述基岛(1)正面通过导电或不导电粘结物质(6)正装有芯片(4),所述芯片(4)正面与引脚(2)正面之间通过金属线(5)相连接,所述基岛(1)和引脚(2)正面的区域以及导电柱子(3)、芯片(4)和金属线(5)外围的区域均包封有塑封料或环氧树脂(7),所述基岛(1)、引脚(2)和导电柱子(3)露出塑封料或环氧树脂(7)的表面设置有抗氧化层(8),所述导电柱子(3)顶部通过导电物质(9)堆叠有封装体(10)。本发明的有益效果是:它能够解决传统基板封装堆叠由于底层基板焊盘低于底层塑封面而造成的封装体间互联焊球质量难以控制的问题。

The invention relates to a three-dimensional system-level chip stacked package structure and process method that is sealed first and etched later. It includes a base island (1) and pins (2), and conductive pillars (3) are arranged on the front of the pins (2) , the front side of the base island (1) is equipped with a chip (4) through a conductive or non-conductive adhesive substance (6), and the front side of the chip (4) is connected to the front side of the pin (2) through a metal wire (5) connection, the area on the front of the base island (1) and the pin (2) and the area around the conductive pillar (3), the chip (4) and the metal wire (5) are encapsulated with plastic encapsulant or epoxy resin (7 ), the surface of the base island (1), pins (2) and conductive pillars (3) exposed to the molding compound or epoxy resin (7) is provided with an anti-oxidation layer (8), and the top of the conductive pillars (3) Packages (10) are stacked through the conductive substance (9). The beneficial effect of the invention is that it can solve the problem that the quality of interconnection solder balls between packages is difficult to control due to the fact that the solder pads of the bottom substrate are lower than the plastic surface of the bottom layer in traditional substrate package stacking.

Description

先封后蚀三维系统级芯片正装堆叠封装结构及工艺方法Seal-before-etch three-dimensional system-on-chip front-mount package structure and process method

技术领域 technical field

本发明涉及一种先封后蚀三维系统级芯片正装堆叠封装结构及工艺方法,属于半导体封装技术领域。 The invention relates to a three-dimensional system-level chip front-mount stack packaging structure and a process method after sealing first and etching later, and belongs to the technical field of semiconductor packaging.

背景技术 Background technique

传统常见的PoP封装体堆叠结构即底层逻辑器件基板封装上堆叠顶层存储器件基板封装,底层器件与顶层器件之间通过焊球的贴装、回流焊实现两个封装体的堆叠与电性互联(如图80所示)。 The traditional common PoP package stacking structure is that the bottom logic device substrate package is stacked with the top layer storage device substrate package, and the bottom layer device and the top layer device are stacked and electrically interconnected by solder ball mounting and reflow soldering ( as shown in Figure 80).

上述PoP(封装体堆叠封装体)封装结构存在以下不足: The above PoP (Package on Package) packaging structure has the following disadvantages:

1、底层封装体与顶层封装体互联的焊盘位于底层封装体的基板上,低于底层封装体的塑封面,所以底部封装体的模塑高度受限于顶部封装体底面的金属锡球尺寸与高度,从而限制底层封装体内部芯片堆叠的层数。相应地,顶层封装体外脚也不能植入单颗小尺寸焊球,否则顶层封装体的焊球高度过小而无法与底层封装体的焊盘实现互联,(如图81所示)。 1. The pads connecting the bottom package and the top package are located on the substrate of the bottom package, which is lower than the plastic cover of the bottom package, so the molding height of the bottom package is limited by the size of the metal solder ball on the bottom surface of the top package and height, thereby limiting the number of layers of chip stacking inside the bottom package. Correspondingly, a single small-sized solder ball cannot be implanted in the outer pin of the top package, otherwise the solder ball height of the top package is too small to be interconnected with the pad of the bottom package (as shown in Figure 81).

2、底部封装体与顶部封装体之间通过顶层封装体外脚的金属锡球互联,回流焊后金属锡球会产生热变形,顶层封装焊球间距会比回流焊前小,如图82,为避免焊球间的短路,所以不能采用顶层封装为Fine Pitch(细间距)的封装堆叠。 2. The bottom package and the top package are interconnected through the metal solder balls on the outer legs of the top package. After reflow soldering, the metal solder balls will be thermally deformed, and the distance between the top package solder balls will be smaller than before reflow soldering, as shown in Figure 82. To avoid short circuits between solder balls, it is not possible to use a package stack with a top package of Fine Pitch (fine pitch).

3、基板封装体堆叠如果为减小球间距采用多颗小金属锡球堆叠进行互联,在贴装堆叠的过程中对位困难,容易造成精度偏差(如图83)或是上球体滑落,影响贴装良率 3. If the substrate package is stacked to reduce the ball pitch by stacking multiple small metal tin balls for interconnection, it will be difficult to align during the mounting and stacking process, which will easily cause accuracy deviation (as shown in Figure 83) or the upper ball will slip, affecting Mounting yield

4、基板封装体堆叠采用多颗小金属锡球堆叠进行互联,经过回流焊,小金属锡球发生不同的热形变,容易造成锡球位移偏差甚至会造成短路。 4. Substrate packages are stacked with multiple small metal solder balls for interconnection. After reflow soldering, the small metal solder balls undergo different thermal deformations, which may easily cause displacement deviation of the solder balls or even cause a short circuit.

发明内容 Contents of the invention

本发明的目的在于克服上述不足,提供一种先封后蚀芯片正装三维系统级封装结构及工艺方法,它能够解决传统基板封装堆叠由于底层基板焊盘低于底层塑封面而造成的封装体间互联焊球质量难以控制的问题。 The purpose of the present invention is to overcome the above-mentioned shortcomings, and provide a three-dimensional system-in-package structure and process method for sealing first and then etching chips, which can solve the gap between packages caused by the traditional substrate package stacking due to the bottom substrate pad being lower than the bottom plastic cover. The problem that the quality of interconnection solder balls is difficult to control.

本发明的目的是这样实现的:一种先封后蚀三维系统级芯片正装堆叠封装结构的工艺方法,所述方法包括以下步骤: The object of the present invention is achieved in the following way: a process method for encapsulating first and then etching a three-dimensional system-on-chip stacked package structure, said method comprising the following steps:

步骤一、取金属基板 Step 1. Take the metal substrate

步骤二、金属基板表面预镀铜材 Step 2. Pre-plating copper on the surface of the metal substrate

在金属基板表面预镀一层铜材, Pre-plating a layer of copper on the surface of the metal substrate,

步骤三、贴光阻膜作业 Step 3: Paste the photoresist film

在步骤二完成预镀铜材的金属基板正面及背面分别贴上可进行曝光显影的光阻膜; In step 2, a photoresist film that can be exposed and developed is pasted on the front and back of the metal substrate of the pre-plated copper material;

步骤四、金属基板正面去除部分光阻膜 Step 4. Remove part of the photoresist film from the front of the metal substrate

利用曝光显影设备将步骤三完成贴光阻膜作业的金属基板正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板正面后续需要进行金属线路层电镀的区域; Use exposure and developing equipment to expose, develop and remove part of the graphic photoresist film on the front of the metal substrate that has completed the photoresist film pasting operation in step 3, so as to expose the area that needs to be electroplated on the metal circuit layer on the front of the metal substrate;

步骤五、电镀金属线路层 Step 5. Plating metal circuit layer

在步骤四中金属基板正面去除部分光阻膜的区域内电镀上金属线路层,金属线路层电镀完成后即在金属基板正面形成相应的基岛和引脚; Electroplate a metal circuit layer in the area where part of the photoresist film is removed from the front of the metal substrate in step 4. After the electroplating of the metal circuit layer is completed, corresponding base islands and pins are formed on the front of the metal substrate;

步骤六、贴光阻膜作业 Step 6. Paste photoresist film

在步骤五完成电镀金属线路层的金属基板正面贴上可进行曝光显影的光阻膜; In step 5, a photoresist film that can be exposed and developed is pasted on the front side of the metal substrate on which the electroplated metal circuit layer is completed;

步骤七、金属基板正面去除部分光阻膜 Step 7. Remove part of the photoresist film from the front of the metal substrate

利用曝光显影设备将步骤六完成贴光阻膜作业的金属基板正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板正面后续需要进行导电柱子电镀的区域; Use exposure and developing equipment to expose, develop and remove part of the patterned photoresist film on the front of the metal substrate that has completed the photoresist film pasting operation in step 6, so as to expose the area on the front of the metal substrate that needs to be electroplated with conductive pillars;

步骤八、电镀导电柱子 Step 8. Plating conductive pillars

在步骤七中金属基板正面去除部分光阻膜的区域内电镀上导电柱子; Electroplate conductive pillars in the area where part of the photoresist film is removed from the front of the metal substrate in step 7;

步骤九、去除光阻膜 Step 9. Remove the photoresist film

去除金属基板表面的光阻膜; Remove the photoresist film on the surface of the metal substrate;

步骤十、装片 Step ten, loading film

在步骤五形成的基岛正面涂覆导电或不导电粘结物质进行第一芯片的植入; Coating conductive or non-conductive bonding substances on the front side of the base island formed in step 5 to implant the first chip;

步骤十一、金属线键合 Step 11. Wire Bonding

在第一芯片正面与步骤五形成的引脚之间进行键合金属线作业; Carry out bonding wire operation between the front surface of the first chip and the pins formed in step five;

步骤十二、环氧树脂塑封 Step 12. Epoxy resin plastic sealing

在完成装片打线后的金属基板正面进行环氧树脂塑封保护; Epoxy resin plastic sealing protection is carried out on the front of the metal substrate after chip loading and wiring;

步骤十三、环氧树脂表面研磨 Step 13. Epoxy resin surface grinding

在步骤十二完成环氧树脂塑封后进行表面研磨; Surface grinding is carried out after completing the epoxy resin molding in step 12;

步骤十四、贴光阻膜作业 Step 14. Paste photoresist film

在步骤十三完成环氧树脂表面研磨后的金属基板正面和背面贴上可进行曝光显影的光阻膜; In step 13, a photoresist film that can be exposed and developed is pasted on the front and back of the metal substrate after the epoxy resin surface is ground;

步骤十五、金属基板背面去除部分光阻膜 Step 15. Remove part of the photoresist film on the back of the metal substrate

利用曝光显影设备将步骤十四完成贴光阻膜作业的金属基板背面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板背面后续需要进行蚀刻的区域; Use the exposure and development equipment to expose, develop and remove part of the graphic photoresist film on the back of the metal substrate that has been pasted with the photoresist film in step 14, so as to expose the area that needs to be etched later on the back of the metal substrate;

步骤十六、蚀刻 Step 16. Etching

在步骤十五中金属基板背面去除部分光阻膜的区域进行化学蚀刻; Perform chemical etching in the region where part of the photoresist film is removed on the back of the metal substrate in step fifteen;

步骤十七、去除光阻膜 Step seventeen, remove the photoresist film

去除金属基板表面的光阻膜; Remove the photoresist film on the surface of the metal substrate;

步骤十八、金属基板背面披覆绿漆或可感光的不导电胶材 Step 18. Cover the back of the metal substrate with green paint or photosensitive non-conductive adhesive

在步骤十七去除光阻膜后的金属基板背面进行绿漆或可感光的不导电胶材的披覆; Apply green paint or photosensitive non-conductive adhesive to the back of the metal substrate after removing the photoresist film in step seventeen;

步骤十九、曝光开窗显影 Step 19: Exposure, window development

利用曝光显影设备对金属基板背面披覆的绿漆或可感光的不导电胶材进行曝光显影开窗,以露出金属基板背面后续需要进行高导电金属层电镀的区域; Use exposure and development equipment to expose and develop the green paint or photosensitive non-conductive adhesive on the back of the metal substrate to expose the area on the back of the metal substrate that needs to be electroplated with a high-conductivity metal layer;

步骤二十、电镀高导电金属层 Step 20: Plating a highly conductive metal layer

在步骤十九中金属基板背面绿漆或可感光的不导电胶材的开窗区域内电镀上高导电金属层; Electroplate a highly conductive metal layer in the window area of the green paint on the back of the metal substrate or photosensitive non-conductive adhesive in step 19;

步骤二十一、电镀抗氧化金属层或披覆抗氧化剂(OSP) Step 21: Plating anti-oxidation metal layer or coating anti-oxidant (OSP)

在金属基板表面裸露在外的金属表面进行抗氧化金属层电镀或抗氧化剂披覆(OSP); Anti-oxidation metal layer electroplating or anti-oxidant coating (OSP) on the exposed metal surface of the metal substrate;

步骤二十二、堆叠封装体 Step 22. Stack Packages

在步骤二十一完成电镀抗氧化金属层或披覆抗氧化剂的导电柱子顶部进行封装体的堆叠; In step 21, the electroplating anti-oxidation metal layer or the top of the conductive pillar covered with anti-oxidant is carried out to stack the packages;

步骤二十三、切割成品 Step 23. Cut the finished product

将步骤二十而完成封装体堆叠的半成品进行切割作业,使原本以阵列式集合体方式集成在一起并含有芯片的塑封体模块一颗颗切割独立开来,制得先封后蚀三维系统级芯片正装堆叠封装结构成品。 The semi-finished product stacked in step 20 is cut and cut, so that the plastic package modules that are originally integrated in the form of an array assembly and contain chips are cut and separated one by one, and the three-dimensional system level of sealing first and etching later is obtained. The chip is mounted on a stacked package structure.

一种先封后蚀三维系统级芯片正装堆叠封装结构的工艺方法,所述方法包括以下步骤: A process method for encapsulating first and then etching a three-dimensional system-on-a-chip stacked packaging structure, the method comprising the following steps:

步骤一、取金属基板 Step 1. Take the metal substrate

步骤二、金属基板表面预镀铜材 Step 2. Pre-plating copper on the surface of the metal substrate

在金属基板表面预镀一层铜材; Pre-plating a layer of copper on the surface of the metal substrate;

步骤三、贴光阻膜作业 Step 3: Paste the photoresist film

在步骤二完成预镀铜材的金属基板正面及背面分别贴上可进行曝光显影的光阻膜; In step 2, a photoresist film that can be exposed and developed is pasted on the front and back of the metal substrate of the pre-plated copper material;

步骤四、金属基板正面去除部分光阻膜 Step 4. Remove part of the photoresist film from the front of the metal substrate

利用曝光显影设备将步骤三完成贴光阻膜作业的金属基板正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板正面后续需要进行第一金属线路层电镀的区域; Using exposure and development equipment, the front of the metal substrate that has completed the photoresist film pasting operation in step 3 is subjected to pattern exposure, development and removal of part of the pattern photoresist film, so as to expose the area on the front of the metal substrate that needs to be electroplated for the first metal circuit layer;

步骤五、电镀第一金属线路层 Step 5. Electroplating the first metal circuit layer

在步骤四中金属基板正面去除部分光阻膜的区域内电镀上第一金属线路层; Electroplating the first metal circuit layer in the area where part of the photoresist film is removed from the front of the metal substrate in step 4;

步骤六、贴光阻膜作业 Step 6. Paste photoresist film

在步骤五完成电镀第一金属线路层的金属基板正面贴上可进行曝光显影的光阻膜; In step 5, a photoresist film that can be exposed and developed is pasted on the front side of the metal substrate that has electroplated the first metal circuit layer;

步骤七、金属基板正面去除部分光阻膜 Step 7. Remove part of the photoresist film from the front of the metal substrate

利用曝光显影设备将步骤六完成贴光阻膜作业的金属基板正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板正面后续需要进行第二金属线路层电镀的区域; Use exposure and development equipment to expose, develop and remove part of the graphic photoresist film on the front of the metal substrate that has completed the photoresist film pasting operation in step 6, so as to expose the area that needs to be electroplated on the second metal circuit layer on the front of the metal substrate;

步骤八、电镀第二金属线路层 Step 8. Electroplating the second metal circuit layer

在步骤七中金属基板正面去除部分光阻膜的区域内电镀上第二金属线路层作为用以连接第一金属线路层与第三金属线路层的导电柱子; Electroplating the second metal circuit layer in the area where part of the photoresist film is removed on the front side of the metal substrate in step 7 as a conductive pillar for connecting the first metal circuit layer and the third metal circuit layer;

步骤九、去除光阻膜 Step 9. Remove the photoresist film

去除金属基板表面的光阻膜; Remove the photoresist film on the surface of the metal substrate;

步骤十、贴压不导电胶膜 Step 10. Paste and press the non-conductive film

在金属基板正面贴压一层不导电胶膜; Paste a layer of non-conductive adhesive film on the front of the metal substrate;

步骤十一、研磨不导电胶膜表面 Step 11. Grinding the surface of the non-conductive film

在步骤十完成不导电胶膜贴压后进行表面研磨; Surface grinding is carried out after the non-conductive adhesive film is pasted and pressed in step ten;

步骤十二、不导电胶膜表面金属化预处理 Step 12. Metallization pretreatment on the surface of the non-conductive film

对不导电胶膜表面进行金属化预处理,使其表面附着上一层金属化高分子材料或表面粗糙化处理; Carry out metallization pretreatment on the surface of the non-conductive adhesive film, so that the surface is attached with a layer of metallized polymer material or surface roughening treatment;

步骤十三、贴光阻膜作业 Step 13. Paste photoresist film

在步骤十二完成金属化的金属基板正面及背面贴上可进行曝光显影的光阻膜; Paste a photoresist film that can be exposed and developed on the front and back of the metallized metal substrate in step 12;

步骤十四、金属基板正面去除部分光阻膜 Step 14. Remove part of the photoresist film from the front of the metal substrate

利用曝光显影设备将步骤十三完成贴光阻膜作业的金属基板正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板正面后续需要进行蚀刻的区域图形; Exposing, developing and removing part of the graphic photoresist film on the front of the metal substrate on which the photoresist film pasting operation has been completed in step 13 by using exposure and development equipment, so as to expose the pattern of the area on the front of the metal substrate that needs to be etched later;

步骤十五、蚀刻 Step 15. Etching

将步骤十四中的金属基板正面光阻膜开窗后的区域进行蚀刻作业; Etching the area after opening the photoresist film on the front of the metal substrate in step 14;

步骤十六、去除光阻膜 Step sixteen, remove the photoresist film

去除金属基板正面的光阻膜; Remove the photoresist film on the front of the metal substrate;

步骤十七、电镀第三金属线路层 Step seventeen, electroplating the third metal circuit layer

在步骤十五中金属基板正面经蚀刻后保留的金属化预处理区域电镀上第三金属线路层,第三金属线路层电镀完成后即在金属基板正面形成相应的基岛和引脚; In step 15, the metallized pretreatment area retained after etching on the front side of the metal substrate is electroplated with a third metal circuit layer, and after the electroplating of the third metal circuit layer is completed, corresponding base islands and pins are formed on the front side of the metal substrate;

步骤十八、贴光阻膜作业 Step 18. Paste photoresist film

在步骤十七完成电镀第三金属线路层的金属基板正面贴上可进行曝光显影的光阻膜; In step 17, a photoresist film that can be exposed and developed is pasted on the front side of the metal substrate on which the electroplating of the third metal circuit layer is completed;

步骤十九、金属基板正面去除部分光阻膜 Step 19. Remove part of the photoresist film from the front of the metal substrate

利用曝光显影设备将步骤十八完成贴光阻膜作业的金属基板正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板正面后续需要进行导电柱子电镀的区域; Using the exposure and development equipment, perform graphic exposure, development and removal of part of the graphic photoresist film on the front of the metal substrate after step 18 has completed the operation of pasting the photoresist film, so as to expose the area on the front of the metal substrate that needs to be electroplated with conductive pillars;

步骤二十、电镀导电柱子 Step 20: Plating conductive pillars

在步骤十九中金属基板正面去除部分光阻膜的区域内电镀上导电柱子; Electroplate conductive pillars in the area where part of the photoresist film is removed from the front of the metal substrate in step 19;

步骤二十一、去除光阻膜 Step 21. Remove the photoresist film

去除金属基板表面的光阻膜; Remove the photoresist film on the surface of the metal substrate;

步骤二十二、装片 Step 22, loading film

在步骤十七形成的基岛正面涂覆导电或不导电粘结物质进行第一芯片的植入; Coating conductive or non-conductive adhesive substance on the front side of the base island formed in step 17 to implant the first chip;

步骤二十三、金属线键合 Step 23. Metal wire bonding

在第一芯片正面与步骤五形成的引脚之间进行键合金属线作业; Carry out bonding wire operation between the front surface of the first chip and the pins formed in step five;

步骤二十四、环氧树脂塑封 Step 24: Epoxy resin molding

在完成装片打线后的金属基板正面进行环氧树脂塑封保护; Epoxy resin plastic sealing protection is carried out on the front of the metal substrate after chip loading and wiring;

步骤二十五、环氧树脂表面研磨 Step 25. Epoxy resin surface grinding

在步骤二十四完成环氧树脂塑封后进行表面研磨; Surface grinding is carried out after epoxy resin molding is completed in step 24;

步骤二十六、贴光阻膜作业 Step 26. Paste the photoresist film

在步骤二十五完成环氧树脂表面研磨后的金属基板正面和背面贴上可进行曝光显影的光阻膜; Paste a photoresist film that can be exposed and developed on the front and back of the metal substrate after the epoxy resin surface is ground in step 25;

步骤二十七、金属基板背面去除部分光阻膜 Step 27. Remove part of the photoresist film on the back of the metal substrate

利用曝光显影设备将步骤二十六完成贴光阻膜作业的金属基板背面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板背面后续需要进行蚀刻的区域; Use the exposure and development equipment to expose, develop and remove part of the graphic photoresist film on the back of the metal substrate after the photoresist film pasting operation in step 26, so as to expose the area that needs to be etched on the back of the metal substrate;

步骤二十八、蚀刻 Step 28. Etching

在步骤二十七中金属基板背面去除部分光阻膜的区域进行化学蚀刻; Perform chemical etching in the area where part of the photoresist film is removed on the back of the metal substrate in step 27;

步骤二十九、去除光阻膜 Step 29. Remove the photoresist film

去除金属基板表面的光阻膜; Remove the photoresist film on the surface of the metal substrate;

步骤三十、金属基板背面披覆绿漆或可感光的不导电胶材 Step 30. Cover the back of the metal substrate with green paint or photosensitive non-conductive adhesive

在步骤二十九去除光阻膜后的金属基板背面进行绿漆或可感光的不导电胶材的披覆; After removing the photoresist film in step 29, coat the back of the metal substrate with green paint or photosensitive non-conductive adhesive;

步骤三十一、曝光开窗显影 Step 31: Exposure, window development

利用曝光显影设备对金属基板背面披覆的绿漆或可感光的不导电胶材进行曝光显影开窗,以露出金属基板背面后续需要进行高导电金属层电镀的区域; Use exposure and development equipment to expose and develop the green paint or photosensitive non-conductive adhesive on the back of the metal substrate to expose the area on the back of the metal substrate that needs to be electroplated with a high-conductivity metal layer;

步骤三十二、电镀高导电金属层 Step thirty-two, electroplating a highly conductive metal layer

在步骤三十一中金属基板背面绿漆或可感光的不导电胶材的开窗区域内电镀上高导电金属层; Electroplate a highly conductive metal layer in the window area of the green paint on the back of the metal substrate or photosensitive non-conductive adhesive in step 31;

步骤三十三、电镀抗氧化金属层或披覆抗氧化剂(OSP) Step 33: Plating anti-oxidation metal layer or coating anti-oxidant (OSP)

在金属基板表面裸露在外的金属表面进行抗氧化金属层电镀或披覆抗氧化剂(OSP); Plating an anti-oxidation metal layer or coating an anti-oxidant (OSP) on the exposed metal surface of the metal substrate;

步骤三十四、堆叠封装体 Step 34. Stack Packages

在步骤三十三完成电镀抗氧化金属层或披覆抗氧化剂的引脚背面进行封装体的堆叠; In step 33, the anti-oxidation metal layer is electroplated or the anti-oxidant is coated on the back of the pin to stack the package body;

步骤三十五、切割成品 Step 35. Cut the finished product

将步骤三十三完成封装体堆叠的半成品进行切割作业,使原本以阵列式集合体方式集成在一起并含有芯片的塑封体模块一颗颗切割独立开来,制得先封后蚀三维系统级芯片正装堆叠封装结构成品。 The semi-finished product stacked in step 33 is cut and cut, so that the plastic package modules that are originally integrated in the form of an array assembly and contain chips are cut and separated one by one, and the three-dimensional system level that is sealed first and etched later is obtained. The chip is mounted on a stacked package structure.

所述步骤六~步骤十七在步骤五与步骤十八之间重复进行多次。 The steps six to seventeen are repeated multiple times between steps five and eighteen.

一种先封后蚀三维系统级芯片正装堆叠封装结构,它包括基岛和引脚,所述引脚正面设置有导电柱子,所述基岛正面通过导电或不导电粘结物质正装有芯片,所述芯片正面与引脚正面之间通过金属线相连接,所述基岛和引脚正面区域以及导电柱子、芯片和金属线外围区域均包封有塑封料或环氧树脂,所述塑封料或环氧树脂与导电柱子顶部齐平,所述基岛和引脚背面设置有高导电金属层,所述高导电金属层与高导电金属层之间填充有绿漆或可感光不导电胶材,所述导电柱子露出塑封料或环氧树脂的表面以及高导电金属层露出绿漆或可感光不导电胶材的表面设置有抗氧化层,所述导电柱子顶部通过导电物质堆叠有封装体。 A three-dimensional system-level chip stacked packaging structure that is sealed first and etched later. It includes a base island and pins. The front side of the pins is provided with conductive pillars, and the front side of the base island is positively loaded with chips through conductive or non-conductive adhesive materials. The front of the chip and the front of the pins are connected by metal wires, and the base island and the front of the pins, as well as the conductive pillars, the peripheral areas of the chip and the metal wires are all encapsulated with a plastic encapsulant or epoxy resin, and the plastic encapsulant Or the epoxy resin is flush with the top of the conductive pillar, the base island and the back of the pin are provided with a highly conductive metal layer, and the space between the highly conductive metal layer and the high conductive metal layer is filled with green paint or photosensitive non-conductive adhesive An anti-oxidation layer is provided on the surface of the conductive pillar exposed from the molding compound or epoxy resin and the surface of the highly conductive metal layer exposed from the green paint or photosensitive non-conductive adhesive material, and the package is stacked on the top of the conductive pillar through the conductive substance.

所述封装体的外脚为L型脚、J型脚、平脚或金属球。 The outer pins of the package body are L-shaped pins, J-shaped pins, flat pins or metal balls.

所述封装体堆叠于导电柱子顶部,所述封装体由单个或多个引线框结构与封装体结构堆叠而成。 The package is stacked on top of the conductive pillars, and the package is formed by stacking a single or multiple lead frame structures and package structures.

所述导电柱子顶部设置有金属球。 A metal ball is arranged on the top of the conductive pillar.

所述封装体可以堆叠在导电柱子顶部,或堆叠在引脚背面高导电金属层上。 The package can be stacked on top of the conductive pillars, or on the highly conductive metal layer on the back of the pins.

与现有技术相比,本发明具有以下有益效果: Compared with the prior art, the present invention has the following beneficial effects:

与现有技术相比,本发明具有以下有益效果: Compared with the prior art, the present invention has the following beneficial effects:

1、本发明通过埋入物件的三维金属线路复合式基板堆叠封装体,该三维金属线路复合基板夹层本身可以埋入对象,所以该三维系统级金属线路基板可以直接堆叠封装体即可实现PoP(封装体堆叠封装体)系统级功能整合封装; 1. The present invention stacks the package body by embedding the three-dimensional metal circuit composite substrate of the object, and the interlayer of the three-dimensional metal circuit composite substrate itself can be embedded in the object, so the three-dimensional system-level metal circuit substrate can directly stack the package body to realize PoP ( package-on-package) system-level functional integration package;

2、三维系统级金属线路复合式基板与封装体之间通过基板上的导电柱子或者RDL(重布线)线路节点进行互联。而导电柱子或者RDL(重布线)线路节点都露出于基板塑封表面,所以三维系统级金属线路基板与顶层封装体之间可以不植金属球,可以直接灵活堆叠任何封装形式的器件包括被动组件如电阻、电容、电感等;; 2. The three-dimensional system-level metal circuit composite substrate and the package are interconnected through conductive pillars on the substrate or RDL (redistribution) circuit nodes. The conductive pillars or RDL (redistribution) circuit nodes are all exposed on the surface of the plastic package of the substrate, so there is no need to plant metal balls between the three-dimensional system-level metal circuit substrate and the top-level package, and devices in any package form can be directly and flexibly stacked, including passive components such as Resistors, capacitors, inductors, etc.;

3、三维系统级金属线路基板的导电柱子或RDL(重布线)线路节点都露出于基板塑封表面,所以基板厚度不会受限于互联节点的高度,基板内部可以根据需要堆叠埋入多层芯片或被动组件; 3. The conductive pillars or RDL (rewiring) circuit nodes of the three-dimensional system-level metal circuit substrate are exposed on the surface of the substrate plastic package, so the thickness of the substrate will not be limited by the height of the interconnection nodes, and the interior of the substrate can be stacked and embedded with multi-layer chips as needed or passive components;

4、三维系统级金属线路基板的导电柱子或(重布线)线路节点都露出于基板塑封表面,所以顶层封装体外脚可以采用小金属球与导电柱子进行互联,如图84。 4. The conductive pillars or (rewiring) circuit nodes of the three-dimensional system-level metal circuit substrate are exposed on the plastic surface of the substrate, so the outer pins of the top package can be interconnected with the conductive pillars by using small metal balls, as shown in Figure 84.

5、三维系统级金属线路基板与封装体之间通过基板上的导电柱子进行互联,所以回流焊前后导电柱子不会发生热形变,从而不需要为避免回流焊后导电柱子互相短路而增加导电柱子之间的间距,方便堆叠密间距的封装体。 5. The three-dimensional system-level metal circuit substrate and the package are interconnected through the conductive pillars on the substrate, so the conductive pillars will not undergo thermal deformation before and after reflow soldering, so there is no need to add conductive pillars to avoid short circuit between the conductive pillars after reflow soldering The spacing between them is convenient for stacking fine-pitch packages.

附图说明 Description of drawings

图1~图23为本发明一种先封后蚀三维系统级芯片正装堆叠封装结构工艺方法实施例1的各工序示意图。 1 to 23 are schematic diagrams of each process in Embodiment 1 of a process method for a three-dimensional system-on-a-chip front-loaded stack package structure according to the present invention.

图24为本发明一种先封后蚀三维系统级芯片正装堆叠封装结构实施例1的示意图。 FIG. 24 is a schematic diagram of Embodiment 1 of a three-dimensional system-on-a-chip front-load stack package structure according to the present invention.

图25~图71为本发明一种先封后蚀三维系统级芯片正装堆叠封装结构工艺方法实施例2的各工序示意图。 25 to 71 are schematic diagrams of each process in Embodiment 2 of a process method of a three-dimensional system-on-a-chip front-load stack package structure according to the present invention.

图72为本发明一种先封后蚀三维系统级芯片正装堆叠封装结构实施例2的示意图。 FIG. 72 is a schematic diagram of Embodiment 2 of a package-first-etch-later three-dimensional system-on-a-chip front-pack package structure according to the present invention.

图73为本发明一种先封后蚀三维系统级芯片正装堆叠封装结构实施例3的示意图。 FIG. 73 is a schematic diagram of Embodiment 3 of a three-dimensional system-on-a-chip front-pack package structure according to the present invention.

图74为本发明一种先封后蚀三维系统级芯片正装堆叠封装结构实施例4的示意图。 FIG. 74 is a schematic diagram of Embodiment 4 of a package-first-etch-later three-dimensional system-on-a-chip front-pack package structure according to the present invention.

图75为本发明一种先封后蚀三维系统级芯片正装堆叠封装结构实施例5的示意图。 FIG. 75 is a schematic diagram of Embodiment 5 of a package-first-etch-then-three-dimensional system-on-a-chip front-pack package structure according to the present invention.

图76为本发明一种先封后蚀三维系统级芯片正装堆叠封装结构实施例6的示意图。 FIG. 76 is a schematic diagram of Embodiment 6 of a package-first-etch-then-three-dimensional system-on-a-chip front-pack package structure according to the present invention.

图77为本发明一种先封后蚀三维系统级芯片正装堆叠封装结构实施例7的示意图。 FIG. 77 is a schematic diagram of Embodiment 7 of a package-first-etch-later three-dimensional system-on-a-chip front-pack package structure according to the present invention.

图78为本发明一种先封后蚀三维系统级芯片正装堆叠封装结构实施例8的示意图。 FIG. 78 is a schematic diagram of Embodiment 8 of a package-first-etch-later three-dimensional system-on-a-chip front-pack package structure according to the present invention.

图79为本发明一种先封后蚀三维系统级芯片正装堆叠封装结构实施例9的示意图。 Fig. 79 is a schematic diagram of Embodiment 9 of a front-pack package structure of a three-dimensional system-on-a-chip stacked before etching according to the present invention.

图80为传统PoP基板封装体堆叠结构的示意图。 FIG. 80 is a schematic diagram of a conventional PoP substrate package stack structure.

图81为传统PoP基板封装体堆叠结构中顶层封装体的焊球高度过小而无法与底层封装体的焊盘实现互联的示意图。 FIG. 81 is a schematic diagram of a traditional PoP substrate package stacking structure in which the solder ball height of the top package is too small to be interconnected with the pads of the bottom package.

图82为传统PoP基板封装体堆叠结构中回流焊后焊球热变形而无法实现密间距封装堆叠的示意图。 FIG. 82 is a schematic diagram of a traditional PoP substrate package stacking structure in which solder balls are thermally deformed after reflow soldering and cannot achieve fine-pitch package stacking.

图83为采用多个小金属锡球堆叠对位偏移的示意图。 FIG. 83 is a schematic diagram of stacking and offsetting multiple small metal solder balls.

图84为本发明顶层封装体外脚可以采用小金属球与三维系统级金属线路基板进行互联的示意图。 FIG. 84 is a schematic diagram showing that the outer pins of the top package of the present invention can be interconnected with a three-dimensional system-level metal circuit substrate by using small metal balls.

其中: in:

基岛1 base island 1

引脚2 pin 2

导电柱子3 Conductive pillar 3

芯片4 chip 4

金属线5 Metal wire 5

导电或不导电粘结物质6 Conductive or non-conductive bonding substances6

塑封料或环氧树脂7 Molding Compound or Epoxy 7

抗氧化层8 Antioxidant layer 8

导电物质9 Conductive substance 9

封装体10 Package 10

引线框结构10.1 Lead frame structure 10.1

封装体结构10.2 Package Structure 10.2

高导电金属层11 Highly Conductive Metal Layer 11

绿漆或可感光不导电胶材12 Green paint or photosensitive non-conductive adhesive 12

金属球13。 metal ball13.

具体实施方式 detailed description

本发明一种先封后蚀三维系统级芯片正装堆叠封装结构及工艺方法如下: The structure and process method of a three-dimensional system-level chip stacked packaging structure and process are as follows:

实施例1:单层线路 Example 1: Single-layer circuit

参见图24,本发明一种先封后蚀三维系统级芯片正装堆叠封装结构,它包括基岛1和引脚2,所述引脚2正面设置有导电柱子3,所述基岛1正面通过导电或不导电粘结物质6正装有芯片4,所述芯片4正面与引脚2正面之间通过金属线5相连接,所述基岛1和引脚2正面区域以及导电柱子3、芯片4和金属线5外围区域均包封有塑封料或环氧树脂7,所述塑封料或环氧树脂7与导电柱子3顶部齐平,所述基岛1和引脚2背面设置有高导电金属层11,所述高导电金属层11与高导电金属层11之间填充有绿漆或可感光不导电胶材12,所述导电柱子3露出塑封料或环氧树脂7的表面以及高导电金属层11露出绿漆或可感光不导电胶材12的表面设置有抗氧化层8,所述导电柱子3顶部通过导电物质9堆叠有封装体10,所述封装体10的外脚为L型脚。 Referring to Fig. 24, the present invention presents a three-dimensional system-on-a-chip stacked packaging structure, which includes a base island 1 and pins 2. Conductive pillars 3 are arranged on the front side of the pins 2, and the front side of the base island 1 passes through Conductive or non-conductive bonding substance 6 is equipped with chip 4, the front of said chip 4 is connected with the front of pin 2 through metal wire 5, the front area of said base island 1 and pin 2 and conductive pillar 3, chip 4 and the peripheral area of the metal wire 5 are encapsulated with a molding compound or epoxy resin 7, the molding compound or epoxy resin 7 is flush with the top of the conductive pillar 3, and the back of the base island 1 and the pin 2 is provided with a highly conductive metal Layer 11, green paint or photosensitive non-conductive adhesive material 12 is filled between the highly conductive metal layer 11 and the highly conductive metal layer 11, and the conductive pillar 3 exposes the surface of the molding compound or epoxy resin 7 and the highly conductive metal An anti-oxidation layer 8 is provided on the surface of the layer 11 that exposes the green paint or photosensitive non-conductive adhesive material 12. The top of the conductive pillar 3 is stacked with a package 10 through a conductive material 9. The outer legs of the package 10 are L-shaped legs. .

其工艺方法如下: Its process method is as follows:

步骤一、取金属基板 Step 1. Take the metal substrate

参见图1,取一片厚度合适的金属基板,金属基板的材质可以是铜材、铁材、镀锌材、不锈钢材或铝材或可以达到导电功能的金属物质等,厚度的选择可依据产品特性进行选择; See Figure 1, take a piece of metal substrate with appropriate thickness, the material of metal substrate can be copper, iron, galvanized material, stainless steel or aluminum or metal material that can achieve conductive function, etc. The choice of thickness can be based on product characteristics make a choice;

步骤二、金属基板表面预镀铜材 Step 2. Pre-plating copper on the surface of the metal substrate

参见图2,在金属基板表面预镀一层铜材,铜层厚度为2~10微米,依据功能需要也可以减薄或是增厚,电镀方式可以是电解电镀也可以采用化学沉积的方式; Referring to Figure 2, a layer of copper is pre-plated on the surface of the metal substrate. The thickness of the copper layer is 2 to 10 microns. It can also be thinned or thickened according to the functional requirements. The electroplating method can be electrolytic plating or chemical deposition;

步骤三、贴光阻膜作业 Step 3: Paste the photoresist film

参见图3,在步骤二完成预镀铜材的金属基板正面及背面分别贴上可进行曝光显影的光阻膜,目的是为了后续金属线路图形的制作,光阻膜可以是干式光阻膜也可以是湿式光阻膜; Referring to Figure 3, in step 2, the front and back of the metal substrate of the pre-plated copper material are respectively pasted with a photoresist film that can be exposed and developed. The purpose is to make subsequent metal circuit patterns. The photoresist film can be a dry photoresist film It can also be a wet photoresist film;

步骤四、金属基板正面去除部分光阻膜 Step 4. Remove part of the photoresist film from the front of the metal substrate

参见图4,利用曝光显影设备将步骤三完成贴光阻膜作业的金属基板正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板正面后续需要进行金属线路层电镀的区域; Referring to Figure 4, use the exposure and developing equipment to expose, develop and remove part of the graphic photoresist film on the front of the metal substrate that has completed the photoresist film pasting operation in step 3, so as to expose the area on the front of the metal substrate that needs to be electroplated with the metal circuit layer;

步骤五、电镀金属线路层 Step 5. Plating metal circuit layer

参见图5,在步骤四中金属基板正面去除部分光阻膜的区域内电镀上金属线路层,金属线路层电镀完成后即在金属基板正面形成相应的基岛和引脚,金属线路层的材质可以是铜、铝、镍、银、金、铜银、镍金或镍钯金或可以达到导电功能的金属物质等,金属线路层厚度为5~20微米,可以根据不同应用选择不同的电镀材质,根据不同特性变换电镀的厚度,电镀方式可以是电解电镀也可以采用化学沉积的方式; Referring to Figure 5, a metal circuit layer is electroplated in the area where part of the photoresist film is removed from the front of the metal substrate in step 4. After the metal circuit layer is electroplated, corresponding base islands and pins are formed on the front of the metal substrate. The material of the metal circuit layer It can be copper, aluminum, nickel, silver, gold, copper silver, nickel gold or nickel palladium gold or metal substances that can achieve conductive function, etc. The thickness of the metal circuit layer is 5~20 microns, and different plating materials can be selected according to different applications According to different characteristics, the thickness of electroplating can be changed, and the electroplating method can be electrolytic plating or chemical deposition;

步骤六、贴光阻膜作业 Step 6. Paste photoresist film

参见图6,在步骤五完成电镀金属线路层的金属基板正面贴上可进行曝光显影的光阻膜,目的是为后续导电柱子的制作,光阻膜可以是干式光阻膜也可以是湿式光阻膜; Referring to Figure 6, the photoresist film that can be exposed and developed is pasted on the front of the metal substrate where the electroplated metal circuit layer is completed in step 5. The purpose is to make the subsequent conductive pillars. The photoresist film can be a dry photoresist film or a wet photoresist film. Photoresist film;

步骤七、金属基板正面去除部分光阻膜 Step 7. Remove part of the photoresist film from the front of the metal substrate

参见图7,利用曝光显影设备将步骤六完成贴光阻膜作业的金属基板正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板正面后续需要进行导电柱子电镀的区域; Referring to Figure 7, use the exposure and developing equipment to expose, develop and remove part of the graphic photoresist film on the front of the metal substrate that has completed the photoresist film pasting operation in step 6, so as to expose the area on the front of the metal substrate that needs to be electroplated with conductive pillars;

步骤八、电镀导电柱子 Step 8. Plating conductive pillars

参见图8,在步骤七中金属基板正面去除部分光阻膜的区域内电镀上导电柱子,导电柱子的材质可以是铜、铝、镍、银、金、铜银、镍金、镍钯金或可以达到导电功能的金属物质等材料,电镀方式可以是电解电镀也可以采用化学沉积的方式; Referring to Figure 8, electroplate conductive pillars in the area where part of the photoresist film is removed from the front of the metal substrate in step 7. The material of the conductive pillars can be copper, aluminum, nickel, silver, gold, copper silver, nickel gold, nickel palladium gold or For materials such as metal substances that can achieve conductive functions, the electroplating method can be electrolytic plating or chemical deposition;

步骤九、去除光阻膜 Step 9. Remove the photoresist film

参见图9,去除金属基板表面的光阻膜,去除光阻膜的方法采用化学药水软化并采用高压水冲洗即可; Referring to Figure 9, remove the photoresist film on the surface of the metal substrate. The method of removing the photoresist film is softened by chemical potion and rinsed with high-pressure water;

步骤十、装片 Step ten, loading film

参见图10,在步骤五形成的基岛正面涂覆导电或不导电粘结物质进行第一芯片的植入; Referring to FIG. 10 , the front side of the base island formed in step five is coated with a conductive or non-conductive adhesive substance to implant the first chip;

步骤十一、金属线键合 Step 11. Wire Bonding

参见图11,在第一芯片正面与步骤五形成的引脚之间进行键合金属线作业; Referring to FIG. 11 , the metal wire bonding operation is performed between the front surface of the first chip and the pins formed in step 5;

步骤十二、环氧树脂塑封 Step 12. Epoxy resin plastic sealing

参见图12,在完成装片打线后的金属基板正面进行环氧树脂塑封保护,环氧树脂材料可以依据产品特性选择有填料或是没有填料的种类; Referring to Figure 12, epoxy resin is used to protect the front of the metal substrate after chip loading and wiring. The epoxy resin material can be filled or not filled according to product characteristics;

步骤十三、环氧树脂表面研磨 Step 13. Epoxy resin surface grinding

参见图13,在步骤十二完成环氧树脂塑封后进行表面研磨; Referring to Figure 13, surface grinding is performed after epoxy resin molding is completed in step 12;

步骤十四、贴光阻膜作业 Step 14. Paste photoresist film

参见图14,在步骤十三完成环氧树脂表面研磨后的金属基板正面和背面贴上可进行曝光显影的光阻膜; Referring to FIG. 14 , in step 13, the front and back of the metal substrate after the surface grinding of the epoxy resin is pasted with a photoresist film that can be exposed and developed;

步骤十五、金属基板背面去除部分光阻膜 Step 15. Remove part of the photoresist film on the back of the metal substrate

参见图15,利用曝光显影设备将步骤十四完成贴光阻膜作业的金属基板背面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板背面后续需要进行蚀刻的区域; Referring to FIG. 15 , use the exposure and developing equipment to expose, develop and remove part of the graphic photoresist film on the back of the metal substrate that has completed the photoresist film pasting operation in step 14, so as to expose the area that needs to be etched later on the back of the metal substrate;

步骤十六、蚀刻 Step 16. Etching

参见图16,在步骤十五中金属基板背面去除部分光阻膜的区域进行化学蚀刻,进行蚀刻的方法可以是氯化铜或是氯化铁的工艺方式; Referring to Fig. 16, chemical etching is carried out in the area where part of the photoresist film is removed on the back of the metal substrate in step 15, and the etching method can be copper chloride or ferric chloride;

步骤十七、去除光阻膜 Step seventeen, remove the photoresist film

参见图17,去除金属基板表面的光阻膜,去除光阻膜的方法采用化学药水软化并采用高压水冲洗即可; Referring to Figure 17, remove the photoresist film on the surface of the metal substrate. The method of removing the photoresist film is softened by chemical potion and rinsed with high-pressure water;

步骤十八、金属基板背面披覆绿漆或可感光的不导电胶材 Step 18. Cover the back of the metal substrate with green paint or photosensitive non-conductive adhesive

参见图18,在步骤十七去除光阻膜后的金属基板背面进行绿漆或可感光的不导电胶材的披覆; Referring to Fig. 18, the back of the metal substrate after removing the photoresist film in step 17 is coated with green paint or photosensitive non-conductive adhesive;

步骤十九、曝光开窗显影 Step 19: Exposure, window development

参见图19,利用曝光显影设备对金属基板背面披覆的绿漆或可感光的不导电胶材进行曝光显影开窗,以露出金属基板背面后续需要进行高导电金属层电镀的区域; Referring to Figure 19, use the exposure and development equipment to expose and develop the green paint or photosensitive non-conductive adhesive material coated on the back of the metal substrate to expose the area on the back of the metal substrate that needs to be electroplated with a high-conductivity metal layer;

步骤二十、电镀高导电金属层 Step 20: Plating a highly conductive metal layer

参见图20,在步骤十九中金属基板背面绿漆或可感光的不导电胶材的开窗区域内电镀上高导电金属层,电镀方式可以是电解电镀也可以采用化学沉积的方式; Referring to Figure 20, in step 19, electroplate a highly conductive metal layer in the window area of the green paint on the back of the metal substrate or photosensitive non-conductive adhesive material, the electroplating method can be electrolytic plating or chemical deposition;

步骤二十一、电镀抗氧化金属层或披覆抗氧化剂(OSP) Step 21: Plating anti-oxidation metal layer or coating anti-oxidant (OSP)

参见图21,在金属基板表面裸露在外的金属表面进行抗氧化金属层电镀,如金、镍金、镍钯金、锡或是披覆抗氧化剂(OSP); Referring to Figure 21, electroplating an anti-oxidation metal layer on the exposed metal surface of the metal substrate, such as gold, nickel gold, nickel palladium gold, tin or coated antioxidant (OSP);

步骤二十二、堆叠封装体 Step 22. Stack Packages

参见图22,在步骤二十一完成电镀抗氧化金属层或披覆抗氧化剂的导电柱子顶部通过导电物质进行封装体的堆叠; Referring to FIG. 22 , in step 21, the electroplating anti-oxidation metal layer or the top of the conductive pillar coated with anti-oxidant is stacked with a conductive substance;

步骤二十三、切割成品 Step 23. Cut the finished product

参见图23,将步骤二十而完成封装体堆叠的半成品进行切割作业,使原本以阵列式集合体方式集成在一起并含有芯片的塑封体模块一颗颗切割独立开来,制得先封后蚀三维系统级芯片正装堆叠封装结构成品。 Referring to Figure 23, the semi-finished product stacked in step 20 is cut, so that the plastic package modules that are originally integrated in the form of an array assembly and contain chips are cut and separated one by one, and the first-sealed and later-packed The three-dimensional system-on-a-chip stacked package structure is finished.

实施例2:多层线路 Embodiment 2: multi-layer circuit

参见图72,本发明一种先封后蚀三维系统级芯片正装堆叠封装结构,它包括基岛1和引脚2,所述引脚2正面设置有导电柱子3,所述基岛1正面通过导电或不导电粘结物质6正装有芯片4,所述芯片4正面与引脚2正面之间通过金属线5相连接,所述基岛1和引脚2正面的区域以及导电柱子3、芯片4和金属线5外围的区域均包封有塑封料或环氧树脂7,所述塑封料或环氧树脂7与导电柱子3顶部齐平,所述基岛1和引脚2背面设置有高导电金属层11,所述高导电金属层11与高导电金属层11之间填充有绿漆或可感光不导电胶材12,所述导电柱子3露出塑封料或环氧树脂7的表面以及高导电金属层11露出绿漆或可感光不导电胶材12的表面设置有抗氧化层8,所述导电柱子3顶部通过导电物质9堆叠有封装体10,所述封装体10的外脚为L型脚。 Referring to Fig. 72, the present invention presents a three-dimensional system-on-a-chip stacked package structure, which includes a base island 1 and pins 2, and conductive pillars 3 are arranged on the front side of the pins 2, and the front side of the base island 1 passes through Conductive or non-conductive bonding material 6 is equipped with chip 4, the front of said chip 4 is connected with the front of pin 2 through metal wire 5, the area of said base island 1 and the front of pin 2 and conductive pillar 3, chip 4 and the peripheral area of the metal wire 5 are encapsulated with molding compound or epoxy resin 7, the molding compound or epoxy resin 7 is flush with the top of the conductive pillar 3, and the base island 1 and the back of the pin 2 are provided with high The conductive metal layer 11 is filled with green paint or photosensitive non-conductive adhesive material 12 between the high conductive metal layer 11 and the high conductive metal layer 11, and the conductive pillar 3 exposes the surface of the molding compound or epoxy resin 7 and the high The conductive metal layer 11 exposes the green paint or the surface of the photosensitive non-conductive adhesive material 12 is provided with an anti-oxidation layer 8, and the top of the conductive pillar 3 is stacked with a package body 10 through a conductive material 9, and the outer leg of the package body 10 is L shaped feet.

实施例2与实施例1的区别在于:所述基岛1和引脚2均由多层金属线路层组成,金属线路层与金属线路层之间通过导电柱子相连接。 The difference between embodiment 2 and embodiment 1 is that: both the base island 1 and the pin 2 are composed of multiple layers of metal circuit layers, and the metal circuit layers are connected by conductive pillars.

其工艺方法如下: Its process method is as follows:

步骤一、取金属基板 Step 1. Take the metal substrate

参见图25,取一片厚度合适的金属基板,金属基板的材质可以是铜材、铁材、镀锌材、不锈钢材、铝材或可以达到导电功能的金属物质或非金属物质,厚度的选择可依据产品特性进行选择; Referring to Figure 25, take a piece of metal substrate with a suitable thickness. The material of the metal substrate can be copper, iron, galvanized, stainless steel, aluminum or metal or non-metal that can achieve conductive function. The thickness can be selected Choose according to product characteristics;

步骤二、金属基板表面预镀铜材 Step 2. Pre-plating copper on the surface of the metal substrate

参见图26,在金属基板表面预镀一层铜材,铜层厚度为2~10微米,依据功能需要也可以减薄或是增厚,电镀方式可以是电解电镀也可以采用化学沉积的方式; Referring to Figure 26, a layer of copper is pre-plated on the surface of the metal substrate. The thickness of the copper layer is 2 to 10 microns. It can also be thinned or thickened according to functional requirements. The electroplating method can be electrolytic plating or chemical deposition;

步骤三、贴光阻膜作业 Step 3: Paste the photoresist film

参见图27,在步骤二完成预镀铜材的金属基板正面及背面分别贴上可进行曝光显影的光阻膜,目的是为了后续金属线路图形的制作,光阻膜可以是干式光阻膜也可以是湿式光阻膜; Referring to Figure 27, in step 2, the front and back of the metal substrate of the pre-plated copper material are respectively pasted with a photoresist film that can be exposed and developed. The purpose is to make subsequent metal circuit patterns. The photoresist film can be a dry photoresist film It can also be a wet photoresist film;

步骤四、金属基板正面去除部分光阻膜 Step 4. Remove part of the photoresist film from the front of the metal substrate

参见图28,利用曝光显影设备将步骤三完成贴光阻膜作业的金属基板正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板正面后续需要进行第一金属线路层电镀的区域; Referring to Figure 28, use the exposure and development equipment to expose, develop and remove part of the patterned photoresist film on the front of the metal substrate that has completed the photoresist film pasting operation in step 3, so as to expose the area that needs to be electroplated on the first metal circuit layer on the front of the metal substrate ;

步骤五、电镀第一金属线路层 Step 5. Electroplating the first metal circuit layer

参见图29,在步骤四中金属基板正面去除部分光阻膜的区域内电镀上第一金属线路层,第一金属线路层的材质可以是铜、铝、镍、银、金、铜银、镍金或镍钯金等,电镀方式可以是电解电镀也可以采用化学沉积的方式; Referring to Figure 29, the first metal circuit layer is electroplated in the area where part of the photoresist film is removed from the front of the metal substrate in step 4. The material of the first metal circuit layer can be copper, aluminum, nickel, silver, gold, copper silver, nickel Gold or nickel-palladium-gold, etc., the electroplating method can be electrolytic plating or chemical deposition;

步骤六、贴光阻膜作业 Step 6. Paste photoresist film

参见图30,在步骤五完成电镀第一金属线路层的金属基板正面贴上可进行曝光显影的光阻膜,目的是为后续金属线路图形的制作,光阻膜可以是干式光阻膜也可以是湿式光阻膜; Referring to Figure 30, in Step 5, the metal substrate that has electroplated the first metal circuit layer is pasted with a photoresist film that can be exposed and developed for the purpose of making subsequent metal circuit patterns. The photoresist film can be dry photoresist film or Can be a wet photoresist film;

步骤七、金属基板正面去除部分光阻膜 Step 7. Remove part of the photoresist film from the front of the metal substrate

参见图31,利用曝光显影设备将步骤六完成贴光阻膜作业的金属基板正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板正面后续需要进行第二金属线路层电镀的区域; Referring to Figure 31, use the exposure and developing equipment to expose, develop and remove part of the patterned photoresist film on the front of the metal substrate that has completed the photoresist film pasting operation in step 6, so as to expose the area on the front of the metal substrate that needs to be electroplated for the second metal circuit layer ;

步骤八、电镀第二金属线路层 Step 8. Electroplating the second metal circuit layer

参见图32,在步骤七中金属基板正面去除部分光阻膜的区域内电镀上第二金属线路层作为用以连接第一金属线路层与第三金属线路层的导电柱子,第二金属线路层的材质可以是铜、铝、镍、银、金、铜银、镍金、镍钯金或可以达到导电功能的金属物质等材料,电镀方式可以是电解电镀也可以采用化学沉积的方式; Referring to Fig. 32, in the area where part of the photoresist film is removed from the front of the metal substrate in step 7, the second metal wiring layer is electroplated as a conductive pillar for connecting the first metal wiring layer and the third metal wiring layer, and the second metal wiring layer The material can be copper, aluminum, nickel, silver, gold, copper silver, nickel gold, nickel palladium gold or metal substances that can achieve conductive functions, and the electroplating method can be electrolytic plating or chemical deposition;

步骤九、去除光阻膜 Step 9. Remove the photoresist film

参见图33,去除金属基板表面的光阻膜,去除光阻膜的方法采用化学药水软化并采用高压水冲洗即可; Referring to Figure 33, remove the photoresist film on the surface of the metal substrate. The method of removing the photoresist film is softened by chemical potion and rinsed with high-pressure water;

步骤十、贴压不导电胶膜 Step 10. Paste and press the non-conductive film

参见图34,在金属基板正面(有线路层的区域)贴压一层不导电胶膜,其目的是为第一金属线路层与第三金属线路层进行绝缘;贴压不导电胶膜的方式可以采用常规的滚压设备,或是在真空环境下进行贴压,以防止贴压过程产生空气的残留;不导电胶膜主要是贴压式热固型环氧树脂,而环氧树脂中可以依据产品特性采用没有填料或是有填料的不导电胶膜; Referring to Figure 34, a layer of non-conductive adhesive film is pasted on the front of the metal substrate (the area with the circuit layer), the purpose of which is to insulate the first metal circuit layer from the third metal circuit layer; the way of pasting the non-conductive film Conventional rolling equipment can be used, or it can be pasted in a vacuum environment to prevent air residue during the pasting process; the non-conductive adhesive film is mainly pasted and pressed thermosetting epoxy resin, and epoxy resin can According to the characteristics of the product, non-conductive film with no filler or filler is used;

步骤十一、研磨不导电胶膜表面 Step 11. Grinding the surface of the non-conductive film

参见图35,在步骤十完成不导电胶膜贴压后进行表面研磨,目的是露出第二金属线路层、维持不导电胶膜与第二金属线路层的平整度以及控制不导电胶膜的厚度; Referring to Figure 35, surface grinding is carried out after the non-conductive adhesive film is pasted and pressed in step 10. The purpose is to expose the second metal circuit layer, maintain the flatness of the non-conductive adhesive film and the second metal circuit layer, and control the thickness of the non-conductive adhesive film ;

步骤十二、不导电胶膜表面金属化预处理 Step 12. Metallization pretreatment on the surface of the non-conductive film

参见图36,对不导电胶膜表面进行金属化预处理,使其表面附着上一层金属化高分子材料或表面粗糙化处理,目的是作为后续金属材料能够镀上去的触媒转换,附着金属化高分子材料可以采用喷涂、等离子震荡、表面粗化等再行烘干即可; Referring to Figure 36, metallization pretreatment is carried out on the surface of the non-conductive adhesive film, so that the surface is attached with a layer of metallized polymer material or the surface is roughened. Polymer materials can be dried by spraying, plasma shock, surface roughening, etc.;

步骤十三、贴光阻膜作业 Step 13. Paste photoresist film

参见图37,在步骤十二完成金属化的金属基板正面及背面贴上可进行曝光显影的光阻膜,目的是为后续金属线路图形的制作,光阻膜可以是干式光阻膜也可以是湿式光阻膜; Referring to Figure 37, in step 12, a photoresist film that can be exposed and developed is attached to the front and back of the metal substrate that has been metallized. The purpose is to make subsequent metal circuit patterns. The photoresist film can be a dry photoresist film It is a wet photoresist film;

步骤十四、金属基板正面去除部分光阻膜 Step 14. Remove part of the photoresist film from the front of the metal substrate

参见图38,利用曝光显影设备将步骤十三完成贴光阻膜作业的金属基板正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板正面后续需要进行蚀刻的区域图形; Referring to FIG. 38 , use the exposure and developing equipment to expose, develop and remove part of the graphic photoresist film on the front of the metal substrate that has completed the photoresist film pasting operation in step 13, so as to expose the area pattern that needs to be etched later on the front of the metal substrate;

步骤十五、蚀刻 Step 15. Etching

参见图39,将步骤十四中的金属基板正面光阻膜开窗后的区域进行蚀刻作业,其目的是利用腐蚀技术腐蚀去除后续不需要进行电镀第三金属线路层的金属化预处理区域,进行蚀刻的方法可以是氯化铜或是氯化铁的工艺方式; Referring to Fig. 39, the etching operation is carried out on the area after the window opening of the photoresist film on the front side of the metal substrate in step 14. The purpose is to use etching technology to etch and remove the subsequent metallization pretreatment area that does not need to be electroplated with the third metal circuit layer. The etching method can be copper chloride or ferric chloride process;

步骤十六、去除光阻膜 Step sixteen, remove the photoresist film

参见图40,去除金属基板正面的光阻膜,去除光阻膜的方法采用化学药水软化并采用高压水冲洗即可; Referring to Figure 40, remove the photoresist film on the front of the metal substrate. The method of removing the photoresist film is softened by chemical potion and rinsed with high-pressure water;

步骤十七、电镀第三金属线路层 Step seventeen, electroplating the third metal circuit layer

参见图41,在步骤十五中金属基板正面经蚀刻后保留的金属化预处理区域电镀上第三金属线路层,第三金属线路层的材质可以是铜、铝、镍、银、金、铜银、镍金或镍钯金等,电镀方式可以是电解电镀也可以采用化学沉积的方式; Referring to Fig. 41, in step 15, the metallized pretreatment area remaining after the front of the metal substrate is etched is electroplated with a third metal circuit layer, and the material of the third metal circuit layer can be copper, aluminum, nickel, silver, gold, copper Silver, nickel gold or nickel palladium gold, etc., the electroplating method can be electrolytic plating or chemical deposition;

步骤十八、贴光阻膜作业 Step 18. Paste photoresist film

参见图42,在步骤十八完成电镀第三金属线路层的金属基板正面贴上可进行曝光显影的光阻膜,目的是为后续金属线路图形的制作,光阻膜可以是干式光阻膜也可以是湿式光阻膜; Referring to Figure 42, in step 18, a photoresist film that can be exposed and developed is pasted on the front side of the metal substrate that is electroplated with the third metal circuit layer. The purpose is to make subsequent metal circuit patterns. The photoresist film can be a dry photoresist film It can also be a wet photoresist film;

步骤十九、金属基板正面去除部分光阻膜 Step 19. Remove part of the photoresist film from the front of the metal substrate

参见图43,利用曝光显影设备将步骤十八完成贴光阻膜作业的金属基板正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板正面后续需要进行第四金属线路层电镀的区域; Referring to Figure 43, use the exposure and developing equipment to expose, develop and remove part of the patterned photoresist film on the front of the metal substrate that has completed the photoresist film pasting operation in step 18, so as to expose the surface of the metal substrate that needs to be subsequently electroplated on the fourth metal circuit layer area;

步骤二十、电镀第四金属线路层 Step 20, electroplating the fourth metal circuit layer

参见图44,在步骤十九中金属基板正面去除部分光阻膜的区域内电镀上第四金属线路层作为用以连接第三金属线路层与第五金属线路层的导电柱子,第四金属线路层的材质可以是铜、铝、镍、银、金、铜银、镍金、镍钯金或可以达到导电功能的金属物质等材料,电镀方式可以是电解电镀也可以采用化学沉积的方式; Referring to Fig. 44, in the area where part of the photoresist film is removed from the front of the metal substrate in step nineteen, the fourth metal circuit layer is electroplated as a conductive pillar for connecting the third metal circuit layer and the fifth metal circuit layer, and the fourth metal circuit layer The material of the layer can be copper, aluminum, nickel, silver, gold, copper silver, nickel gold, nickel palladium gold or metal substances that can achieve conductive functions, and the electroplating method can be electrolytic plating or chemical deposition;

步骤二十一、去除光阻膜 Step 21. Remove the photoresist film

参见图45,去除金属基板正面的光阻膜,去除光阻膜的方法采用化学药水软化并采用高压水冲洗即可; Referring to Figure 45, remove the photoresist film on the front of the metal substrate. The method of removing the photoresist film is softened by chemical potion and washed with high-pressure water;

步骤二十二、贴压不导电胶膜 Step 22. Paste and press the non-conductive film

参见图46,在金属基板正面(有线路层的区域)贴压一层不导电胶膜,其目的是为第三金属线路层与第五金属线路层进行绝缘;贴压不导电胶膜的方式可以采用常规的滚压设备,或是在真空环境下进行贴压,以防止贴压过程产生空气的残留;不导电胶膜主要是贴压式热固型环氧树脂,而环氧树脂中可以依据产品特性采用没有填料或是有填料的不导电胶膜; Referring to Figure 46, a layer of non-conductive adhesive film is pasted on the front of the metal substrate (the area with the circuit layer), the purpose of which is to insulate the third metal circuit layer and the fifth metal circuit layer; the way of pasting and pressing the non-conductive film Conventional rolling equipment can be used, or it can be pasted in a vacuum environment to prevent air residue during the pasting process; the non-conductive adhesive film is mainly pasted and pressed thermosetting epoxy resin, and epoxy resin can According to the characteristics of the product, non-conductive film with no filler or filler is used;

步骤二十三、研磨不导电胶膜表面 Step 23. Grinding the surface of the non-conductive film

参见图47,在步骤二十二完成不导电胶膜贴压后进行表面研磨,目的是露出第四金属线路层、维持不导电胶膜与第四金属线路层的平整度以及控制不导电胶膜的厚度; Referring to Figure 47, surface grinding is carried out after the non-conductive adhesive film is pasted and pressed in step 22. The purpose is to expose the fourth metal circuit layer, maintain the flatness of the non-conductive adhesive film and the fourth metal circuit layer, and control the non-conductive adhesive film. thickness of;

步骤二十四、不导电胶膜表面金属化预处理 Step 24. Metallization pretreatment on the surface of the non-conductive film

参见图48,对不导电胶膜表面进行金属化预处理,使其表面附着上一层金属化高分子材料或表面粗糙化处理,目的是作为后续金属材料能够镀上去的触媒转换,附着金属化高分子材料可以采用喷涂、等离子震荡、表面粗化等再行烘干即可; Referring to Figure 48, the metallization pretreatment is carried out on the surface of the non-conductive adhesive film, so that the surface is attached with a layer of metallized polymer material or surface roughening treatment. Polymer materials can be dried by spraying, plasma shock, surface roughening, etc.;

步骤二十五、贴光阻膜作业 Step 25. Paste the photoresist film

参见图49,在步骤二十四完成金属化的金属基板正面及背面贴上可进行曝光显影的光阻膜,目的是为后续金属线路图形的制作,光阻膜可以是干式光阻膜也可以是湿式光阻膜; Referring to Figure 49, the front and back sides of the metallized metal substrate completed in step 24 are pasted with a photoresist film that can be exposed and developed for the purpose of making subsequent metal circuit patterns. The photoresist film can be dry photoresist film or Can be a wet photoresist film;

步骤二十六、金属基板正面去除部分光阻膜 Step 26. Remove part of the photoresist film from the front of the metal substrate

参见图50,利用曝光显影设备将步骤二十五完成贴光阻膜作业的金属基板正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板正面后续需要进行蚀刻的区域图形; Referring to FIG. 50 , use the exposure and developing equipment to expose, develop and remove part of the graphic photoresist film on the front of the metal substrate that has completed the photoresist film pasting operation in step 25, so as to expose the area pattern that needs to be etched later on the front of the metal substrate;

步骤二十七、蚀刻 Step 27. Etching

参见图51,将步骤二十六中的金属基板正面光阻膜开窗后的区域进行蚀刻作业,其目的是利用腐蚀技术腐蚀去除后续不需要进行电镀第五金属线路层的金属化预处理区域,进行蚀刻的方法可以是氯化铜或是氯化铁的工艺方式; Referring to Figure 51, the etching operation is carried out on the area after the window opening of the photoresist film on the front of the metal substrate in step 26, the purpose of which is to use etching technology to etch and remove the subsequent metallization pretreatment area that does not need to be electroplated with the fifth metal circuit layer , the etching method can be copper chloride or ferric chloride process;

步骤二十八、去除光阻膜 Step 28, remove the photoresist film

参见图52,去除金属基板表面的光阻膜,去除光阻膜的方法采用化学药水软化并采用高压水冲洗即可; Referring to Figure 52, remove the photoresist film on the surface of the metal substrate. The method of removing the photoresist film is softened by chemical potion and rinsed with high-pressure water;

步骤二十九、电镀第五金属线路层 Step 29, electroplating the fifth metal circuit layer

参见图53,在步骤二十七中金属基板正面经蚀刻后保留的金属化预处理区域电镀上第五金属线路层,第五金属线路层电镀完成后即在金属基板正面形成相应的基岛和引脚,第五金属线路层的材质可以是铜、铝、镍、银、金、铜银、镍金或镍钯金等,电镀方式可以是电解电镀也可以采用化学沉积的方式; Referring to Fig. 53, in step 27, the metallized pretreatment area remaining after etching the front side of the metal substrate is electroplated with the fifth metal circuit layer. After the electroplating of the fifth metal circuit layer is completed, the corresponding base island and The pin, the material of the fifth metal circuit layer can be copper, aluminum, nickel, silver, gold, copper silver, nickel gold or nickel palladium gold, etc., and the electroplating method can be electrolytic plating or chemical deposition;

步骤三十、贴光阻膜作业 Step 30: Paste the photoresist film

参见图54,在步骤二十九完成电镀第五金属线路层的金属基板正面贴上可进行曝光显影的光阻膜,目的是为后续导电柱子的制作,光阻膜可以是干式光阻膜也可以是湿式光阻膜; Referring to Fig. 54, in step 29, the metal substrate on which the fifth metal circuit layer is electroplated is pasted with a photoresist film that can be exposed and developed for the purpose of making subsequent conductive pillars. The photoresist film can be a dry photoresist film It can also be a wet photoresist film;

步骤三十一、金属基板正面去除部分光阻膜 Step 31. Remove part of the photoresist film from the front of the metal substrate

参见图55,利用曝光显影设备将步骤三十完成贴光阻膜作业的金属基板正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板正面后续需要进行导电柱子电镀的区域; Referring to FIG. 55 , use the exposure and development equipment to expose, develop and remove part of the graphic photoresist film on the front of the metal substrate that has completed the photoresist film pasting operation in step 30, so as to expose the area on the front of the metal substrate that needs to be electroplated with conductive pillars;

步骤三十二、电镀导电柱子 Step 32. Plating conductive pillars

参见图56,在步骤三十一中金属基板正面去除部分光阻膜的区域内电镀上导电柱子,导电柱子的材质可以是铜、铝、镍、银、金、铜银、镍金、镍钯金或可以达到导电功能的金属物质等材料,电镀方式可以是电解电镀也可以采用化学沉积的方式; Referring to Figure 56, electroplate conductive pillars in the area where part of the photoresist film is removed from the front of the metal substrate in step 31. The material of the conductive pillars can be copper, aluminum, nickel, silver, gold, copper silver, nickel gold, nickel palladium For materials such as gold or metal substances that can achieve conductive functions, the electroplating method can be electrolytic plating or chemical deposition;

步骤三十三、去除光阻膜 Step 33. Remove the photoresist film

参见图57,去除金属基板表面的光阻膜,去除光阻膜的方法采用化学药水软化并采用高压水冲洗即可; Referring to Figure 57, remove the photoresist film on the surface of the metal substrate. The method of removing the photoresist film is softened by chemical potion and rinsed with high-pressure water;

步骤三十四、装片 Step thirty-four, loading film

参见图58,在步骤二十九形成的基岛正面涂覆导电或不导电粘结物质进行第一芯片的植入; Referring to FIG. 58, the front surface of the base island formed in step 29 is coated with a conductive or non-conductive adhesive substance to implant the first chip;

步骤三十五、金属线键合 Step 35. Metal wire bonding

参见图59,在第一芯片正面与步骤五形成的引脚之间进行键合金属线作业; Referring to FIG. 59, perform bonding metal wire operation between the front surface of the first chip and the pins formed in step five;

步骤三十六、环氧树脂塑封 Step 36: Epoxy resin molding

参见图60,在完成装片打线后的金属基板正面进行环氧树脂塑封保护,环氧树脂材料可以依据产品特性选择有填料或是没有填料的种类; Referring to Figure 60, the front of the metal substrate after chip mounting and wire bonding is protected by epoxy resin molding. The epoxy resin material can be selected with or without filler according to product characteristics;

步骤三十七、环氧树脂表面研磨 Step thirty-seven, epoxy resin surface grinding

参见图61,在步骤三十六完成环氧树脂塑封后进行表面研磨; Referring to FIG. 61 , perform surface grinding after epoxy resin molding is completed in step 36;

步骤三十八、贴光阻膜作业 Step 38. Paste photoresist film

参见图62,在步骤三十七完成环氧树脂表面研磨后的金属基板正面和背面贴上可进行曝光显影的光阻膜; Referring to FIG. 62 , in step 37, the front and back of the metal substrate after the surface grinding of the epoxy resin is pasted with a photoresist film that can be exposed and developed;

步骤三十九、金属基板背面去除部分光阻膜 Step 39. Remove part of the photoresist film on the back of the metal substrate

参见图63,利用曝光显影设备将步骤三十八完成贴光阻膜作业的金属基板背面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板背面后续需要进行蚀刻的区域; Referring to FIG. 63 , use the exposure and development equipment to expose, develop and remove part of the graphic photoresist film on the back of the metal substrate that has completed the photoresist film pasting operation in step 38, so as to expose the area that needs to be etched later on the back of the metal substrate;

步骤四十、蚀刻 Step 40: Etching

参见图64,在步骤三十九中金属基板背面去除部分光阻膜的区域进行化学蚀刻,蚀刻的方法可以是氯化铜或是氯化铁的工艺方式; Referring to FIG. 64 , chemical etching is performed on the area where part of the photoresist film is removed on the back of the metal substrate in step 39, and the etching method can be copper chloride or ferric chloride;

步骤四十一、去除光阻膜 Step 41. Remove the photoresist film

参见图65,去除金属基板表面的光阻膜,去除光阻膜的方法采用化学药水软化并采用高压水冲洗即可; Referring to Figure 65, remove the photoresist film on the surface of the metal substrate. The method of removing the photoresist film is softened by chemical potion and rinsed with high-pressure water;

步骤四十二、金属基板背面披覆绿漆或可感光的不导电胶材 Step 42. Cover the back of the metal substrate with green paint or photosensitive non-conductive adhesive

参见图66,在步骤四十一去除光阻膜后的金属基板背面进行绿漆或可感光的不导电胶材的披覆; Referring to FIG. 66 , the back of the metal substrate after removing the photoresist film in step 41 is coated with green paint or photosensitive non-conductive adhesive;

步骤四十三、曝光开窗显影 Step 43: Exposure, window development

参见图67,利用曝光显影设备对金属基板背面披覆的绿漆或可感光的不导电胶材进行曝光显影开窗,以露出金属基板背面后续需要进行高导电金属层电镀的区域; Referring to Figure 67, use exposure and development equipment to expose and develop the green paint or photosensitive non-conductive adhesive material coated on the back of the metal substrate to expose the area on the back of the metal substrate that needs to be electroplated with a high-conductivity metal layer;

步骤四十四、电镀高导电金属层 Step 44: Plating a highly conductive metal layer

参见图68,在步骤四十三中金属基板背面绿漆或可感光的不导电胶材的开窗区域内电镀上高导电金属层,电镀方式可以是电解电镀也可以采用化学沉积的方式; Referring to Figure 68, in step 43, electroplate a highly conductive metal layer in the window area of the green paint on the back of the metal substrate or photosensitive non-conductive adhesive material, the electroplating method can be electrolytic plating or chemical deposition;

步骤四十五、电镀抗氧化金属层或披覆抗氧化剂(OSP) Step forty-five, electroplating anti-oxidation metal layer or coating anti-oxidant (OSP)

参见图69,在金属基板表面裸露在外的金属表面进行抗氧化金属层电镀,如金、镍金、镍钯金、锡或是被覆抗氧化剂(OSP); Referring to Figure 69, an anti-oxidation metal layer is electroplated on the exposed metal surface of the metal substrate, such as gold, nickel gold, nickel palladium gold, tin or coated antioxidant (OSP);

步骤四十六、堆叠封装体 Step 46. Stack Packages

参见图70,在步骤四十五完成电镀抗氧化金属层或披覆抗氧化剂的导电柱子顶部通过导电物质进行封装体的堆叠; Referring to FIG. 70 , in step 45, the electroplating anti-oxidation metal layer or the top of the conductive pillar covered with anti-oxidant is stacked with a conductive substance;

步骤四十七、切割成品 Step forty-seven, cut the finished product

参见图71,将步骤四十三完成封装体堆叠的半成品进行切割作业,使原本以阵列式集合体方式集成在一起并含有芯片的塑封体模块一颗颗切割独立开来,制得先封后蚀三维系统级芯片正装堆叠封装结构成品。 Referring to Figure 71, the semi-finished product stacked in step 43 is cut, so that the plastic package modules that are originally integrated in the form of an array assembly and contain chips are cut and separated one by one, and the first-sealed and later-packed The three-dimensional system-on-a-chip stacked package structure is finished.

实施例3:单层线路+引脚背面堆叠L型封装体 Example 3: Single-layer circuit + backside stacked L-shaped package with pins

参见图73,实施例3与实施例1的区别在于,所述封装体10堆叠于引脚背面抗氧化层上。 Referring to FIG. 73 , the difference between Embodiment 3 and Embodiment 1 is that the package body 10 is stacked on the anti-oxidation layer on the back of the pin.

实施例4:单层线路+J型脚封装体 Embodiment 4: Single-layer circuit + J-shaped pin package

参见图74,实施例4与实施例1的区别在于:所述封装体10的外脚为J型脚。 Referring to FIG. 74 , the difference between Embodiment 4 and Embodiment 1 is that the outer legs of the package body 10 are J-shaped legs.

实施例5:单层线路+平脚封装体 Embodiment 5: Single-layer circuit + flat-pin package

参见图75,实施例5与实施例1的区别在于:所述封装体10的外脚为平脚。 Referring to FIG. 75 , the difference between Embodiment 5 and Embodiment 1 is that the outer legs of the package body 10 are flat legs.

实施例6:单层线路+球栅封装体 Example 6: Single-layer circuit + ball grid package

参见图76,实施例6与实施例1的区别在于:所述封装体10的外脚为金属球。 Referring to FIG. 76 , the difference between Embodiment 6 and Embodiment 1 is that the outer legs of the package body 10 are metal balls.

实施例7:单层线路凸点封装(1) Example 7: Single-layer circuit bump packaging (1)

参见图77,实施例7与实施例3的区别在于:所述导电柱子3顶部设置有金属球13。 Referring to FIG. 77 , the difference between Embodiment 7 and Embodiment 3 is that: a metal ball 13 is arranged on the top of the conductive pillar 3 .

实施例8:单层线路凸点封装(2) Example 8: Single-layer circuit bump packaging (2)

参见图78,实施例8与实施例1的区别在于:所述基岛1和引脚2背面设置有金属球13。 Referring to FIG. 78 , the difference between Embodiment 8 and Embodiment 1 is that metal balls 13 are provided on the back of the base island 1 and pins 2 .

实施例9:多层引线框架堆叠封装体 Embodiment 9: Multi-layer lead frame stacked package

参见图79,实施例9与实施例1的区别在于:所述封装体10安装于导电柱子3顶部,所述封装体10由单个或多个引线框结构10.1与封装体结构10.2堆叠而成。 Referring to FIG. 79 , the difference between Embodiment 9 and Embodiment 1 is that the package 10 is mounted on the top of the conductive pillar 3, and the package 10 is formed by stacking a single or multiple lead frame structures 10.1 and package structures 10.2.

Claims (3)

1.一种先封后蚀三维系统级芯片正装堆叠封装结构的工艺方法,其特征在于所述方法包括以下步骤: 1. A method for encapsulating and then etching a three-dimensional system-on-a-chip stacked packaging structure, characterized in that the method comprises the following steps: 步骤一、取金属基板 Step 1. Take the metal substrate 步骤二、金属基板表面预镀铜材 Step 2. Pre-plating copper on the surface of the metal substrate 在金属基板表面预镀一层铜材, Pre-plating a layer of copper on the surface of the metal substrate, 步骤三、贴光阻膜作业 Step 3: Paste the photoresist film 在步骤二完成预镀铜材的金属基板正面及背面分别贴上可进行曝光显影的光阻膜; In step 2, a photoresist film that can be exposed and developed is pasted on the front and back of the metal substrate of the pre-plated copper material; 步骤四、金属基板正面去除部分光阻膜 Step 4. Remove part of the photoresist film from the front of the metal substrate 利用曝光显影设备将步骤三完成贴光阻膜作业的金属基板正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板正面后续需要进行金属线路层电镀的区域; Use exposure and developing equipment to expose, develop and remove part of the graphic photoresist film on the front of the metal substrate that has completed the photoresist film pasting operation in step 3, so as to expose the area that needs to be electroplated on the metal circuit layer on the front of the metal substrate; 步骤五、电镀金属线路层 Step 5. Plating metal circuit layer 在步骤四中金属基板正面去除部分光阻膜的区域内电镀上金属线路层,金属线路层电镀完成后即在金属基板正面形成相应的基岛和引脚; Electroplate a metal circuit layer in the area where part of the photoresist film is removed from the front of the metal substrate in step 4. After the electroplating of the metal circuit layer is completed, corresponding base islands and pins are formed on the front of the metal substrate; 步骤六、贴光阻膜作业 Step 6. Paste photoresist film 在步骤五完成电镀金属线路层的金属基板正面贴上可进行曝光显影的光阻膜; In step 5, a photoresist film that can be exposed and developed is pasted on the front side of the metal substrate on which the electroplated metal circuit layer is completed; 步骤七、金属基板正面去除部分光阻膜 Step 7. Remove part of the photoresist film from the front of the metal substrate 利用曝光显影设备将步骤六完成贴光阻膜作业的金属基板正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板正面后续需要进行导电柱子电镀的区域; Use exposure and developing equipment to expose, develop and remove part of the patterned photoresist film on the front of the metal substrate that has completed the photoresist film pasting operation in step 6, so as to expose the area on the front of the metal substrate that needs to be electroplated with conductive pillars; 步骤八、电镀导电柱子 Step 8. Plating conductive pillars 在步骤七中金属基板正面去除部分光阻膜的区域内电镀上导电柱子; Electroplate conductive pillars in the area where part of the photoresist film is removed from the front of the metal substrate in step 7; 步骤九、去除光阻膜 Step 9. Remove the photoresist film 去除金属基板表面的光阻膜; Remove the photoresist film on the surface of the metal substrate; 步骤十、装片 Step ten, loading film 在步骤五形成的基岛正面涂覆导电或不导电粘结物质进行芯片的植入; Coating conductive or non-conductive bonding substances on the front side of the base island formed in step 5 for chip implantation; 步骤十一、金属线键合 Step 11. Wire Bonding 在第一芯片正面与步骤五形成的引脚之间进行键合金属线作业; Carry out bonding wire operation between the front surface of the first chip and the pins formed in step five; 步骤十二、环氧树脂塑封 Step 12. Epoxy resin plastic sealing 在完成装片打线后的金属基板正面进行环氧树脂塑封保护; Epoxy resin plastic sealing protection is carried out on the front of the metal substrate after chip loading and wiring; 步骤十三、环氧树脂表面研磨 Step 13. Epoxy resin surface grinding 在步骤十二完成环氧树脂塑封后进行表面研磨; Surface grinding is carried out after completing the epoxy resin molding in step 12; 步骤十四、贴光阻膜作业 Step 14. Paste photoresist film 在步骤十三完成环氧树脂表面研磨后的金属基板正面和背面贴上可进行曝光显影的光阻膜; In step 13, a photoresist film that can be exposed and developed is pasted on the front and back of the metal substrate after the epoxy resin surface is ground; 步骤十五、金属基板背面去除部分光阻膜 Step 15. Remove part of the photoresist film on the back of the metal substrate 利用曝光显影设备将步骤十四完成贴光阻膜作业的金属基板背面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板背面后续需要进行蚀刻的区域; Use the exposure and development equipment to expose, develop and remove part of the graphic photoresist film on the back of the metal substrate that has been pasted with the photoresist film in step 14, so as to expose the area that needs to be etched later on the back of the metal substrate; 步骤十六、蚀刻 Step 16. Etching 在步骤十五中金属基板背面去除部分光阻膜的区域进行化学蚀刻; Perform chemical etching in the region where part of the photoresist film is removed on the back of the metal substrate in step fifteen; 步骤十七、去除光阻膜 Step seventeen, remove the photoresist film 去除金属基板表面的光阻膜; Remove the photoresist film on the surface of the metal substrate; 步骤十八、金属基板背面披覆绿漆或可感光的不导电胶材 Step 18. Cover the back of the metal substrate with green paint or photosensitive non-conductive adhesive 在步骤十七去除光阻膜后的金属基板背面进行绿漆或可感光的不导电胶材的披覆; Apply green paint or photosensitive non-conductive adhesive to the back of the metal substrate after removing the photoresist film in step seventeen; 步骤十九、曝光开窗显影 Step 19: Exposure, window development 利用曝光显影设备对金属基板背面披覆的绿漆或可感光的不导电胶材进行曝光显影开窗,以露出金属基板背面后续需要进行高导电金属层电镀的区域; Use exposure and development equipment to expose and develop the green paint or photosensitive non-conductive adhesive on the back of the metal substrate to expose the area on the back of the metal substrate that needs to be electroplated with a high-conductivity metal layer; 步骤二十、电镀高导电金属层 Step 20: Plating a highly conductive metal layer 在步骤十九中金属基板背面绿漆或可感光的不导电胶材的开窗区域内电镀上高导电金属层; Electroplate a highly conductive metal layer in the window area of the green paint on the back of the metal substrate or photosensitive non-conductive adhesive in step 19; 步骤二十一、披覆抗氧化剂 Step 21: Coating Antioxidant 在金属基板表面裸露在外的金属表面进行抗氧化剂披覆; Antioxidant coating on the exposed metal surface of the metal substrate; 步骤二十二、堆叠封装体 Step 22. Stack Packages 在步骤二十一完成披覆抗氧化剂的导电柱子顶部通过导电物质进行封装体的堆叠; In step 21, the top of the conductive pillar covered with antioxidant is completed and the package is stacked through a conductive substance; 步骤二十三、切割成品 Step 23. Cut the finished product 将步骤二十二完成封装体堆叠的半成品进行切割作业,使原本以阵列式集合体方式集成在一起并含有芯片的塑封体模块一颗颗切割独立开来,制得先封后蚀三维系统级芯片正装堆叠封装结构成品。 Cutting the semi-finished products that have been stacked in step 22, so that the plastic package modules that were originally integrated in the form of an array assembly and containing chips are cut and separated one by one to obtain a three-dimensional system level that is sealed first and etched later. The chip is mounted on a stacked package structure. 2.一种先封后蚀三维系统级芯片正装堆叠封装结构的工艺方法,其特征在于所述方法包括以下步骤: 2. A method for encapsulating first and then etching a three-dimensional system-on-a-chip stacked package structure, characterized in that the method comprises the following steps: 步骤一、取金属基板 Step 1. Take the metal substrate 步骤二、金属基板表面预镀铜材 Step 2. Pre-plating copper on the surface of the metal substrate 在金属基板表面预镀一层铜材; Pre-plating a layer of copper on the surface of the metal substrate; 步骤三、贴光阻膜作业 Step 3: Paste the photoresist film 在步骤二完成预镀铜材的金属基板正面及背面分别贴上可进行曝光显影的光阻膜; In step 2, a photoresist film that can be exposed and developed is pasted on the front and back of the metal substrate of the pre-plated copper material; 步骤四、金属基板正面去除部分光阻膜 Step 4. Remove part of the photoresist film from the front of the metal substrate 利用曝光显影设备将步骤三完成贴光阻膜作业的金属基板正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板正面后续需要进行第一金属线路层电镀的区域; Using exposure and development equipment, the front of the metal substrate that has completed the photoresist film pasting operation in step 3 is subjected to pattern exposure, development and removal of part of the pattern photoresist film, so as to expose the area on the front of the metal substrate that needs to be electroplated for the first metal circuit layer; 步骤五、电镀第一金属线路层 Step 5. Electroplating the first metal circuit layer 在步骤四中金属基板正面去除部分光阻膜的区域内电镀上第一金属线路层; Electroplating the first metal circuit layer in the area where part of the photoresist film is removed from the front of the metal substrate in step 4; 步骤六、贴光阻膜作业 Step 6. Paste photoresist film 在步骤五完成电镀第一金属线路层的金属基板正面贴上可进行曝光显影的光阻膜; In step 5, a photoresist film that can be exposed and developed is pasted on the front side of the metal substrate that has electroplated the first metal circuit layer; 步骤七、金属基板正面去除部分光阻膜 Step 7. Remove part of the photoresist film from the front of the metal substrate 利用曝光显影设备将步骤六完成贴光阻膜作业的金属基板正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板正面后续需要进行第二金属线路层电镀的区域; Use exposure and development equipment to expose, develop and remove part of the graphic photoresist film on the front of the metal substrate that has completed the photoresist film pasting operation in step 6, so as to expose the area that needs to be electroplated on the second metal circuit layer on the front of the metal substrate; 步骤八、电镀第二金属线路层 Step 8. Electroplating the second metal circuit layer 在步骤七中金属基板正面去除部分光阻膜的区域内电镀上第二金属线路层作为用以连接第一金属线路层与第三金属线路层的导电柱子; Electroplating the second metal circuit layer in the area where part of the photoresist film is removed on the front side of the metal substrate in step 7 as a conductive pillar for connecting the first metal circuit layer and the third metal circuit layer; 步骤九、去除光阻膜 Step 9. Remove the photoresist film 去除金属基板表面的光阻膜; Remove the photoresist film on the surface of the metal substrate; 步骤十、贴压不导电胶膜 Step 10. Paste and press the non-conductive film 在金属基板正面贴压一层不导电胶膜; Paste a layer of non-conductive adhesive film on the front of the metal substrate; 步骤十一、研磨不导电胶膜表面 Step 11. Grinding the surface of the non-conductive film 在步骤十完成不导电胶膜贴压后进行表面研磨; Surface grinding is carried out after the non-conductive adhesive film is pasted and pressed in step ten; 步骤十二、不导电胶膜表面金属化预处理 Step 12. Metallization pretreatment on the surface of the non-conductive film 对不导电胶膜表面进行金属化预处理,使其表面附着上一层金属化高分子材料或使其表面粗糙化; Carry out metallization pretreatment on the surface of the non-conductive adhesive film, so that the surface is attached with a layer of metallized polymer material or the surface is roughened; 步骤十三、贴光阻膜作业 Step 13. Paste photoresist film 在步骤十二完成金属化预处理的金属基板正面及背面贴上可进行曝光显影的光阻膜; Paste a photoresist film that can be exposed and developed on the front and back of the metal substrate that has completed the metallization pretreatment in step 12; 步骤十四、金属基板正面去除部分光阻膜 Step 14. Remove part of the photoresist film from the front of the metal substrate 利用曝光显影设备将步骤十三完成贴光阻膜作业的金属基板正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板正面后续需要进行蚀刻的区域图形; Exposing, developing and removing part of the graphic photoresist film on the front of the metal substrate on which the photoresist film pasting operation has been completed in step 13 by using exposure and developing equipment, so as to expose the pattern of the area on the front of the metal substrate that needs to be etched later; 步骤十五、蚀刻 Step 15. Etching 将步骤十四中的金属基板正面光阻膜开窗后的区域进行蚀刻作业; Etching the area after opening the photoresist film on the front of the metal substrate in step 14; 步骤十六、去除光阻膜 Step sixteen, remove the photoresist film 去除金属基板表面的光阻膜; Remove the photoresist film on the surface of the metal substrate; 步骤十七、电镀第三金属线路层 Step seventeen, electroplating the third metal circuit layer 在步骤十五中金属基板正面经蚀刻后保留的金属化预处理区域电镀上第三金属线路层,第三金属线路层电镀完成后即在金属基板正面形成相应的基岛和引脚; In step 15, the metallized pretreatment area retained after etching on the front side of the metal substrate is electroplated with a third metal circuit layer, and after the electroplating of the third metal circuit layer is completed, corresponding base islands and pins are formed on the front side of the metal substrate; 步骤十八、贴光阻膜作业 Step 18. Paste photoresist film 在步骤十七完成电镀第三金属线路层的金属基板正面贴上可进行曝光显影的光阻膜; In step 17, a photoresist film that can be exposed and developed is pasted on the front side of the metal substrate on which the electroplating of the third metal circuit layer is completed; 步骤十九、金属基板正面去除部分光阻膜 Step 19. Remove part of the photoresist film from the front of the metal substrate 利用曝光显影设备将步骤十八完成贴光阻膜作业的金属基板正面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板正面后续需要进行导电柱子电镀的区域; Using the exposure and developing equipment, perform graphic exposure, development and removal of part of the graphic photoresist film on the front of the metal substrate after step 18 has completed the operation of pasting the photoresist film, so as to expose the area on the front of the metal substrate that needs to be electroplated with conductive pillars; 步骤二十、电镀导电柱子 Step 20: Plating conductive pillars 在步骤十九中金属基板正面去除部分光阻膜的区域内电镀上导电柱子; Electroplate conductive pillars in the area where part of the photoresist film is removed from the front of the metal substrate in step 19; 步骤二十一、去除光阻膜 Step 21. Remove the photoresist film 去除金属基板表面的光阻膜; Remove the photoresist film on the surface of the metal substrate; 步骤二十二、装片 Step 22, loading film 在步骤十七形成的基岛正面涂覆导电或不导电粘结物质进行第一芯片的植入; Coating conductive or non-conductive adhesive substance on the front side of the base island formed in step 17 to implant the first chip; 步骤二十三、金属线键合 Step 23. Metal wire bonding 在第一芯片正面与步骤五形成的引脚之间进行键合金属线作业; Carry out bonding wire operation between the front surface of the first chip and the pins formed in step five; 步骤二十四、环氧树脂塑封 Step 24: Epoxy resin molding 在完成装片打线后的金属基板正面进行环氧树脂塑封保护; Epoxy resin plastic sealing protection is carried out on the front of the metal substrate after chip loading and wiring; 步骤二十五、环氧树脂表面研磨 Step 25. Epoxy resin surface grinding 在步骤二十四完成环氧树脂塑封后进行表面研磨; Surface grinding is carried out after epoxy resin molding is completed in step 24; 步骤二十六、贴光阻膜作业 Step 26. Paste the photoresist film 在步骤二十五完成环氧树脂表面研磨后的金属基板正面和背面贴上可进行曝光显影的光阻膜; Paste a photoresist film that can be exposed and developed on the front and back of the metal substrate after the epoxy resin surface is ground in step 25; 步骤二十七、金属基板背面去除部分光阻膜 Step 27. Remove part of the photoresist film on the back of the metal substrate 利用曝光显影设备将步骤二十六完成贴光阻膜作业的金属基板背面进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板背面后续需要进行蚀刻的区域; Use the exposure and development equipment to expose, develop and remove part of the graphic photoresist film on the back of the metal substrate after the photoresist film pasting operation in step 26, so as to expose the area that needs to be etched later on the back of the metal substrate; 步骤二十八、蚀刻 Step 28. Etching 在步骤二十七中金属基板背面去除部分光阻膜的区域进行化学蚀刻; Perform chemical etching on the area where part of the photoresist film is removed on the back of the metal substrate in step 27; 步骤二十九、去除光阻膜 Step 29. Remove the photoresist film 去除金属基板表面的光阻膜; Remove the photoresist film on the surface of the metal substrate; 步骤三十、金属基板背面披覆绿漆或可感光的不导电胶材 Step 30. Cover the back of the metal substrate with green paint or photosensitive non-conductive adhesive 在步骤二十九去除光阻膜后的金属基板背面进行绿漆或可感光的不导电胶材的披覆; After removing the photoresist film in step 29, coat the back of the metal substrate with green paint or photosensitive non-conductive adhesive; 步骤三十一、曝光开窗显影 Step 31: Exposure, window development 利用曝光显影设备对金属基板背面披覆的绿漆或可感光的不导电胶材进行曝光显影开窗,以露出金属基板背面后续需要进行高导电金属层电镀的区域; Use exposure and development equipment to expose and develop the green paint or photosensitive non-conductive adhesive on the back of the metal substrate to expose the area on the back of the metal substrate that needs to be electroplated with a high-conductivity metal layer; 步骤三十二、电镀高导电金属层 Step thirty-two, electroplating a highly conductive metal layer 在步骤三十一中金属基板背面绿漆或可感光的不导电胶材的开窗区域内电镀上高导电金属层; Electroplate a highly conductive metal layer in the window area of the green paint on the back of the metal substrate or photosensitive non-conductive adhesive in step 31; 步骤三十三、抗氧化剂披覆 Step 33: Antioxidant Coating 在金属基板表面裸露在外的金属表面进行抗氧化剂披覆; Antioxidant coating on the exposed metal surface of the metal substrate; 步骤三十四、堆叠封装体 Step 34. Stack Packages 在步骤三十三完成披覆抗氧化剂的导电柱子顶部通过导电物质进行封装体的堆叠; In step 33, complete the stacking of packages through conductive substances on top of the conductive pillars coated with antioxidants; 步骤三十五、切割成品 Step 35. Cut the finished product 将步骤三十四完成封装体堆叠的半成品进行切割作业,使原本以阵列式集合体方式集成在一起并含有芯片的塑封体模块一颗颗切割独立开来,制得先封后蚀三维系统级芯片正装堆叠封装结构成品。 The semi-finished product stacked in step 34 is cut, so that the plastic package modules that are originally integrated in the form of an array assembly and contain chips are cut and separated one by one, and the three-dimensional system level that is sealed first and etched later is obtained. The chip is mounted on a stacked package structure. 3.根据权利要求2所述的一种先封后蚀三维系统级芯片正装堆叠封装结构的工艺方法,其特征在于:所述步骤六~步骤十七在步骤五与步骤十八之间重复进行多次。 3. The process method of sealing first and then etching a three-dimensional system-on-a-chip stacked package structure according to claim 2, characterized in that: the steps 6 to 17 are repeated between steps 5 and 18 repeatedly.
CN201310340418.2A 2013-08-06 2013-08-06 First it is honored as a queen and loses three-dimensional systematic chip formal dress stack package structure and process Active CN103441078B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310340418.2A CN103441078B (en) 2013-08-06 2013-08-06 First it is honored as a queen and loses three-dimensional systematic chip formal dress stack package structure and process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310340418.2A CN103441078B (en) 2013-08-06 2013-08-06 First it is honored as a queen and loses three-dimensional systematic chip formal dress stack package structure and process

Publications (2)

Publication Number Publication Date
CN103441078A CN103441078A (en) 2013-12-11
CN103441078B true CN103441078B (en) 2016-08-17

Family

ID=49694766

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310340418.2A Active CN103441078B (en) 2013-08-06 2013-08-06 First it is honored as a queen and loses three-dimensional systematic chip formal dress stack package structure and process

Country Status (1)

Country Link
CN (1) CN103441078B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105185764B (en) * 2015-10-08 2017-09-12 江苏长电科技股份有限公司 Spring pins POP structures and process
CN108231729B (en) * 2017-12-29 2020-07-14 通富微电子股份有限公司 Packaging substrate, chip packaging body and chip stacking and packaging method
CN111834330B (en) * 2020-06-30 2025-07-04 江苏长电科技股份有限公司 A semiconductor packaging structure and manufacturing process thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1921108A (en) * 2005-08-23 2007-02-28 新光电气工业株式会社 Semiconductor package and manufacturing method thereof
CN102386104A (en) * 2010-09-01 2012-03-21 群成科技股份有限公司 Quad flat non-leaded package method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4072505B2 (en) * 2003-02-28 2008-04-09 エルピーダメモリ株式会社 Stacked semiconductor package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1921108A (en) * 2005-08-23 2007-02-28 新光电气工业株式会社 Semiconductor package and manufacturing method thereof
CN102386104A (en) * 2010-09-01 2012-03-21 群成科技股份有限公司 Quad flat non-leaded package method

Also Published As

Publication number Publication date
CN103441078A (en) 2013-12-11

Similar Documents

Publication Publication Date Title
CN103489792B (en) First be honored as a queen and lose three-dimensional systematic flip chip encapsulation structure and process
CN103456645B (en) First lose and seal three-dimensional systematic chip afterwards and just filling stack package structure and processing method
CN103390563B (en) Erosion flip-chip of being first honored as a queen three-dimensional systematic metal circuit board structure &processes method
CN103400767B (en) First sealing chip flipchip bump three-dimensional systematic metal circuit board and process after erosion
CN107622996B (en) Three-dimensional high-density fan-out type packaging structure and manufacturing method thereof
CN103794587A (en) Embedded type rewiring line packaging structure of chip with good heat dissipation performance and manufacturing method thereof
CN103400775B (en) First it is honored as a queen and loses three-dimensional systematic flip-chip bump packaging structure and process
CN103400770B (en) First be honored as a queen and lose flip-chip salient point three-dimensional systematic metal circuit board and process
CN103441078B (en) First it is honored as a queen and loses three-dimensional systematic chip formal dress stack package structure and process
CN103515249B (en) First be honored as a queen and lose three-dimensional systematic chip formal dress bump packaging structure and process
CN103400769B (en) First lose and seal three-dimensional systematic flip-chip bump packaging structure and process afterwards
CN103400777A (en) Packaging-prior-to-etching chip-normally-bonded bump type three-dimensional system-level metal circuit board and process method thereof
CN103400776B (en) First lose and seal three-dimensional systematic flip chip encapsulation structure and process afterwards
CN103311216B (en) High-density multi-layered circuit chip flip-chip packaged structure and manufacture method
CN102867791B (en) Multi-chip reversely-arranged etched-encapsulated base island-buried encapsulating structure and manufacturing method thereof
CN103400768B (en) First lose and seal three-dimensional systematic chip formal dress encapsulating structure and process afterwards
CN103413767B (en) First be honored as a queen and lose chip formal dress three-dimensional system level packaging structure and process
CN102867802B (en) Multi-chip reversely-arranged etched-encapsulated base island-exposed encapsulating structure and manufacturing method thereof
CN102856284B (en) Multi-chip flip, etching-after-packaging and pad exposed packaging structure and manufacturing method thereof
CN103681582A (en) One-time eroding-before-plating metal frame subtraction embedded chip normally-arranged salient point structure and technological method
CN103681580B (en) Etching-prior-to-plametal metal frame subtraction imbedded chip flipchip bump structure and process
CN102856291B (en) First etched and then packaged packaging structure with multiple chips normally installed and without base islands as well as preparation method thereof
CN103390567B (en) First lose and seal three-dimensional systematic chip formal dress bump packaging structure and process afterwards
CN103400774B (en) First be honored as a queen and lose chip formal dress salient point three-dimensional systematic metal circuit board and process
CN102856292B (en) Single-chip flip, packaging-after-etching and non-pad packaging structure and manufacturing method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20160505

Address after: 214434 Jiangyin, Jiangsu, Chengjiang city street, Long Hill Road, No. 78

Applicant after: Jiangsu Changjiang Electronics Technology Co., Ltd.

Address before: 214434 Jiangyin, Jiangsu Province, the development of mountain road, No. 78, No.

Applicant before: Jiangsu Changjiang Electronics Technology Co., Ltd.

C14 Grant of patent or utility model
GR01 Patent grant