CN103440018B - Power control method, power control circuit and energy-saving system - Google Patents

Abstract

The embodiment of the invention provides a power control method, a power control circuit and an energy-saving system. In order to the solve the problems that according to a battery management chip of an existing terminal, when a controller of the terminal is powered down, due to the fact that the terminal can not enter a low-power consumption mode, the power consumption is increased, and the probability that a battery is damaged is increased, the method comprises the steps of being free of generating signals for delayed restarting any more when periodic pulse signals coming from the controller of the terminal are not detected in preset duration, determining the signals which are not generated for the delayed restarting in delayed duration, and after the delayed duration is ended, outputting a conditioning signal of a first level to a low-power consumption mode register in the battery management chip of the terminal, wherein the conditioning signal of the first level can allow the battery management chip to enter the low-power consumption mode.

Description

A power control method, power control circuit and energy-saving system

technical field

The invention relates to the technical field of circuit design, in particular to a power control method, a power control circuit and an energy-saving system.

Background technique

Currently, there are some chips that can run in low power consumption mode. For example, battery management chips can run in low power consumption mode when the battery is not in use (that is, the battery is not charging and does not supply power to the mobile terminal) or the battery power is low. , to save power and prolong battery life. Because when the power of the battery is low, if the battery cannot be charged in time, the chip will continuously take power from the battery, causing the battery to be damaged. If the chip runs in low-power mode when the battery is low, the chances of recharging the battery increase due to the extended battery life, which reduces the chance of battery damage.

There are two commonly used battery management chips at present, one can work in standby mode, measurement mode and monitoring mode. When it is in standby mode, except for the serial port and the voltage regulator circuit, other circuits are in the off state, and the current of the battery management chip is at the minimum state at this time. When it is running in the measurement mode or monitoring mode, if it needs to enter the standby mode, the central processing unit (CPU, Center Processing Unit) will use the serial peripheral interface (SPI, Serial Peripheral Interface) to register the standby mode of the battery management chip The duty cycle configuration bit is set to the level signal required by the standby mode, so that the battery management chip enters the standby mode. Another battery management chip can work in sleep mode. When it works in sleep mode, the chip consumes the least amount of power. The CPU can set the controllable input and output port of the sleep mode register of the battery management chip to a level signal required by the sleep mode through the SPI, so that the battery management chip enters the sleep mode.

When the above two battery management chips enter the low power consumption mode, the CPU needs to write a certain value in the low power consumption mode register of the chip to enter the low power consumption mode. At this time, if the CPU is abnormally powered off, and the CPU has not had time to write the corresponding value to the low-power mode register of the chip, then the chip cannot enter the low-power mode. At this time, the power consumption of the chip will be relatively large, and the battery The power will be quickly drained by the chip, which will increase the chance of the battery being damaged.

To sum up, the existing battery management chip can only enter the low power consumption mode under the control of the terminal controller, such as the CPU, and if the controller loses power abnormally, the battery management chip cannot enter the low power consumption mode. This will cause the battery's power to be drained quickly, resulting in an increased chance of the battery being damaged.

Contents of the invention

The embodiment of the present invention provides a power control method, a power control circuit and an energy-saving system, which are used to solve the problem that the existing battery management chip cannot enter the low power consumption mode when the controller of the terminal is powered off, resulting in increased power consumption , resulting in an increased chance of the battery being damaged.

In a first aspect, a power control method is provided, including:

When the periodic pulse signal from the terminal controller is not detected within the preset duration, the delayed restart signal will no longer be generated;

It is determined that no delayed restart signal is generated within a delay period, and after the delay period ends, an adjustment signal of the first level is output to the low power consumption mode register in the battery management chip of the terminal, and the first level A level adjustment signal can enable the battery management chip to enter a low power consumption mode;

Wherein, the start time of the delay time is earlier than or equal to the end time of the preset time length, the delay time is greater than or equal to the preset time length, and the preset time length is longer than the periodic pulse signal a pulse width.

With reference to the first aspect, in a first possible implementation manner, before it is determined that a delayed restart signal is not generated within a delay period, the method further includes:

When the number of pulses of the periodic pulse signal detected within the preset duration is less than N, the delayed restart signal is no longer generated, wherein the preset duration is equal to the length of N cycles of the periodic pulse signal .

With reference to the first possible implementation of the first aspect, in a second possible implementation, the method further includes:

When the number of pulses of the periodic pulse signal detected within the preset duration is greater than or equal to N, a delayed restart signal is generated;

Within a delay period after the delayed restart signal is generated, an adjustment signal of a second level is output to the low power consumption mode register in the battery management chip, and the adjustment signal of the second level can enable the The signal for the battery management chip to exit the low power consumption mode.

In the second aspect, another power control method is provided, including:

determining that the control signal output by the controller of the terminal has not been received, and the control signal is used to make the battery management chip of the terminal enter a low power consumption mode or exit a low power consumption mode;

Outputting an adjustment signal of a first level to a low power consumption mode register in the battery management chip of the terminal, where the adjustment signal of the first level can cause the battery management chip to enter a low power consumption mode.

With reference to the second aspect, in a first possible implementation manner, before outputting the adjustment signal of the first level to the low power consumption mode register in the battery management chip, the method further includes:

It is determined that the control signal of the first preset voltage output by the controller of the terminal is received.

With reference to the second aspect, in a second possible implementation manner, the method further includes:

determining to receive a control signal of a second preset voltage output by the controller of the terminal;

Outputting an adjustment signal of a second level to a low power consumption mode register in the battery management chip, the second level adjustment signal enables the battery management chip to exit the low power consumption mode.

In a third aspect, a power control circuit is provided, including a detection generation circuit and an output circuit, the detection generation circuit is connected to a port for outputting a periodic pulse signal in the controller of the terminal and the output circuit, and the output circuit is connected to a low power consumption mode register in the battery management chip of the terminal;

The detection generation circuit is configured to no longer generate a delayed restart signal when the periodic pulse signal from the controller of the terminal is not detected within a preset duration; the preset duration is longer than the period of the periodic pulse signal a pulse width;

The output circuit is configured to determine that no delayed restart signal is generated within a delay period, and output the first level to the low power consumption mode register in the battery management chip of the terminal after the delay period ends The adjustment signal of the first level can make the battery management chip enter the low power consumption mode; the start time of the delay time is earlier than or equal to the end time of the preset time length, and the delay time The duration is greater than or equal to the preset duration.

With reference to the third aspect, in a first possible implementation manner, the detection generation circuit is further configured to:

It is determined that before a delayed restart signal is not generated within a delay duration, if the number of pulses of the periodic pulse signal detected within a preset duration is less than N, a delayed restart signal is no longer generated, wherein the preset It is assumed that the duration is equal to the length of N periods of the periodic pulse signal.

With reference to the first possible implementation of the third aspect, in a second possible implementation, the detection generation circuit is further configured to:

When the number of pulses of the periodic pulse signal detected within the preset duration is greater than or equal to N, a delayed restart signal is generated;

The output circuit is further configured to output a second-level adjustment signal to a low-power mode register in the battery management chip within a delay period after the delayed restart signal is generated, and the second power A flat adjustment signal can cause the battery management chip to exit the low power consumption mode.

In a fourth aspect, another power control circuit is provided, including a receiving circuit and a transmission circuit, the receiving circuit is connected to a port for outputting a control signal in the controller of the terminal and the transmission circuit, and the transmission circuit is connected to the terminal The low-power mode register in the battery management chip;

The receiving circuit is configured to receive a control signal output by a controller of the terminal, where the control signal is used to enable the battery management chip of the terminal to enter a low power consumption mode or exit a low power consumption mode;

The transmission circuit is configured to output an adjustment signal of a first level to a low power consumption mode register in the battery management chip when the receiving circuit determines that the control signal output by the controller has not been received, the The adjustment signal of the first level can cause the battery management chip to enter a low power consumption mode.

With reference to the fourth aspect, in a first possible implementation manner, the transmission circuit is further configured to:

When the receiving circuit determines to receive the control signal of the first preset voltage output by the controller, it outputs an adjustment signal of a first level to the low power consumption mode register in the battery management chip, and the first The level adjustment signal can make the battery management chip enter a low power consumption mode.

With reference to the fourth aspect, in a second possible implementation manner, the transmission circuit is also used for:

When the receiving circuit determines to receive the control signal of the second preset voltage output by the controller of the terminal, it outputs an adjustment signal of a second level to the low power consumption mode register in the battery management chip, the said The adjustment signal of the second level can cause the battery management chip to exit the low power consumption mode.

With reference to the fourth aspect, in a third possible implementation manner, the receiving circuit includes a first resistance unit;

One end of the first resistance unit is connected to a port of the controller for outputting a control signal, and the other end of the first resistance unit outputs the received control signal to the transmission unit.

With reference to the fourth aspect, in a fourth possible implementation manner, the transmission circuit includes a second resistance unit and a third resistance unit, one end of the second resistance unit receives a set voltage signal, and the second resistance unit The other end of the second resistance unit is connected to one end of the third resistance unit, and receives the signal of the receiving unit; if the set voltage signal and the adjustment signal of the first level are both high-level signals, or both are low-level signal, the other end of the third resistor unit is connected to the low power consumption mode register in the battery management chip of the terminal.

With reference to the fourth aspect, in a fifth possible implementation manner, if the set voltage signal is a high-level signal, the adjustment signal of the first level is a low-level signal, or the set voltage signal is low-level signal, the adjusted signal of the first level is a high-level signal; then the output circuit also includes an inversion circuit, and the other end of the third resistance unit is connected to the terminal through the inversion circuit Low power mode register in the battery management chip.

A fifth aspect provides an energy-saving system, including a terminal controller, a battery management chip of the terminal, and the third aspect, the first possible implementation of the third aspect to the second possible implementation of the third aspect method, the fourth aspect, and any one of the power control circuits in the first possible implementation manner of the fourth aspect to the fifth possible implementation manner of the fourth aspect.

The beneficial effects of the embodiments of the present invention include:

The embodiment of the present invention provides a power control method, a power control circuit and an energy-saving system. If the controller of the terminal is abnormally powered off and cannot output a periodic pulse signal, then the control signal from the terminal cannot be detected within a preset period of time. When the periodic pulse signal of the device, the delayed restart signal is no longer generated, and it is determined that the delayed restart signal is not generated within a delay time. After the delay time is over, the battery management chip of the terminal The low power consumption mode register outputs an adjustment signal of a first level, and the adjustment signal of the first level can cause the battery management chip to enter a low power consumption mode; Afterwards, the control signal is used to make the battery management chip of the terminal enter the low power consumption mode or exit the low power consumption mode; output the adjustment signal of the first level to the low power consumption mode register in the battery management chip of the terminal, The adjustment signal of the first level can enable the battery management chip to enter a low power consumption mode; thereby enabling the battery management chip of the terminal to enter a low power consumption mode, thereby reducing power consumption, prolonging battery life, and finally reducing battery consumption. chance of damage.

Description of drawings

FIG. 1 is one of the flowcharts of the power control method provided by the embodiment of the present invention;

FIG. 2 is the second flowchart of the power control method provided by the embodiment of the present invention;

FIG. 3 is the third flowchart of the power control method provided by the embodiment of the present invention;

FIG. 4 is the fourth flowchart of the power control method provided by the embodiment of the present invention;

FIG. 5 is the fifth flowchart of the power control method provided by the embodiment of the present invention;

FIG. 6 is the sixth flowchart of the power control method provided by the embodiment of the present invention;

Fig. 7 is one of the flow charts of the power control method provided by the embodiment of the present invention applied in practice;

Fig. 8 is the second flow chart of the power control method provided by the embodiment of the present invention applied in practice;

FIG. 9 is one of the structural schematic diagrams of the power control circuit provided by the embodiment of the present invention;

FIG. 10 is the second structural schematic diagram of the power control circuit provided by the embodiment of the present invention;

Fig. 11 is the third structural schematic diagram of the power control circuit provided by the embodiment of the present invention;

Fig. 12a is the fourth structural schematic diagram of the power control circuit provided by the embodiment of the present invention;

Fig. 12b is the fifth structural schematic diagram of the power control circuit provided by the embodiment of the present invention.

Detailed ways

Embodiments of the present invention provide a power control method, a power control circuit, and an energy-saving system. When the periodic pulse signal from the controller of the terminal is not detected within a preset period of time, it is determined that the controller of the terminal is faulty and cannot be controlled. The battery management chip enters the low power consumption mode and no longer generates a delayed restart signal. If the delayed restart signal is not generated within a delay time, after the delay time ends, the battery management chip of the terminal The low power consumption mode register in the output first level adjustment signal, the adjustment signal of the first level can make the battery management chip enter the low power consumption mode; the start time of the delay time is earlier than or equal to At the end moment of the preset duration, the delay duration is greater than or equal to the preset duration, and the preset duration is longer than a pulse width of the periodic pulse signal. Or, by outputting an adjustment signal of a first level to a low power consumption mode register in the battery management chip of the terminal after determining that the control signal output by the controller of the terminal has not been received, the adjustment of the first level The signal can make the battery management chip enter a low power consumption mode; the control signal is used to make the battery management chip of the terminal enter a low power consumption mode or exit a low power consumption mode, so that the terminal controller fails and cannot When controlling the battery management chip to enter the low-power mode, output the first level adjustment signal to the low-power mode register in the battery management chip of the terminal, and control the battery management chip of the terminal to enter the low-power mode, thereby reducing power consumption .

The specific implementation manners of a power control method, a power control circuit and an energy-saving system provided by the embodiments of the present invention will be described below with reference to the drawings in the description.

A power control method provided by an embodiment of the present invention, as shown in FIG. 1 , specifically includes the following steps:

S101. When the periodic pulse signal from the controller of the terminal is not detected within the preset time period, no longer generate a delayed restart signal;

S102. It is determined that no delayed restart signal is generated within a delay period, and after the delay period ends, an adjustment signal of the first level is output to the low power consumption mode register in the battery management chip of the terminal, the first The level adjustment signal can make the battery management chip enter a low power consumption mode;

Wherein, the start time of the delay time is earlier than or equal to the end time of the preset time length, the delay time length is greater than or equal to the preset time length, and the preset time length is longer than one pulse width of the periodic pulse signal.

In this way, when the controller of the terminal, such as the CPU, is powered off abnormally, since the controller cannot output periodic pulse signals, the battery management chip of the terminal can be controlled to enter a low power consumption mode.

Wherein, the periodic pulse signal may be a clock signal, or other periodic signals. The adjustment signal of the first level may be a high level signal or a low level signal, depending on the level of the signal required when the battery management chip of the terminal enters the low power consumption mode.

Further, the power control method provided by the embodiment of the present invention, as shown in FIG. 2 , before S102, further includes:

S101a. When the number of pulses of the periodic pulse signal detected within the preset duration is less than N, no longer generate a delayed restart signal, wherein the preset duration is equal to the length of N cycles of the periodic pulse signal.

Optionally, the power control method provided in the embodiment of the present invention, as shown in FIG. 3 , further includes:

S301. When the number of pulses of the periodic pulse signal from the controller of the terminal detected within the preset duration is greater than or equal to N, generate a delayed restart signal;

S302. Within a delay period after the delayed restart signal is generated, output an adjustment signal of a second level to the low power consumption mode register in the battery management chip of the terminal, and the adjustment signal of the second level can make the The battery management chip exits the low power consumption mode.

When the adjustment signal of the first level is a high level signal, the adjustment signal of the second level is a low level signal; when the adjustment signal of the first level is a low level signal, the adjustment signal of the second level is a high level signal level signal.

Another power control method provided by an embodiment of the present invention, as shown in FIG. 4 , includes:

S401. Determine that the control signal output by the controller of the terminal has not been received, and the control signal is used to make the battery management chip of the terminal enter a low power consumption mode or exit the low power consumption mode;

S402. Output an adjustment signal of a first level to a low power consumption mode register in the battery management chip of the terminal, where the adjustment signal of the first level can cause the battery management chip to enter a low power consumption mode.

Optionally, the power control method provided in the embodiment of the present invention, as shown in FIG. 5 , also includes before S402:

S401a. Determine that the control signal of the first preset voltage output by the controller of the terminal is received.

Wherein, the signal of the first preset voltage may be a high-level signal or a low-level signal.

Optionally, the power control method provided in this embodiment of the present invention, as shown in FIG. 6 , further includes:

S601. Determine to receive the control signal of the second preset voltage output by the controller of the terminal;

S602. Output an adjustment signal of a second level to a low power consumption mode register in the battery management chip of the terminal, where the adjustment signal of the second level can enable the battery management chip to exit the low power consumption mode.

When the control signal of the first preset voltage is a high-level signal, the control signal of the second preset voltage is a low-level signal; when the control signal of the first preset voltage is a low-level signal, the second preset The voltage control signal is a high level signal.

In order to further illustrate the power control method provided by the embodiment of the present invention, the following uses an example in which the power control method is applied in practice for description.

A practical flow chart of a power control method provided by an embodiment of the present invention is shown in Figure 7, including:

S701. Determine whether a control signal from the terminal controller is received, the control signal is used to enable the battery management chip of the terminal to enter the low power consumption mode or exit the low power consumption mode, if so, execute S702, otherwise, execute S703;

S702. Determine whether the received control signal from the controller is a control signal of the first preset voltage, if yes, execute S703, otherwise, that is, the control signal is a control signal of the second preset voltage, execute S704;

S703. Output an adjustment signal of a first level to a low power consumption mode register in the battery management chip of the terminal, where the adjustment signal of the first level can enable the battery management chip to enter a low power consumption mode;

S704. Output an adjustment signal of a second level to a low power consumption mode register in the battery management chip of the terminal, where the adjustment signal of the second level can cause the battery management chip to exit the low power consumption mode.

A flowchart of another power control method provided by an embodiment of the present invention applied in practice is shown in FIG. 8 , including:

S801. Determine whether the number of pulses of the periodic pulse signal detected from the terminal controller within the preset duration is greater than or equal to N, if so, execute S802, otherwise, execute S804; wherein, the preset duration is equal to the control signal The length of N cycles of ;

S802. Generate a delayed restart signal;

S803. Within a delay period after the delayed restart signal is generated, output an adjustment signal of a second level to the low power consumption mode register in the battery management chip of the terminal, and the adjustment signal of the second level can make the terminal A signal for the battery management chip to exit the low power consumption mode; the start time of the delay time is earlier than or equal to the end time of the preset time length, and the delay time length is greater than or equal to the preset time length;

S804, the delayed restart signal is no longer generated;

S805. If no delayed restart signal is generated within a delay time, after the delay time ends, output the first level adjustment signal to the low power consumption mode register in the battery management chip of the terminal, the first An adjustment signal of a level can enable the battery management chip to enter a low power consumption mode.

Based on the same inventive concept, the embodiment of the present invention also provides a power control circuit and an energy-saving system. Since the principles of the problems solved by these circuits and systems are similar to the aforementioned control methods, the implementation of these circuits and systems can refer to the implementation of the aforementioned methods. , the repetitions will not be repeated.

A power control circuit provided by an embodiment of the present invention, as shown in FIG. 9 , includes a detection generation circuit 91 and an output circuit 92; the detection generation circuit 91 is connected to the port and output port for outputting a periodic pulse signal in the controller 90 of the terminal A circuit 92, the output circuit 92 is connected to the low power consumption mode register in the battery management chip 93 of the terminal;

The detection generating circuit 91 is configured to no longer generate a delayed restart signal when the periodic pulse signal from the controller 90 of the terminal is not detected within the preset duration; the preset duration is longer than the period of the periodic pulse signal a pulse width;

The output circuit 92 is configured to determine that a delayed restart signal is not generated within a delay period, and after the delay period ends, output the adjustment of the first level to the low power consumption mode register in the battery management chip 93 of the terminal Signal, the adjustment signal of the first level can make the battery management chip 93 enter the low power consumption mode; the start time of the delay time is earlier than or equal to the end time of the preset time length, and the delay time is longer than or equal to the preset duration.

Wherein, the detection generation circuit 91 and the output circuit 92 can be located in the battery management chip, or can be located outside the battery management chip. In FIG. 9 , an example is described in which the detection generation circuit and the output circuit are located outside the chip with the low power consumption mode.

Optionally, the detection generation circuit 91 is further configured to, before the output circuit 92 determines that the delayed restart signal is not generated within a delay time length, if the number of pulses of the periodic pulse signal detected within a preset time length If the number is less than N, the delayed restart signal is no longer generated, wherein the preset duration is equal to the length of N cycles of the periodic pulse signal.

Optionally, the detection generation circuit 91 is also used to generate a delayed restart signal when the number of pulses of the periodic pulse signal detected within the preset duration is greater than or equal to N;

The output circuit 92 is further configured to output an adjustment signal of a second level to the low power consumption mode register in the battery management chip within a delay period after the delayed restart signal is generated, and the second level The adjustment signal can cause the battery management chip to exit the low power consumption mode.

Another power control circuit provided by an embodiment of the present invention, as shown in FIG. 10 , includes a receiving circuit 101 and a transmission circuit 102. The receiving circuit 101 is connected to a port for outputting control signals in the controller 90 of the terminal and the transmission circuit 102. The transmission circuit 102 is connected to the low power consumption mode register in the battery management chip 93 of the terminal;

The receiving circuit 101 is configured to receive a control signal output by the controller 90 of the terminal, where the control signal is used to enable the battery management chip 93 of the terminal to enter a low power consumption mode or exit the low power consumption mode;

The transmission circuit 102 is configured to output an adjustment signal of a first level to the low power consumption mode register in the battery management chip 93 when the receiving circuit 101 determines that the control signal output by the controller 90 has not been received, and the first level The level adjustment signal can enable the battery management chip 93 to enter a low power consumption mode.

Optionally, the transmission circuit 102 is also configured to output the first level to the low power consumption mode register in the battery management chip 93 when the receiving circuit 101 determines to receive the control signal of the first preset voltage output by the controller 90 The adjustment signal of the first level can cause the battery management chip to enter a low power consumption mode.

Optionally, the transmission circuit 102 is also configured to output the second preset voltage to the low power consumption mode register in the battery management chip 93 when the receiving circuit 101 determines to receive the control signal of the second preset voltage output by the controller 90 of the terminal. The adjustment signal of the second level can make the battery management chip 93 exit the low power consumption mode.

Optionally, as shown in FIG. 11 , the receiving circuit 101 includes a first resistance unit 1011; one end of the first resistance unit 1011 is connected to a port for outputting a control signal in the controller 90, and the other end of the first resistance unit 1011 will receive The received control signal is output to the transmission unit 102. Wherein, the first resistance unit is a network of series/parallel resistances.

Optionally, as shown in FIG. 12a, the transmission circuit 102 includes a second resistance unit 1021 and a third resistance unit 1022, one end of the second resistance unit 1021 receives the set voltage signal V, and the other end of the second resistance unit 1021 is connected to the third resistance unit 1022. One end of the three resistor unit 1022 is connected to receive the signal of the receiving unit 102; if the setting voltage signal V and the adjustment signal of the first level are both high-level signals, or both are low-level signals, the third resistor The other end of the unit 1022 is connected to the low power consumption mode register in the battery management chip 93 of the terminal.

Wherein, the set voltage signal V can be a ground signal, or a voltage signal with a preset voltage value, and a high-level signal can be generated according to the set voltage signal. The second resistance unit is a network of resistors connected in series/parallel, and the third resistance unit is a network of resistors connected in series/parallel.

When the voltage signal V is set as a ground signal, when the low power consumption mode register of the battery management chip 93 is set to 0, that is, the low power consumption mode can only be entered when a low level signal is stored in the low power consumption mode register, that is, the battery can be The signal that the management chip 93 enters the low power consumption mode is a low-level signal, then when the first resistance unit 1011 does not receive the control signal, the first resistance unit 1011 cannot output the control signal to the output circuit 102, and because the second resistance unit One end of 1021 receives the set voltage signal V, that is, is grounded. Therefore, the third resistor unit 1022 can output a low level signal, and the second resistor unit 1021 is a pull-down resistor. When the preset signal V is a voltage signal with a preset voltage value, the battery management chip 93 can enter the low power consumption mode when the low power consumption mode register is set to 1, that is, the low power consumption mode register stores a high level signal , that is, the signal that enables the battery management chip 93 to enter the low power consumption mode is a high-level signal, then when the first resistance unit 1011 does not receive the control signal, the first resistance unit 1011 cannot output the control signal to the output circuit 102, and Since one end of the second resistor unit 1021 receives the set voltage signal V, that is, a voltage signal with a preset voltage value, the third resistor unit 1022 can output a high level signal, and the second resistor unit 1021 is a pull-up resistor.

Optionally, as shown in Figure 12b, if the set voltage signal is a high-level signal, the adjustment signal of the first level is a low-level signal, or, if the set voltage signal is a low-level signal, the first level The adjusted signal is a high level signal; then the output circuit further includes an inversion circuit 1023, and the other end of the third resistance unit 1022 is connected to the low power consumption mode register in the battery management chip 93 of the terminal through the inversion circuit 1023.

When the voltage signal V is set as a ground signal, the battery management chip 93 can enter the low-power mode when the low-power mode register is set to 1, that is, when a high-level signal is stored in the low-power mode register, that is, the battery can be activated. The signal that the management chip 93 enters the low power consumption mode is a high-level signal, then when the first resistance unit 1011 does not receive the control signal, the first resistance unit 1011 cannot output the control signal to the output circuit 102, and because the second resistance unit One end of 1021 receives the set voltage signal V, that is, is grounded. Therefore, the third resistor unit 1022 can output a low level signal, and the second resistor unit 1021 is a pull-down resistor. Therefore, the output circuit 102 includes an inversion circuit 1023, which can convert the input low-level signal into a high-level signal. When the preset signal V is a voltage signal with a preset voltage value, the low power consumption mode register of the battery management chip 93 is set to 0, that is, the low power consumption mode can only be entered when a low level signal is stored in the low power consumption mode register. , that is, the signal that enables the battery management chip 93 to enter the low power consumption mode is a low-level signal, then when the first resistance unit 1011 does not receive the control signal, the first resistance unit 1011 cannot output the control signal to the output circuit 102, and Since one end of the second resistor unit 1021 receives the set voltage signal V, that is, a voltage signal with a preset voltage value, the third resistor unit 1022 can output a high level signal, and the second resistor unit 1021 is a pull-up resistor. Therefore, the output circuit 102 includes an inversion circuit 1023, which can convert the input high-level signal into a low-level signal.

An embodiment of the present invention also provides an energy-saving system, including a terminal controller, a battery management chip of the terminal, and any power control circuit provided in the embodiments of the present invention.

Through the above description of the implementation manners, those skilled in the art can clearly understand that the embodiments of the present invention can be implemented by hardware, or by means of software plus a necessary general hardware platform. Based on this understanding, the technical solutions of the embodiments of the present invention can be embodied in the form of software products, which can be stored in a non-volatile storage medium (which can be CD-ROM, U disk, mobile hard disk, etc.), Several instructions are included to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute the methods described in various embodiments of the present invention.

Those skilled in the art can understand that the drawing is only a schematic diagram of a preferred embodiment, and the modules or processes in the drawing are not necessarily necessary for implementing the present invention.

Those skilled in the art can understand that the modules in the device in the embodiment can be distributed in the device in the embodiment according to the description in the embodiment, or can be located in one or more devices different from the embodiment according to corresponding changes. The modules in the above embodiments can be combined into one module, and can also be further split into multiple sub-modules.

The serial numbers of the above embodiments of the present invention are for description only, and do not represent the advantages and disadvantages of the embodiments.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (16)

1. a Poewr control method, is characterized in that, comprising:

When not detecting the cyclic pulse signal of the controller of self terminal in preset duration, the not regeneration time delay signal of restarting;

Determine not generate in a delay duration signal that time delay is restarted, after this delay duration terminates, export the adjustment signal of the first level to the low-power consumption mode register in the battery management chip of described terminal, the adjustment signal of described first level can make described battery management chip enter low-power consumption mode;

Wherein, start time of described delay duration early than or equal finish time of described preset duration, described delay duration is more than or equal to described preset duration, and described preset duration is greater than a pulse width of described cyclic pulse signal.

2. control method as claimed in claim 1, is characterized in that, before determining not generate in a delay duration signal that time delay restarts, described method also comprises:

When the number of the pulse of the described cyclic pulse signal detected in preset duration is less than N, the not regeneration time delay signal of restarting, wherein, preset duration equals the length in N number of cycle of described cyclic pulse signal.

3. control method as claimed in claim 2, it is characterized in that, described method also comprises:

When the number of the pulse of the described cyclic pulse signal detected in preset duration is more than or equal to N, generate the signal that time delay is restarted;

In a delay duration after the signal that generation time delay is restarted, export the adjustment signal of second electrical level to the low-power consumption mode register in described battery management chip, the adjustment signal of described second electrical level can make described battery management chip exit the signal of low-power consumption mode.

4. a Poewr control method, is characterized in that, comprising:

The control signal that the controller determining not receive terminal exports, the battery management chip that described control signal is provided for described terminal enters low-power consumption mode or exits low-power consumption mode;

Export the adjustment signal of the first level to the low-power consumption mode register in the battery management chip of described terminal, the adjustment signal of described first level can make described battery management chip enter low-power consumption mode.

5. control method as claimed in claim 4, it is characterized in that, export the adjustment signal of the first level to the low-power consumption mode register in described battery management chip before, described method also comprises:

The control signal of the first predeterminated voltage that the controller determining to receive described terminal exports.

6. control method as claimed in claim 4, it is characterized in that, described method also comprises:

The control signal of the second predeterminated voltage that the controller determining to receive described terminal exports;

Export the adjustment signal of second electrical level to the low-power consumption mode register in described battery management chip, the adjustment signal of described second electrical level can make described battery management chip exit low-power consumption mode.

7. a power control circuit, it is characterized in that, comprise and detect generative circuit and output circuit, described detection generative circuit connects for exporting the port of cyclic pulse signal and described output circuit in the controller of terminal, and described output circuit connects the low-power consumption mode register in the battery management chip of described terminal;

Described detection generative circuit, during for not detecting the cyclic pulse signal of the controller of self terminal in preset duration, the not regeneration time delay signal of restarting; Described preset duration is greater than a pulse width of described cyclic pulse signal;

Described output circuit, for determining not generate in a delay duration signal that time delay is restarted, after this delay duration terminates, export the adjustment signal of the first level to the low-power consumption mode register in the battery management chip of described terminal, the adjustment signal of described first level can make described battery management chip enter low-power consumption mode; Start time of described delay duration early than or equal finish time of described preset duration, described delay duration is more than or equal to described preset duration.

8. circuit as claimed in claim 7, is characterized in that, described detection generative circuit also for:

Before determining not generate in a delay duration signal that time delay restarts, if the number of the pulse of the described cyclic pulse signal detected in preset duration is less than N, the not regeneration time delay signal of restarting, wherein, preset duration equals the length in N number of cycle of described cyclic pulse signal.

9. circuit as claimed in claim 8, is characterized in that, described detection generative circuit also for:

When the number of the pulse of the cyclic pulse signal detected in preset duration is more than or equal to N, generate the signal that time delay is restarted;

Described output circuit, also in a delay duration after generating the time delay signal of restarting, export the adjustment signal of second electrical level to the low-power consumption mode register in described battery management chip, the adjustment signal of described second electrical level can make described battery management chip exit the signal of low-power consumption mode.

10. a power control circuit, it is characterized in that, comprise receiving circuit and transmission circuit, described receiving circuit connects for exporting the port of control signal and described transmission circuit in the controller of terminal, and described transmission circuit connects the low-power consumption mode register in the battery management chip of described terminal;

Described receiving circuit, the control signal that the controller for receiving described terminal exports, the battery management chip that described control signal is provided for described terminal enters low-power consumption mode or exits low-power consumption mode;

Described transmission circuit, during for determining the control signal not receiving the output of described controller at described receiving circuit, export the adjustment signal of the first level to the low-power consumption mode register in described battery management chip, the adjustment signal of described first level can make described battery management chip enter low-power consumption mode.

11. circuit as claimed in claim 10, is characterized in that, described transmission circuit also for:

When the control signal receiving the first predeterminated voltage that described controller exports determined by described receiving circuit, export the adjustment signal of the first level to the low-power consumption mode register in described battery management chip, the adjustment signal of described first level can make described battery management chip enter low-power consumption mode.

12. circuit as claimed in claim 10, is characterized in that, described transmission circuit also for:

When the control signal of the second predeterminated voltage that the controller that described receiving circuit determines to receive described terminal exports, export the adjustment signal of second electrical level to the low-power consumption mode register in described battery management chip, the adjustment signal of described second electrical level can make described battery management chip exit low-power consumption mode.

13. circuit as claimed in claim 10, it is characterized in that, described receiving circuit comprises the first resistance unit;

One end of described first resistance unit connects for exporting the port of control signal in described controller, and the control signal received exports to described transmission unit by the other end of described first resistance unit.

14. circuit as claimed in claim 10, it is characterized in that, described transmission circuit comprises the second resistance unit and the 3rd resistance unit, one end of described second resistance unit receives setting voltage signal, the other end of described second resistance unit is connected with one end of the 3rd resistance unit, and receives the signal of described receiving element; If the adjustment signal of described setting voltage signal and the first level is high level signal, or be low level signal, then the other end of described 3rd resistance unit connects the low-power consumption mode register in the battery management chip of described terminal.

15. circuit as claimed in claim 14, is characterized in that, if described setting voltage signal is high level signal, the adjustment signal of the first level is low level signal, or described setting voltage signal is low level signal, the signal of the adjustment of the first level is high level signal; Then described output circuit also comprises negate circuit, and the other end of described 3rd resistance unit connects the low-power consumption mode register in the battery management chip of described terminal by described negate circuit.

16. 1 kinds of energy conserving systems, is characterized in that, comprise the controller of terminal, the battery management chip of this terminal and the power control circuit as described in any one of claim 7 ~ 15.