CN103439844B - The method of array substrate, display unit and making array substrate - Google Patents
The method of array substrate, display unit and making array substrate Download PDFInfo
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- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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Abstract
本发明涉及阵列基板、显示装置及制作阵列基板的方法，其中一种阵列基板，包括：位于不同层的第一金属连接部和第二金属连接部，还包括用于连接第一金属连接部和第二金属连接部的透明导电膜层；第一金属部与第二金属连接部通过第一绝缘层隔开；第一金属连接部与第二金属连接部在垂直于阵列基板平面的方向上至少部分重叠。本发明的有益效果是：第一金属连接部与第二金属连接部在垂直于基板平面的方向上至少部分重叠，用于连通第一金属连接部、第二金属连接部的透明导电膜层在与衬底基板平行方向上的距离大大缩短，减小了透明导电膜层与第一金属连接部、第二金属连接部接触的接触电阻的大小，减少了透明导电膜层坡面的产生。
The present invention relates to an array substrate, a display device and a method for manufacturing the array substrate, wherein an array substrate includes: a first metal connection part and a second metal connection part located in different layers, and a The transparent conductive film layer of the second metal connection part; the first metal part and the second metal connection part are separated by the first insulating layer; the first metal connection part and the second metal connection part are at least partially overlap. The beneficial effects of the present invention are: the first metal connection part and the second metal connection part at least partly overlap in the direction perpendicular to the plane of the substrate, and the transparent conductive film layer used to communicate the first metal connection part and the second metal connection part The distance in the direction parallel to the base substrate is greatly shortened, the contact resistance between the transparent conductive film layer and the first metal connection part and the second metal connection part is reduced, and the generation of slopes of the transparent conductive film layer is reduced.
Description
技术领域technical field
本发明涉及液晶显示技术领域，尤其涉及一种阵列基板、显示装置及制作阵列基板的方法。The invention relates to the technical field of liquid crystal display, in particular to an array substrate, a display device and a method for manufacturing the array substrate.
背景技术Background technique
阵列基板包括衬底基板1，以及依次形成在衬底基板1上的栅金属连接部2、第一绝缘层3、源/漏金属连接部4、第二绝缘层5，需要连接Gate（栅金属连接部）和SD（源/漏金属连接部）金属时，会在Gate和SD金属上分别设置第一过孔7和第二过孔8去除栅金属连接部上方的第一绝缘层3和第二绝缘层5，以及去除源/漏金属连接部4上方的第二绝缘层5，然后用ITO（透明导电膜层）6连接，如图1所示，由于过孔存在坡度角以及绝缘层存在段差，且栅金属连接部2和源/漏金属连接部4之间的距离比较长，栅金属连接部2和源/漏金属连接部4之间的ITO6出现多个坡面结构，而使得栅金属连接部2和源/漏金属连接部4之间的电阻增加，且ITO6容易出现断裂现象。The array substrate includes a base substrate 1, and a gate metal connection part 2, a first insulating layer 3, a source/drain metal connection part 4, and a second insulating layer 5 are sequentially formed on the base substrate 1, and it is necessary to connect the Gate (gate metal Connection part) and SD (source/drain metal connection part) metal, the first via hole 7 and the second via hole 8 will be provided on the Gate and SD metal respectively to remove the first insulating layer 3 and the second via hole above the gate metal connection part The second insulating layer 5, and remove the second insulating layer 5 above the source/drain metal connection part 4, and then use ITO (transparent conductive film layer) 6 to connect, as shown in Figure 1, due to the slope angle of the via hole and the existence of the insulating layer step difference, and the distance between the gate metal connection part 2 and the source/drain metal connection part 4 is relatively long, and the ITO6 between the gate metal connection part 2 and the source/drain metal connection part 4 has multiple slope structures, so that the gate The resistance between the metal connection part 2 and the source/drain metal connection part 4 increases, and the ITO6 is prone to breakage.
发明内容Contents of the invention
为了解决上述技术问题，本发明提供一种阵列基板、显示装置及制作阵列基板的方法，减少栅金属连接部、源/漏金属连接部之间的透明导电膜层的坡面结构，减小电阻。In order to solve the above-mentioned technical problems, the present invention provides an array substrate, a display device, and a method for manufacturing an array substrate, which reduce the slope structure of the transparent conductive film layer between the gate metal connection part and the source/drain metal connection part, and reduce the resistance. .
为了达到上述目的，本发明采用的技术方案是：一种阵列基板，包括：位于不同层的第一金属连接部和第二金属连接部，还包括用于连接所述第一金属连接部和第二金属连接部的透明导电膜层；In order to achieve the above object, the technical solution adopted by the present invention is: an array substrate, including: a first metal connection part and a second metal connection part located in different layers, and a The transparent conductive film layer of the two metal connection parts;
所述第一金属部与所述第二金属连接部通过第一绝缘层隔开；所述第一金属连接部与所述第二金属连接部在垂直于阵列基板平面的方向上至少部分重叠。The first metal part and the second metal connection part are separated by a first insulating layer; the first metal connection part and the second metal connection part at least partially overlap in a direction perpendicular to the plane of the array substrate.
进一步的，还包括：Further, it also includes:
与所述第二金属连接部同层或在所述第二金属连接部上形成的第二绝缘层；a second insulating layer formed on the same layer as the second metal connection part or on the second metal connection part;
贯穿所述第二绝缘层和第一绝缘层的第一开口，所述第一开口露出所述第一金属连接部的至少一部分以及所述第二金属连接部的至少一部分；所述透明导电膜层覆盖所述第一开口以连接所述第一金属连接部和所述第二金属连接部。A first opening through the second insulating layer and the first insulating layer, the first opening exposing at least a part of the first metal connection part and at least a part of the second metal connection part; the transparent conductive film A layer covers the first opening to connect the first metal connection part and the second metal connection part.
进一步的，所述第一金属连接部的至少部分边缘与所述第二金属连接部的至少部分边缘在垂直于阵列基板平面的方向上平齐，所述第一开口露出该平齐的所述第一金属连接部的边缘及所述第二金属连接部的边缘。Further, at least part of the edge of the first metal connection part is flush with at least part of the edge of the second metal connection part in a direction perpendicular to the plane of the array substrate, and the first opening exposes the flush The edge of the first metal connection part and the edge of the second metal connection part.
进一步的，所述第二金属连接部位于所述第一金属连接部的正上方。Further, the second metal connection part is located right above the first metal connection part.
进一步的，所述第一开口还贯穿所述第二金属连接部，并露出所述第一金属连接部上表面的一部分。Further, the first opening also penetrates through the second metal connection part and exposes a part of the upper surface of the first metal connection part.
进一步的，所述阵列基板为薄膜晶体管阵列基板，所述第一金属连接部和第二金属连接部位于所述阵列基板的周边区域；所述第一金属连接部为栅金属连接部，所述第二金属连接部为源/漏金属连接部。Further, the array substrate is a thin film transistor array substrate, the first metal connection part and the second metal connection part are located in the peripheral area of the array substrate; the first metal connection part is a gate metal connection part, and the The second metal connection part is a source/drain metal connection part.
进一步的，所述阵列基板上的所述栅金属连接部、第一绝缘层、所述源/漏金属连接部、第二绝缘层依次设置在所述阵列基板的衬底基板上；或，Further, the gate metal connection part, the first insulating layer, the source/drain metal connection part, and the second insulating layer on the array substrate are sequentially arranged on the base substrate of the array substrate; or,
所述阵列基板的所述源/漏金属连接部、第一绝缘层、所述栅金属连接部、第二绝缘层依次设置在所述阵列基板的衬底基板上。The source/drain metal connection part, the first insulating layer, the gate metal connection part, and the second insulating layer of the array substrate are sequentially disposed on the base substrate of the array substrate.
进一步的，further,
所述栅金属连接部为所述阵列基板的栅线的一端连接部，所述源/漏金属连接部为栅线引出线的一端连接部，所述透明导电膜层用于通过所述第一开口将所述栅线和所述栅线引出线电连接；或者，The gate metal connection part is the connection part of one end of the gate line of the array substrate, the source/drain metal connection part is the connection part of one end of the lead wire of the gate line, and the transparent conductive film layer is used to pass through the first The opening electrically connects the grid line and the grid line lead-out line; or,
所述源/漏金属连接部为所述阵列基板的数据线的一端连接部，所述栅金属连接部为所述阵列基板的数据线引出线的一端连接部，所述透明导电膜层用于通过所述第一开口将所述数据线和所述数据线引出线电连接；或者，The source/drain metal connection part is one end connection part of the data line of the array substrate, the gate metal connection part is one end connection part of the data line lead-out line of the array substrate, and the transparent conductive film layer is used for electrically connecting the data line and the data line lead-out line through the first opening; or,
所述栅金属连接部和所述源/漏金属连接部两者中之一为所述阵列基板的信号线的一端连接部，另一为该信号线的修复线，所述透明导电膜层用于通过所述第一开口将所述信号线和所述修复线电连接，其中所述信号线为栅线或数据线；或者，One of the gate metal connection part and the source/drain metal connection part is the one-end connection part of the signal line of the array substrate, and the other is the repair line of the signal line. for electrically connecting the signal line and the repair line through the first opening, wherein the signal line is a gate line or a data line; or,
所述栅金属连接部和所述源/漏金属连接部分别为所述阵列基板的公共电极引线的不同线段之间的连接部，所述透明导电膜层用于通过所述第一开口将该不同线段电连接。The gate metal connection part and the source/drain metal connection part are connection parts between different line segments of the common electrode lead of the array substrate, and the transparent conductive film layer is used to pass through the first opening. The different line segments are electrically connected.
本发明还提供一种显示装置，包括上述的阵列基板。The present invention also provides a display device, including the above-mentioned array substrate.
本发明还提供一种阵列基板的制造方法，包括：The present invention also provides a method for manufacturing an array substrate, including:
通过构图工艺在阵列基板上形成位于不同层的第一金属连接部和第二金属连接部；forming a first metal connection part and a second metal connection part located in different layers on the array substrate through a patterning process;
通过构图工艺在阵列基板上形成用于连接所述第一金属连接部和第二金属连接部的透明导电膜层；forming a transparent conductive film layer for connecting the first metal connection part and the second metal connection part on the array substrate through a patterning process;
所述方法还包括;在所述第一金属部与所述第二金属连接部之间形成第一绝缘层；The method further includes: forming a first insulating layer between the first metal part and the second metal connection part;
且，所述第一金属连接部与所述第二金属连接部在垂直于基板平面的方向上至少部分重叠。Moreover, the first metal connection part and the second metal connection part at least partially overlap in a direction perpendicular to the plane of the substrate.
进一步的，还包括Further, it also includes
在阵列基板顶层的所述第一金属连接部或所述第二金属连接部上形成第二绝缘层；forming a second insulating layer on the first metal connection part or the second metal connection part on the top layer of the array substrate;
通过构图工艺，贯穿所述第二绝缘层和第一绝缘层形成第一开口，所述第一开口露出所述第一金属连接部的至少一部分以及所述第二金属连接部的至少一部分；Through a patterning process, a first opening is formed through the second insulating layer and the first insulating layer, and the first opening exposes at least a part of the first metal connection part and at least a part of the second metal connection part;
通过构图工艺，在所述第一开口上形成所述透明导电膜层以连接所述第一金属连接部和所述第二金属连接部。Through a patterning process, the transparent conductive film layer is formed on the first opening to connect the first metal connection part and the second metal connection part.
本发明的有益效果是：所述第一金属连接部与所述第二金属连接部在垂直于基板平面的方向上至少部分重叠，用于连通所述第一金属连接部、所述第二金属连接部的透明导电膜层在与所述衬底基板平行方向上的距离大大缩短，减小了透明导电膜层与所述第一金属连接部、第二金属连接部接触的接触电阻的大小，减少了透明导电膜层坡面的产生。The beneficial effect of the present invention is that: the first metal connection part and the second metal connection part at least partly overlap in the direction perpendicular to the plane of the substrate, and are used to connect the first metal connection part and the second metal connection part. The distance between the transparent conductive film layer of the connection part in the direction parallel to the base substrate is greatly shortened, reducing the contact resistance between the transparent conductive film layer and the first metal connection part and the second metal connection part, The generation of the slope of the transparent conductive film layer is reduced.
附图说明Description of drawings
图1表示现有技术中阵列基板截面示意图；FIG. 1 shows a schematic cross-sectional view of an array substrate in the prior art;
图2表示本发明一实施例中阵列基板截面示意图；2 shows a schematic cross-sectional view of an array substrate in an embodiment of the present invention;
图3表示本发明一实施例中阵列基板截面示意图；3 shows a schematic cross-sectional view of an array substrate in an embodiment of the present invention;
图4表示本发明一实施例中阵列基板截面示意图。FIG. 4 is a schematic cross-sectional view of an array substrate in an embodiment of the present invention.
具体实施方式detailed description
以下结合附图对本发明的结构和原理进行详细说明，所举实施例仅用于解释本发明，并非以此限定本发明的保护范围。The structure and principle of the present invention will be described in detail below in conjunction with the accompanying drawings, and the examples given are only used to explain the present invention, not to limit the protection scope of the present invention.
如图2所示，本实施例提供一种阵列基板，包括：位于不同层的第一金属连接部2和第二金属连接部4，还包括用于连接所述第一金属连接部2和第二金属连接部4的透明导电膜层6；As shown in FIG. 2 , this embodiment provides an array substrate, including: a first metal connection part 2 and a second metal connection part 4 located in different layers, and a The transparent conductive film layer 6 of the two metal connection parts 4;
所述第一金属部2与所述第二金属连接部4通过第一绝缘层3隔开；所述第一金属连接部2与所述第二金属连接部4在垂直于阵列基板平面的方向上至少部分重叠。The first metal part 2 and the second metal connection part 4 are separated by the first insulating layer 3; the first metal connection part 2 and the second metal connection part 4 are arranged in a direction perpendicular to the plane of the array substrate overlap at least partially.
本实施例中，所述第一金属连接部与所述第二金属连接部在垂直于基板平面的方向上至少部分重叠，用于连通所述第一金属连接部、所述第二金属连接部的透明导电膜层在与所述衬底基板平行方向上的距离大大缩短，减小了透明导电膜层与所述第一金属连接部、第二金属连接部接触的接触电阻的大小，减少了透明导电膜层坡面的产生。提升了画面质量，同时减少了透明导电膜层坡面的产生，则大大减少了透明导电膜层断裂的可能性。In this embodiment, the first metal connection part and the second metal connection part at least partially overlap in a direction perpendicular to the plane of the substrate, and are used to connect the first metal connection part and the second metal connection part. The distance of the transparent conductive film layer in the direction parallel to the base substrate is greatly shortened, which reduces the contact resistance between the transparent conductive film layer and the first metal connection part and the second metal connection part, and reduces the Generation of transparent conductive film layer slope. The picture quality is improved, and at the same time, the slope of the transparent conductive film layer is reduced, and the possibility of breaking the transparent conductive film layer is greatly reduced.
与所述第二金属连接部同层或在所述第二金属连接部上形成的第二绝缘层；a second insulating layer formed on the same layer as the second metal connection part or on the second metal connection part;
贯穿所述第二绝缘层5和第一绝缘层3的第一开口，所述第一开口露出所述第一金属连接部2的至少一部分以及所述第二金属连接部4的至少一部分；所述透明导电膜层6覆盖所述第一开口以连接所述第一金属连接部2和所述第二金属连接部4。Through the first opening of the second insulating layer 5 and the first insulating layer 3, the first opening exposes at least a part of the first metal connection part 2 and at least a part of the second metal connection part 4; The transparent conductive film layer 6 covers the first opening to connect the first metal connection part 2 and the second metal connection part 4 .
本实施例中仅采用第一开口一个开口的设置代替现有技术中的两个开口的结构形式，减少了透明导电膜层坡面的产生，则大大减少了透明导电膜层断裂的可能性。In this embodiment, only one opening of the first opening is used instead of the structure of two openings in the prior art, which reduces the slope of the transparent conductive film layer and greatly reduces the possibility of breaking the transparent conductive film layer.
本实施例中，为了实现所述第一金属连接部2与所述第二金属连接部4在与阵列基板平面平行的方向的间隙为零，以实现用于连通所述第一金属连接部2、所述第二金属连接部4的透明导电膜层6的坡面结构减少，所述第一金属连接部2、所述第二金属连接部4的设置优选为以下结构形式：In this embodiment, in order to realize that the gap between the first metal connection part 2 and the second metal connection part 4 in the direction parallel to the plane of the array substrate is zero, so as to realize the communication between the first metal connection part 2 , The slope structure of the transparent conductive film layer 6 of the second metal connection part 4 is reduced, and the setting of the first metal connection part 2 and the second metal connection part 4 is preferably the following structural form:
如图3所示，一实施例中，所述第一金属连接部2的至少部分边缘与所述第二金属连接部4的至少部分边缘在垂直于阵列基板平面的方向上平齐，所述第一开口露出该平齐的所述第一金属连接部2的边缘及所述第二金属连接部4的边缘。As shown in FIG. 3 , in one embodiment, at least part of the edges of the first metal connection part 2 are flush with at least part of the edges of the second metal connection part 4 in a direction perpendicular to the plane of the array substrate. The first opening exposes the flush edges of the first metal connection part 2 and the second metal connection part 4 .
应当指出的是，所述第一金属连接部2的至少部分边缘与所述第二金属连接部4的至少部分边缘在垂直于阵列基板平面的方向上平齐，即所述第一金属连接部2的至少部分边缘与所述第二金属连接部4的至少部分边缘在垂直于阵列基板平面的方向上是重叠的，是上述所描述的实施例中所述第一金属连接部2与所述第二金属连接部4在垂直于阵列基板平面的方向上至少部分重叠中的一种实施方式。It should be noted that at least part of the edge of the first metal connection part 2 is flush with at least part of the edge of the second metal connection part 4 in a direction perpendicular to the plane of the array substrate, that is, the first metal connection part At least part of the edge of 2 and at least part of the edge of the second metal connection part 4 overlap in the direction perpendicular to the plane of the array substrate, which is the combination of the first metal connection part 2 and the An implementation manner in which the second metal connecting portion 4 at least partially overlaps in a direction perpendicular to the plane of the array substrate.
如图4所示，一实施例中，所述第二金属连接部4位于所述第一金属连接部2的正上方。As shown in FIG. 4 , in an embodiment, the second metal connection part 4 is located directly above the first metal connection part 2 .
所述第一开口还贯穿所述第二金属连接部4，并露出所述第一金属连接部2上表面的一部分。The first opening also passes through the second metal connection part 4 and exposes a part of the upper surface of the first metal connection part 2 .
本实施例中，所述阵列基板为薄膜晶体管阵列基板，所述第一金属连接部2和第二金属连接部4位于所述阵列基板的周边区域（阵列基板可以是显示基板，也可以是其他用途的基板，例如太阳能电池板等，这里的周边区域，是指在阵列基板周边用于信号线引出、包括布线走线、衬垫等的区域，例如显示基板外围的非显示区域）；所述第一金属连接部2为栅金属连接部，所述第二金属连接部4为源/漏金属连接部。In this embodiment, the array substrate is a thin film transistor array substrate, and the first metal connection part 2 and the second metal connection part 4 are located in the peripheral area of the array substrate (the array substrate may be a display substrate or other Substrates for substrates, such as solar panels, etc., the peripheral area here refers to the area around the array substrate that is used to lead out signal lines, including wiring, pads, etc., such as the non-display area around the display substrate); The first metal connection part 2 is a gate metal connection part, and the second metal connection part 4 is a source/drain metal connection part.
所述栅金属连接部、所述源/漏金属连接部至少部分重叠，仅仅设置在所述栅金属连接部、所述源/漏金属连接部上的的透明导电膜层6即可直接将所述栅金属连接部、所述原/漏金属连接部连通，减少了接触电阻，透明导电膜层6上与所述栅金属连接部、所述源/漏金属连接部接触的部分相对于阵列基板上透明导电膜层整体所占的比例增大，同时减少了透明导电膜层6断裂的可能性。The gate metal connection part and the source/drain metal connection part are at least partially overlapped, and only the transparent conductive film layer 6 provided on the gate metal connection part and the source/drain metal connection part can directly connect the The gate metal connection part and the source/drain metal connection part are connected, which reduces the contact resistance, and the part of the transparent conductive film layer 6 that is in contact with the gate metal connection part and the source/drain metal connection part is relatively The overall proportion of the upper transparent conductive film layer is increased, and at the same time, the possibility of breaking the transparent conductive film layer 6 is reduced.
所述阵列基板上的所述栅金属连接部、第一绝缘层3、所述源/漏金属连接部、第二绝缘层5依次设置在所述阵列基板的衬底基板1上；或，The gate metal connection part, the first insulating layer 3, the source/drain metal connection part, and the second insulating layer 5 on the array substrate are sequentially arranged on the base substrate 1 of the array substrate; or,
所述阵列基板的所述源/漏金属连接部、第一绝缘层3、所述栅金属连接部、第二绝缘层5依次设置在所述阵列基板的衬底基板1上。The source/drain metal connection part of the array substrate, the first insulating layer 3 , the gate metal connection part and the second insulating layer 5 are sequentially disposed on the base substrate 1 of the array substrate.
本实施例中，所述栅金属连接部为所述阵列基板的栅线的一端连接部，所述源/漏金属连接部为栅线引出线的一端连接部，所述透明导电膜层用于通过所述第一开口将所述栅线和所述栅线引出线电连接；或者，In this embodiment, the gate metal connection part is the connection part of one end of the gate line of the array substrate, the source/drain metal connection part is the connection part of one end of the lead wire of the gate line, and the transparent conductive film layer is used for electrically connecting the grid line and the grid line lead-out line through the first opening; or,
所述源/漏金属连接部为所述阵列基板的数据线的一端连接部，所述栅金属连接部为所述阵列基板的数据线引出线的一端连接部，所述透明导电膜层用于通过所述第一开口将所述数据线和所述数据线引出线电连接；或者，The source/drain metal connection part is one end connection part of the data line of the array substrate, the gate metal connection part is one end connection part of the data line lead-out line of the array substrate, and the transparent conductive film layer is used for electrically connecting the data line and the data line lead-out line through the first opening; or,
所述栅金属连接部和所述源/漏金属连接部两者中之一为所述阵列基板的信号线的一端连接部，另一为该信号线的修复线，所述透明导电膜层用于通过所述第一开口将所述信号线和所述修复线电连接，其中所述信号线为栅线或数据线；或者，One of the gate metal connection part and the source/drain metal connection part is the one-end connection part of the signal line of the array substrate, and the other is the repair line of the signal line. for electrically connecting the signal line and the repair line through the first opening, wherein the signal line is a gate line or a data line; or,
所述栅金属连接部和所述源/漏金属连接部分别为所述阵列基板的公共电极引线的不同线段之间的连接部，所述透明导电膜层用于通过所述第一开口将该不同线段电连接。The gate metal connection part and the source/drain metal connection part are connection parts between different line segments of the common electrode lead of the array substrate, and the transparent conductive film layer is used to pass through the first opening. The different line segments are electrically connected.
本发明实施例中还提供一种显示装置，包括上述的阵列基板。An embodiment of the present invention also provides a display device, including the above-mentioned array substrate.
本发明实施例中还提供一种阵列基板的制造方法，该阵列基板可以是上述的任意一种类型的阵列基板，所述方法包括：An embodiment of the present invention also provides a method for manufacturing an array substrate. The array substrate may be any of the above-mentioned types of array substrates. The method includes:
通过构图工艺在阵列基板上形成位于不同层的第一金属连接部和第二金属连接部；forming a first metal connection part and a second metal connection part located in different layers on the array substrate through a patterning process;
通过构图工艺在阵列基板上形成用于连接所述第一金属连接部和第二金属连接部的透明导电膜层；forming a transparent conductive film layer for connecting the first metal connection part and the second metal connection part on the array substrate through a patterning process;
所述方法还包括;在所述第一金属部与所述第二金属连接部之间形成第一绝缘层；The method further includes: forming a first insulating layer between the first metal part and the second metal connection part;
且，所述第一金属连接部与所述第二金属连接部在垂直于基板平面的方向上至少部分重叠。Moreover, the first metal connection part and the second metal connection part at least partially overlap in a direction perpendicular to the plane of the substrate.
还包括：在阵列基板顶层的所述第一金属连接部或所述第二金属连接部上形成第二绝缘层；It also includes: forming a second insulating layer on the first metal connection part or the second metal connection part on the top layer of the array substrate;
通过构图工艺，贯穿所述第二绝缘层和第一绝缘层形成第一开口，所述第一开口露出所述第一金属连接部的至少一部分以及所述第二金属连接部的至少一部分；Through a patterning process, a first opening is formed through the second insulating layer and the first insulating layer, and the first opening exposes at least a part of the first metal connection part and at least a part of the second metal connection part;
通过构图工艺，在所述第一开口上形成所述透明导电膜层以连接所述第一金属连接部和所述第二金属连接部。以上所述为本发明较佳实施例，应当指出，对于本领域普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明保护范围。Through a patterning process, the transparent conductive film layer is formed on the first opening to connect the first metal connection part and the second metal connection part. The above description is a preferred embodiment of the present invention. It should be pointed out that those skilled in the art can make some improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be considered as For the protection scope of the present invention.
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| CN104362153B (en) * | 2014-09-17 | 2017-07-04 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device |
| CN105140179B (en) * | 2015-08-13 | 2018-12-14 | 京东方科技集团股份有限公司 | Array substrate and its manufacturing method, display panel and display device |
| CN106094371A (en) * | 2016-08-24 | 2016-11-09 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display floater and display device |
| CN110262139B (en) * | 2019-06-11 | 2021-07-06 | 惠科股份有限公司 | Contact hole structure, array substrate and display panel |
| CN116779616A (en) * | 2022-03-07 | 2023-09-19 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method thereof, display device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6326641B1 (en) * | 1998-11-27 | 2001-12-04 | Lg. Philips Lcd Co., Ltd. | Liquid crystal display device having a high aperture ratio |
| CN101369078A (en) * | 2007-08-17 | 2009-02-18 | 北京京东方光电科技有限公司 | TFT-LCD array substrate structure and manufacturing method thereof |
| CN101398585A (en) * | 2007-09-27 | 2009-04-01 | 北京京东方光电科技有限公司 | Array substrate of LCD |
| CN101847640A (en) * | 2009-03-27 | 2010-09-29 | 北京京东方光电科技有限公司 | Array substrate, manufacturing method thereof and liquid crystal display panel |
| CN102566165A (en) * | 2010-12-20 | 2012-07-11 | 北京京东方光电科技有限公司 | Array substrate, array substrate production method and liquid crystal display |
| WO2012132953A1 (en) * | 2011-03-25 | 2012-10-04 | シャープ株式会社 | Display device |
| CN103149757A (en) * | 2011-12-07 | 2013-06-12 | 乐金显示有限公司 | Liquid crystal display device and method for fabricating the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003338628A (en) * | 2002-05-20 | 2003-11-28 | Seiko Epson Corp | Thin-film semiconductor device, electro-optical device, electronic equipment, method of manufacturing thin-film semiconductor device, method of manufacturing electro-optical device |
| CN202975551U (en) * | 2012-12-26 | 2013-06-05 | 北京京东方光电科技有限公司 | Array substrate and display device |
| CN103439844B (en) * | 2013-08-30 | 2016-06-01 | 京东方科技集团股份有限公司 | The method of array substrate, display unit and making array substrate |
-
2013
- 2013-08-30 CN CN201310389372.3A patent/CN103439844B/en active Active
- 2013-12-13 WO PCT/CN2013/089379 patent/WO2015027619A1/en not_active Ceased
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6326641B1 (en) * | 1998-11-27 | 2001-12-04 | Lg. Philips Lcd Co., Ltd. | Liquid crystal display device having a high aperture ratio |
| CN101369078A (en) * | 2007-08-17 | 2009-02-18 | 北京京东方光电科技有限公司 | TFT-LCD array substrate structure and manufacturing method thereof |
| CN101398585A (en) * | 2007-09-27 | 2009-04-01 | 北京京东方光电科技有限公司 | Array substrate of LCD |
| CN101847640A (en) * | 2009-03-27 | 2010-09-29 | 北京京东方光电科技有限公司 | Array substrate, manufacturing method thereof and liquid crystal display panel |
| CN102566165A (en) * | 2010-12-20 | 2012-07-11 | 北京京东方光电科技有限公司 | Array substrate, array substrate production method and liquid crystal display |
| WO2012132953A1 (en) * | 2011-03-25 | 2012-10-04 | シャープ株式会社 | Display device |
| CN103149757A (en) * | 2011-12-07 | 2013-06-12 | 乐金显示有限公司 | Liquid crystal display device and method for fabricating the same |
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