CN103427927B - Clock synchronization realizing method and system for MPLS-TP network - Google Patents

Abstract

The invention provides a clock synchronization realizing method and system for an MPLS-TP network. The method comprises the steps of recording the time stamp of packaged PTP1588V2 messages of the MPLS-TP, and upgrading the value of the fixed reserved domain of the PTP1588V2 messages according to the time stamp; generating corresponding processing orders according to the packaging format of the PTP1588V2 messages; compiling the PTP1588V2 messages according to the processing orders; conducting synchronous treatment on the compiled PTP1588V2 messages. The device comprises a wire card and an ASIC integrated chip. The method and device simplify designs, reduce cost, and solve the problem of time stamp treatment.

Description

Method and device for implementing clock synchronization in MPLS-TP network

technical field

The present invention relates to the communication field, in particular to a method and device for implementing clock synchronization in an MPLS (Multi-Protocol Label Switching, multi-protocol label switching)-TP network.

Background technique

MPLS-TP network, namely MPLS Transport Profile, is a combination of T-MPLS and traditional MPLS network technology, and is used to solve the intercommunication problem between T-MPLS and traditional MPLS.

PTN (Packet Transport Network, Packet Transport Network) is mainly used for the backhaul of mobile or data services. It belongs to the category of transmission network and is more suitable for transmitting data services. However, PTN needs the clock synchronization of the entire network. The synchronization of PTN clocks is mainly reflected in two Aspects: ① When carrying TDM (time division multiplexing mode) services or intercommunicating with PSTN (Public Switched Telephone Network, public switched telephone network), it is necessary to provide synchronization functions at the TDM interface. ② When PTN carries 3G base station services, 3G service base stations like TD-CDMA, CDMA2000, and WiMAX need to provide high-precision time synchronization information. PTN is more suitable to use MPLS-TP network to transmit data information, so MPLS-TP network also needs to have the ability to transmit high-precision clock.

Existing clock synchronization technologies include: synchronous Ethernet technology, TOP (Timing Over Packet-swithing, packet delivery time) technology, NTP (Network Time Protocol, Network Time Protocol), GPS (Global Positioning System, Global Positioning System) timing, and PTP1588V2 technology. Among them, the use of PTP1588V2 to transmit clocks on the network has the advantages of low cost, high precision, and simultaneous transmission of time and frequency compared with other synchronization technologies, and is widely used in PTN network equipment.

Since the existing PTP1588 standard only provides PTP1588V2 to be carried on the second or third layer network, and there is no relevant standard definition for the MPLS-TP network, but if the PTN uses the MPLS-TP network to transmit data information and uses PTP1588V2 for clock synchronization, Then the MPLS-TP network must support PTP1588V2 to meet the high-precision clock requirements of PTN running on the MPLS-TP network.

Contents of the invention

The object of the present invention is to provide a method and device for implementing clock synchronization in an MPLS-TP network to solve the problem of clock synchronization in the MPLS-TP network.

The invention provides a method for implementing clock synchronization in an MPLS-TP network, comprising the following steps:

Record the timestamp of the PTP1588V2 message encapsulated by MPLS-TP received, and update the value of the fixed reserved field of the above-mentioned PTP1588V2 message according to the above timestamp;

Generate corresponding processing instructions according to the encapsulation format of the above-mentioned PTP1588V2 message;

According to the above processing instructions, edit the above PTP1588V2 message;

Perform timestamp synchronization on the edited PTP1588V2 message.

Preferably, the above-mentioned fixed reserved field is the correction field of the above-mentioned PTP1588V2 message.

Preferably, the encapsulation format of the above-mentioned PTP1588V2 message includes a PTP1588V2 message encapsulated at the segment layer, a PTP1588V2 message encapsulated at the LSP (Label Switching Path) layer, a PTP1588V2 message encapsulated at the PW layer, an Ethernet PTP1588V2 message encapsulated at the PW layer, and a PW Layer-encapsulated IP PTP1588V2 packets.

Preferably, the timestamp of the MPLS-TP encapsulated PTP1588V2 message received by the above-mentioned record, and the value step of updating the fixed reserved field of the above-mentioned PTP1588V2 message according to the above-mentioned timestamp is specifically:

Record the timestamp of the received PTP1588V2 message;

Determine whether the above-mentioned PTP1588V2 message is a PTP1588V2 message encapsulated by MPLS-TP; if so, take out the current value of the correction field of the above-mentioned PTP1588V2 message, subtract the timestamp of the above-mentioned record, and update the correction field of the above-mentioned PTP1588V2 message with the obtained difference value; otherwise, transparently transmit the above PTP1588V2 message.

Preferably, the above-mentioned step of generating corresponding processing instructions according to the encapsulation format of the PTP1588V2 message specifically includes the following steps:

Determine the encapsulation format of the above PTP1588V2 message;

If the encapsulation format of the above-mentioned PTP1588V2 message is a PTP1588V2 message encapsulated at the segment layer, the link number of the above-mentioned PTP1588V2 message is the sum of the logical port number and VLAN (Virtual Local Area Network, virtual local area network); message, the link number of the above PTP1588V2 message is the sum of the logical port number and the LSP label; if it is a PTP1588V2 message encapsulated at the PW layer, an Ethernet PTP1588V2 message encapsulated at the PW layer, and an IP (Internet Protocol, Internet Protocol) PTP1588V2 message, then the connection number of the above PTP1588V2 message is the sum of the logical port number, LSP label and PW label;

According to the link number of the above-mentioned PTP1588V2 message, search the configuration information of the above-mentioned link, and obtain its port attribute and message type;

According to the above-mentioned port attribute and message type, generate the processing instruction of the above-mentioned PTP1588V2 message.

Preferably, the above-mentioned steps of editing the above-mentioned PTP1588V2 message according to the processing instruction are specifically:

Parse the above PTP1588V2 message;

According to the analysis result and the above-mentioned processing instructions, perform asymmetric compensation and timestamp processing on the above-mentioned PTP1588V2 message.

Preferably, the steps for performing timestamp synchronization on the edited PTP1588V2 message are as follows:

Obtain the timestamp of the above PTP1588V2 message;

Determine the message type of the above PTP1588V2 message;

If it is the sync type and the two_step mode and the sourceportID matches successfully, or the Resp type and the two_step mode and the sourceportID matches successfully, then temporarily store the time and frequency of the above PTP1588V2 message and restore the timestamp and correction field; if it is the Req type, then Generate a RESP message; if it is Req type and two_step mode, generate a follow_up message, and send the PTP1588V2 message of the above Req type into the queuing queue, waiting to be sent; if it is other types, it will be directly forwarded to the upper layer for processing;

When the message sending time is up, send the above PTP1588V2 message and record the time stamp.

The present invention further provides a device for implementing clock synchronization in an MPLS-TP network, including a line card and an ASIC integrated chip, each input port of the above-mentioned line card is integrated with a first time stamp processor, and the above-mentioned ASIC integrated chip includes an uplink processing device, downlink processor and protocol processing engine, wherein,

The above-mentioned first timestamp processor is used to record the timestamp of the PTP1588V2 message encapsulated by MPLS-TP received, and updates the value of the fixed reserved field of the above-mentioned PTP1588V2 message according to the above-mentioned timestamp, and sends the above-mentioned PTP1588V2 message to The aforementioned ASIC integrated chip;

The above-mentioned upstream processor is used to generate corresponding processing instructions according to the encapsulation format of the above-mentioned PTP1588V2 message;

The above-mentioned downlink processor is configured to edit the above-mentioned PTP1588V2 message according to the processing instructions generated by the above-mentioned uplink processor;

The above-mentioned protocol processing engine is used to perform time stamp synchronization processing on the PTP1588V2 message edited by the above-mentioned downlink processor.

Preferably, the port of the ASIC integrated chip not connected to the line card is integrated with a second time stamp processor for recording the time stamp of the MPLS-TP-encapsulated PTP1588V2 message received by the ASIC integrated chip.

Preferably, the above-mentioned device further includes a third time stamp processor, which is used to convert externally accessed GPS signals into internal interface signals of the above-mentioned protocol processing engine, and synchronously transmit them to the above-mentioned protocol processing engine.

Preferably, the above-mentioned timestamp processor is used to judge whether the above-mentioned PTP1588V2 message is a PTP1588V2 message encapsulated by MPLS-TP; Subtract the timestamp recorded above from the current value of the domain, and update the value of the correction domain of the PTP1588V2 message with the obtained difference.

Preferably, the above-mentioned upstream processor is used to determine the encapsulation format of the above-mentioned PTP1588V2 message; and when the encapsulation format of the above-mentioned PTP1588V2 message is a PTP1588V2 message encapsulated at the segment layer, the sum of the logical port number and the VLAN is calculated to obtain the above-mentioned PTP1588V2 The link number of the message; when the encapsulation format of the above-mentioned PTP1588V2 message is the PTP1588V2 message encapsulated by the LSP layer, calculate the sum of the logical port number and the LSP label to obtain the link number of the above-mentioned PTP1588V2 message; in the encapsulation of the above-mentioned PTP1588V2 message When the format is a PTP1588V2 message encapsulated at the PW layer, an Ethernet PTP1588V2 message encapsulated at the PW layer, and an IP PTP1588V2 message encapsulated at the PW layer, calculate the sum of the logical port number, LSP label, and PW label to obtain the link number of the above PTP1588V2 message ; And according to the link number of the above-mentioned PTP1588V2 message, search the configuration information of the above-mentioned link, obtain its port attribute and message type, and according to the above-mentioned port attribute and message type, generate the processing instruction of the above-mentioned PTP1588V2 message;

The above-mentioned downlink processor is used to analyze the above-mentioned PTP1588V2 message; and perform asymmetric compensation and time stamp processing on the above-mentioned PTP1588V2 message according to the analysis result and the processing instruction generated by the above-mentioned uplink processor.

Preferably, the above-mentioned protocol processing engine is used to obtain the timestamp of the above-mentioned PTP1588V2 message; determine the message type of the above-mentioned PTP1588V2 message; and the message type of the above-mentioned PTP1588V2 message is a sync type and is a two_step mode while the sourceportID matches successfully , or if it is Resp type and two_step mode and the sourceportID matches successfully, temporarily store the time and frequency recovery timestamp and correction field of the above PTP1588V2 message; when the message type of the above PTP1588V2 message is Req type, generate a RESP message ; When the message type of the above-mentioned PTP1588V2 message is the Req type and the two_step mode, generate a follow_up message, and send the PTP1588V2 message of the above-mentioned Req type into the queuing queue, waiting to be sent; the message type of the above-mentioned PTP1588V2 message For other types, directly forward the above-mentioned PTP1588V2 message to the upper layer for processing; and after the message sending time is up, send the above-mentioned PTP1588V2 message and record the timestamp; and periodically update the local timestamp, and time the above-mentioned timestamp information Send to the above-mentioned first timestamp processor, the second timestamp processor and the above-mentioned third timestamp processor.

Preferably, the above-mentioned first time stamp processor is configured to update the local time stamp when receiving the time stamp information sent by the above-mentioned protocol processing engine;

The second timestamp processor is configured to update the local timestamp when receiving the timestamp information sent by the protocol processing engine;

The third timestamp processor is configured to update the local timestamp when receiving the timestamp information sent by the protocol processing engine.

The present invention only uses one protocol processing engine to process the PTP1588V2 messages received by multiple line cards or non-line cards, which simplifies the design and reduces the cost; and supports the clock processing of PTP1588V2 on MPLS-TP, which solves the problems of the entry of line cards and the like. Timestamp processing issues, and protocol processing engine timestamp coordination and synchronization issues.

Description of drawings

The accompanying drawings described here are used to provide a further understanding of the present invention, and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention, and do not constitute improper limitations to the present invention. In the attached picture:

Fig. 1 is the functional block diagram of the device preferred embodiment that MPLS-TP network of the present invention realizes clock synchronization;

Fig. 2 is the flow chart of a preferred embodiment of the method for implementing clock synchronization in the MPLS-TP network of the present invention;

Fig. 3 is the schematic diagram of the PTP1588V2 message format of MPLS-TP encapsulation;

Fig. 4 is a schematic diagram of a typical application example of the present invention.

detailed description

In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer and clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

As shown in Figure 1, it is the functional block diagram of the preferred embodiment of the device for implementing clock synchronization in the MPLS-TP network of the present invention, and this embodiment includes a line card 10 with N groups of input/output ports and an ASIC integrated chip with N+1 ports 20 and the third time stamp processor 30, each input port of the line card 10 is integrated with a first time stamp processor 101, and the N output ports of the line card 10 are connected to the 1-N ports of the ASIC integrated chip 20 The ASIC integrated chip 20 comprises a second time stamp processor 201, an uplink processor 202, a downlink processor 203 and a protocol processing engine 204, and the second time stamp processor 201 is integrated in a port without a line card. The N+1th port of the chip 20 does not have a line card, so in this embodiment, the second timestamp processor 201 is integrated in this port, wherein,

The first timestamp processor 101 is used to record the timestamp of the MPLS-TP encapsulated PTP1588V2 message received by the line card 10, and update the value of the fixed reserved field of the above-mentioned PTP1588V2 message according to the timestamp, specifically: judge Whether the above-mentioned PTP1588V2 message is a PTP1588V2 message encapsulated by MPLS-TP; and when the above-mentioned PTP1588V2 message is a PTP1588V2 message encapsulated by MPLS-TP, take out the current value of the correction field of the above-mentioned PTP1588V2 message, and subtract the timestamp of the above-mentioned record , and update the value of the above-mentioned PTP1588V2 message correction field with the difference obtained, and send the above-mentioned PTP1588V2 message to the ASIC integrated chip 02; and when receiving the timestamp information sent by the protocol processing engine 204, update the local timestamp;

The second timestamp processor 201 is used to record the timestamp of the MPLS-TP encapsulated PTP1588V2 message received by the ASIC integrated chip 20; and when receiving the timestamp information sent by the protocol processing engine 204, update the local timestamp ;

The upstream processor 202 is used to generate corresponding processing instructions according to the encapsulation format of the above-mentioned PTP1588V2 message; specifically: determine the encapsulation format of the PTP1588V2 message; When calculating the sum of the logical port number and VLAN, the link number of the above-mentioned PTP1588V2 message is obtained; when the encapsulation format of the above-mentioned PTP1588V2 message is the PTP1588V2 message encapsulated by the LSP layer, the sum of the logical port number and the LSP label is calculated to obtain the above-mentioned The link number of the PTP1588V2 message; when the encapsulation format of the above PTP1588V2 message is the PTP1588V2 message encapsulated at the PW layer, the Ethernet PTP1588V2 message encapsulated at the PW layer, and the IP PTP1588V2 message encapsulated at the PW layer, calculate the logical port number and LSP label and the sum of PW labels to obtain the link number of the above-mentioned PTP1588V2 message; and according to the link number of the above-mentioned PTP1588V2 message, look up the configuration information of the above-mentioned link, obtain its port attribute and message type, and according to the above-mentioned port attribute and message type , generate the processing instruction of the PTP1588V2 message;

The downlink processor 203 is used to edit the above-mentioned PTP1588V2 message according to the processing instruction generated by the uplink processor 202; specifically: analyze the PTP1588V2 message, and according to the analysis result and the processing instruction generated by the uplink processor 202, report to the PTP1588V2 Asymmetric compensation and time stamp processing for documents;

The protocol processing engine 204 is used to carry out timestamp synchronization processing to the PTP1588V2 message edited by the downstream processor 203; specifically: obtain the timestamp of the PTP1588V2 message; determine the message type of the PTP1588V2 message; and in the PTP1588V2 message When the type of the message is sync type and the two_step mode and the sourceportID is successfully matched, or the Resp type is the two_step mode and the sourceportID is successfully matched, the time and frequency of the PTP1588V2 message are temporarily stored and the time stamp and correction field are restored; in the PTP1588V2 message When the message type of the PTP1588V2 message is the Req type, a RESP message is generated; when the message type of the PTP1588V2 message is the Req type and the two_step mode, a follow_up message is generated, and the PTP1588V2 message of the Req type is sent to the queue for waiting Send; when the message type of the PTP1588V2 message is other types, directly forward it to the upper layer for processing; and after the message sending time is up, send the PTP1588V2 message in the queue and record the timestamp, and periodically update the local time Stamp, and the above-mentioned time stamp information is regularly sent to the first time stamp processor 101, the second time stamp processor 201 and the third time stamp processor 30;

The third time stamp processor 30 is used to convert the externally accessed GPS signal into the internal interface signal of the above-mentioned protocol processing engine, and transmit it synchronously to the protocol processing engine 204; and when receiving the time stamp sent by the protocol processing engine 204 Update the local timestamp when the information is displayed.

As shown in Figure 2, it is a flow chart of a preferred embodiment of a method for implementing clock synchronization in an MPLS-TP network of the present invention, and this embodiment specifically includes the following steps:

Step S001: Record the timestamp of the received PTP1588V2 message;

Step S002: Determine whether the above-mentioned PTP1588V2 message is an MPLS-TP encapsulated PTP1588V2 message, if so, perform step S003; otherwise, perform step S023;

As shown in Figure 3, it is a schematic diagram of the PTP1588V2 message format encapsulated by MPLS-TP. The encapsulation format of the PTP1588V2 message includes the PTP1588V2 message encapsulated by the segment layer, as shown in a in the figure; the PTP1588V2 message encapsulated by the LSP layer, such as As shown in b in the figure; the PTP1588V2 message encapsulated in the PW layer, as shown in c in the figure; the Ethernet PTP1588V2 message encapsulated in the PW layer, as shown in d in the figure; and the IP PTP1588V2 message encapsulated in the PW layer, As shown in e in the figure; according to the protocol, in the figure, DA represents the destination address; SA represents the source address; VLAN0 represents the first layer VLAN; VLAN1 represents the second layer VLAN; VLAN2 represents the third layer VLAN; Etype represents the Ethernet type Value; Label_ptp indicates MPLS Label For PTP; Label_1 indicates the first layer label of MPLS; Label_2 indicates the second layer label of MPLS; Gach indicates Generic associated channel; PTP1588_payload indicates the payload of PTP1588 message; ;IP_PTP1588_payload indicates the IP-encapsulated PTP1588 message payload; IP head indicates the IP header; UDP head indicates the UDP header; CRC indicates the CRC check value;

Step S003: Take out the current value of the correction field of the above-mentioned PTP1588V2 message, subtract the time stamp of the above-mentioned record, and use the obtained difference to update the value of the correction field of the above-mentioned PTP1588V2 message;

In this embodiment, the fixed reserved field is the correction field of the above-mentioned PTP1588V2 message;

If the above-mentioned PTP1588V2 message is received by the input port of the line card 01, then steps S001-step S003 are received by the first timestamp processor 101; if the above-mentioned PTP1588V2 message is received by the port of the ASIC integrated chip 20 that is not connected to the line card , then steps S001-step S003 are executed by the second timestamp processor 201; the PTP1588V2 message processed by the timestamp processor is sent to the upstream processor 202 for processing;

Step S004: The upstream processor 202 determines the encapsulation format of the above-mentioned PTP1588V2 message, if it is a PTP1588V2 message encapsulated at the segment layer, then execute step S005; if it is a PTP1588V2 message encapsulated at the LSP layer, then execute step S006; if it is a PW layer encapsulated The encapsulated PTP1588V2 message, the Ethernet PTP1588V2 message encapsulated by the PW layer, and the IP PTP1588V2 message encapsulated by the PW layer, then execute step S007;

Step S005: Calculate the sum of the logical port number and the VLAN, obtain the link number of the above-mentioned PTP1588V2 message, and proceed to step S008 for execution;

Step S006: Calculate the sum of the logical port number and the LSP label to obtain the link number of the above-mentioned PTP1588V2 message, and proceed to step S008 for execution;

Step S007: Calculate the sum of the logical port number, LSP label and PW label to obtain the link number of the above PTP1588V2 message;

Step S008: According to the link number of the above-mentioned PTP1588V2 message, search for the configuration information of the above-mentioned link, and obtain its port attribute and message type;

Step S009: According to the above-mentioned port attribute and message type, generate the processing instruction of the above-mentioned PTP1588V2 message, and transmit the above-mentioned instruction to the downlink processor 203;

Step S010: the downlink processor 203 parses the above PTP1588V2 message;

Step S011: Perform asymmetric compensation and time stamp processing on the above PTP1588V2 message according to the analysis result and the received processing instruction, and then send the PTP1588V2 message to the protocol engine 204;

Step S012: the protocol engine 204 obtains the time stamp of the above-mentioned PTP1588V2 message;

Step S013: Determine the message type of the above-mentioned PTP1588V2 message, if it is a sync type or a Req type, then perform step S014; if it is a Resp type, then perform step S018; if it is another type, then perform step S024;

Step S014: Determine whether the above-mentioned PTP1588V2 message is in the two_step mode, if so, execute step S015; otherwise, execute step S017;

Step S015: Waiting for the follow_up message to be matched;

Step S016: Determine whether the sourceportID of the above PTP1588V2 message matches successfully, if so, the processing of the above PTP1588V2 message ends; otherwise, execute step S017;

Step S017: Temporarily store the time and frequency of the above PTP1588V2 message, restore the timestamp and the correction field, and end;

Step S018: Generate a RESP message;

Step S019: Determine whether the above-mentioned PTP1588V2 message is in two_step mode, if so, execute step S020; otherwise, execute step S021;

Step S020: generate a follow_up message;

Step S021: Send the above PTP1588V2 message into the queuing queue, waiting to be sent;

Step S022: When the message sending time is up, send the above PTP1588V2 message and record the timestamp, and end;

Step S023: Transparently transmit the above PTP1588V2 message, end;

Step S024: directly forward the above-mentioned PTP1588V2 message to the upper layer for processing, and end.

As shown in Figure 4, it is a schematic diagram of a typical application example of the present invention; in the figure, the MPLS-TP-1588 part is an MPLS-TP network, including edge PE nodes and intermediate P nodes; CE nodes are encapsulated by Ethernet or IP PTP1588V2 The message communicates with the PE node; a typical application is that the CE node is an OC (Ordinary Clock, ordinary clock) /BC (Boundary Clock, boundary clock) node, the PE node is an OC/BC node, and the P node can be a TC (Transparent Clock, Transparent clock) or BC node; MPLS-TP 1588 protocol is run between PE-P-PE, so that the clock synchronization between CE and PE nodes can be realized by using PTP1588V2 packets encapsulated by Ethernet or IP , and the MPLS-TP-encapsulated PTP1588V2 packets are run from PE node to PE node for clock synchronization, thereby realizing clock synchronization of the entire network. PW-encapsulated PTP1588V2 packets can also be run between PEs and PE nodes, segment-layer-encapsulated PTP1588V2 packets can be run between adjacent nodes, and LSP-encapsulated PTP1588V2 packets can be run on end-to-end nodes. The label distribution may adopt an LDP (label distribution protocol, label distribution protocol) protocol. For example, when the pdelay measurement mechanism is run between two points, the master node sends a 1588 message encapsulated at the segment layer to the slave node, and the slave node automatically replies with a PTP1588V2 message encapsulated at the segment layer in the opposite direction after receiving the detection process, realizing the master-slave Time handshake to achieve the effect of measuring the link delay of the master-slave node.

The foregoing description shows and describes preferred embodiments of the present invention, but as previously stated, it should be understood that the present invention is not limited to the form disclosed herein, and should not be viewed as excluding other embodiments, but can be used in various Other combinations, modifications and circumstances, and can be modified within the scope of the inventive concept described herein, by the above teachings or by skill or knowledge in the relevant field. However, changes and changes made by those skilled in the art do not depart from the spirit and scope of the present invention, and should all be within the protection scope of the appended claims of the present invention.

Claims (14)

1. a kind of MPLS-TP network realizes the synchronous method of clock, it is characterised in that comprise the following steps：

The timestamp of the PTP1588V2 messages of the MPLS-TP encapsulation that record is received, and according to the update of time stamp The value of the fixed reserved field of PTP1588V2 messages；

According to the encapsulation format of the PTP1588V2 messages, corresponding process instruction is generated；

According to the process instruction, edlin is entered to the PTP1588V2 messages；

Timestamp synchronization process is carried out to the PTP1588V2 messages after editor.

2. method according to claim 1, it is characterised in that the fixed reserved field is the PTP1588V2 messages Correction domain.

3. method according to claim 1, it is characterised in that the encapsulation format of the PTP1588V2 messages includes section layer The PTP1588V2 messages of encapsulation, the PTP1588V2 messages of LSP layers encapsulation, the PTP1588V2 messages of PW layers encapsulation, the encapsulation of PW layers Ether PTP1588V2 messages and PW layers encapsulation IP PTP1588V2 messages.

4. method according to claim 2, it is characterised in that the PTP1588V2 of the MPLS-TP encapsulation that the record is received The timestamp of message, and the value step of the fixed reserved field of PTP1588V2 messages is specially according to the update of time stamp：

The timestamp of the PTP1588V2 messages that record is received；

Judge that whether the PTP1588V2 messages are the PTP1588V2 messages of MPLS-TP encapsulation；If so, then take out described PTP1588V2 messages correct the currency in domain, deduct the timestamp of the record, and update described with the difference for obtaining PTP1588V2 messages correct the value in domain；Otherwise, PTP1588V2 messages described in transparent transmission.

5. method according to claim 4, it is characterised in that the encapsulation format according to PTP1588V2 messages, generates Corresponding process instruction step specifically includes following steps：

Determine the encapsulation format of the PTP1588V2 messages；

If the encapsulation format of the PTP1588V2 messages is the PTP1588V2 messages of section layer encapsulation, the PTP1588V2 reports The link number of text is logical port number and VLAN sums；If the PTP1588V2 messages of LSP layers encapsulation, the then PTP1588V2 The link number of message is logical port number and LSP label sum；If the PTP1588V2 messages of PW layers encapsulation, PW layers are encapsulated Ether PTP1588V2 messages and the IP PTP1588V2 messages of PW layers encapsulation, then the link number of the PTP1588V2 messages is Logical port number, LSP label and PW label sums；

According to the link number of the PTP1588V2 messages, the configuration information of the link is searched, its port attribute and message is obtained Type；

According to the port attribute and type of message, the process instruction of the PTP1588V2 messages is generated.

6. method according to claim 1, it is characterised in that described according to process instruction, to the PTP1588V2 messages Carry out edit step to be specially：

Parse the PTP1588V2 messages；

According to analysis result and the process instruction, asymmetry compensation is carried out to the PTP1588V2 messages and timestamp is processed.

7. method according to claim 1, it is characterised in that the PTP1588V2 messages after described couple of editor carry out the time Stamp synchronization process step is specially：

Obtain the timestamp of the PTP1588V2 messages；

Determine the type of message of the PTP1588V2 messages；

If sync types and for two_step patterns simultaneously sourceportID the match is successful, or be Resp types and be Two_step patterns simultaneously sourceportID the match is successful, then the Time And Frequency for keeping in the PTP1588V2 messages recovers Timestamp and correction domain；If Req types, then RESP messages are generated；If Req types and be two_step patterns, then generate Follow_up messages, and the PTP1588V2 messages of the Req types are sent into into queue queue, wait to be sent；If other classes Type, then be directly forwarded to upper strata process；

Message sends the time to sending the PTP1588V2 messages logging timestamp.

8. a kind of MPLS-TP network realizes the synchronous device of clock, including line card and ASIC integrated chips, it is characterised in that institute State be integrated with each input port of line card the very first time stamp processor, the ASIC integrated chips include upstream processor, Downstream processor and network protocol processing engine, wherein,

The very first time stabs processor, for recording the timestamp of the PTP1588V2 messages of the MPLS-TP for receiving encapsulation, and The value of the fixed reserved field of PTP1588V2 messages according to the update of time stamp, the PTP1588V2 messages are sent to The ASIC integrated chips；

The upstream processor, for the encapsulation format according to the PTP1588V2 messages, generates corresponding process instruction；

The downstream processor, for the process instruction generated according to the upstream processor, enters to the PTP1588V2 messages Edlin；

The network protocol processing engine, it is same for carrying out timestamp to the PTP1588V2 messages after the downstream processor editor described in Step process.

9. device according to claim 8, it is characterised in that the port Nei Ji of the not connected line card of the ASIC integrated chips Into there is the second timestamp processor, for record the PTP1588V2 messages of the MPLS-TP encapsulation that ASIC integrated chips are received when Between stab.

10. device according to claim 8 or claim 9, it is characterised in that described device also includes the 3rd timestamp processor, For the outside gps signal for accessing to be converted into the internal interface signal of the network protocol processing engine, and synchronous transfer to described Network protocol processing engine.

11. devices according to claim 10, it is characterised in that the very first time stamp processor and second time Stamp processor, for judging that whether the PTP1588V2 messages are the PTP1588V2 messages of MPLS-TP encapsulation；And described When PTP1588V2 messages are the PTP1588V2 messages of MPLS-TP encapsulation, the current of the PTP1588V2 messages correction domain is taken out Value, deducts the timestamp of the record, and updates the value that the PTP1588V2 messages correct domain with the difference for obtaining.

12. devices according to claim 10, it is characterised in that the upstream processor, it is described for determining The encapsulation format of PTP1588V2 messages；And the PTP1588V2 messages encapsulation format be section layer encapsulation PTP1588V2 During message, calculating logic port numbers and VLAN sums obtain the link number of the PTP1588V2 messages；In the PTP1588V2 When the encapsulation format of message is the PTP1588V2 messages of LSP layers encapsulation, calculating logic port numbers and LSP label sum obtain institute State the link number of PTP1588V2 messages；In the PTP1588V2 reports that the encapsulation format of the PTP1588V2 messages is the encapsulation of PW layers During the IP PTP1588V2 messages of text, the ether PTP1588V2 messages of PW layers encapsulation and the encapsulation of PW layers, calculating logic port Number, LSP label and PW label sums, obtain the link number of the PTP1588V2 messages；And according to the PTP1588V2 The link number of message, searches the configuration information of the link, obtains its port attribute and type of message, and is belonged to according to the port Property and type of message, generate the process instruction of the PTP1588V2 messages；

The downstream processor, for parsing the PTP1588V2 messages；And given birth to according to analysis result and the upstream processor Into process instruction, asymmetry compensation and timestamp are carried out to the PTP1588V2 messages and are processed.

13. devices according to claim 10, it is characterised in that the network protocol processing engine, it is described for obtaining The timestamp of PTP1588V2 messages；Determine the type of message of the PTP1588V2 messages；And in the PTP1588V2 messages Type of message be sync types and for two_step patterns simultaneously sourceportID the match is successful, or be Resp types and be Two_step patterns simultaneously sourceportID when the match is successful, the Time And Frequency for keeping in the PTP1588V2 messages recovers Timestamp and correction domain；When the type of message of the PTP1588V2 messages is Req types, RESP messages are generated；Described The type of message of PTP1588V2 messages be Req types and for two_step patterns when, generate follow_up messages, and will be described The PTP1588V2 messages of Req types send into queue queue, wait to be sent；It is which in the type of message of the PTP1588V2 messages During his type, the PTP1588V2 messages are directly forwarded to into upper strata process；And the time is sent to after in message, send institute State PTP1588V2 messages logging timestamp；And local time stamp is periodically updated, and timestamp information timing is sent out Give the very first time stamp processor, the second timestamp processor and the 3rd timestamp processor.

14. devices according to claim 13, it is characterised in that the very first time stabs processor, for receiving When stating the timestamp information that network protocol processing engine sends, local time stamp is updated；

The second timestamp processor, for when the timestamp information that the network protocol processing engine sends is received, updating Local time stamp；

The 3rd timestamp processor, for when the timestamp information that the network protocol processing engine sends is received, updating Local time stamp.