CN103427649A - Power converter and its control method - Google Patents

Abstract

The invention discloses a power converter, which comprises a full-bridge type switching circuit, a resonance circuit, a transformer, an overvoltage protection unit, a pulse width modulation control unit, a trigger control unit and a driving unit. The overvoltage protection unit detects the output voltage of the power converter and generates an output voltage signal. The pulse width modulation control unit generates a pulse width modulation signal. The trigger control unit receives the output voltage signal and the pulse width modulation signal and generates a trigger control signal. When the overvoltage protection unit detects that the output voltage is an overvoltage, the trigger control unit outputs a low-level trigger control signal to disable the driving unit when the working period of the pulse width modulation signal is finished.

Description

Power converter and its control method

technical field

The present invention relates to a power converter and a control method thereof, in particular to a power converter for a charging device of a mobile vehicle and a control method thereof.

Background technique

Today, the development of mobile vehicles has moved towards pollution-free, high-efficiency electric drives. However, the energy for electric drive must pass through the battery as a container for energy storage, so that energy can be stored in the battery. By converting energy, such as firepower, waterpower, windpower, thermal energy, solar energy, and nuclear energy, etc. into electrical energy, the electrical energy can be properly converted and stored in the battery. However, in the process of power conversion, issues such as safety, high efficiency, and convenience must be considered.

Please refer to FIG. 1 , which is a schematic block diagram of a mobile vehicle charging device in the prior art. As shown in the figure, the charging device 10A receives an external AC voltage Vs, and converts the external AC voltage Vs into a DC output voltage Vo to charge a rechargeable battery 20A.

The charging device 10A includes an electromagnetic interference filter 102A, a power factor corrector 104A, an isolated power converter 106A (isolated DC-to-DC converter) and a non-isolated power converter 108A (non-isolated DC- to-DC converter). The EMI filter 102A receives the external AC power Vs to eliminate the noise of the AC power Vs and prevent the interference of conductive electromagnetic noise. The power factor corrector 104A is electrically connected to the EMI filter 102A to improve the power factor of the converted DC power. The isolated power converter 106A is electrically connected to the power factor corrector 104A to convert and output the energy generated by the DC voltage output by the power factor corrector 104A. The non-isolated power converter 108A is electrically connected to the isolated power converter 106A to provide conversion and adjustment of different DC output voltage Vo levels, and then output the required charging voltage level of the rechargeable battery 20A.

It is worth mentioning that in the current practical application, the isolated power converter 106A mainly adopts an LLC full-bridge series resonant converter (LLC full-bridge series resonant converter). The resonant converter uses a resonant circuit and frequency modulation to make the current phase lag behind the voltage phase according to the load characteristics to achieve zero-voltage switching; or if the current phase leads the voltage phase, zero-current switching can be achieved. Traditional resonant converters are mainly divided into series resonance, parallel resonance and series-parallel resonance. Although these three circuit architectures can achieve zero-voltage or zero-current switching, for series resonant converters, under light-load operation conditions, the output voltage cannot be adjusted, resulting in voltage regulation problems. The LLC resonant converter is evolved from the combination of a half-bridge or full-bridge converter and a series resonant circuit. When operating at a normal operating voltage, the duty cycle of the power switch operates at a complementary signal close to 50%, and The output voltage is stabilized by switching frequency modulation.

For reference, FIG. 2 is a schematic block diagram of an LLC full-bridge series resonant converter in the prior art. The control structure of the isolated power converter 106A is an open-loop design. Due to the open-loop circuit structure, the voltage regulation characteristics of its output voltage are related to the size of the load, the size of the duty cycle, and the conduction voltage drop of the power element. Therefore, when the isolated power converter 106A operates in the light-load mode, its output voltage It will continue to increase upwards, resulting in poor voltage regulation characteristics. Therefore, in order to achieve stable voltage control under light load, the control loop usually uses over-voltage protection.

Please refer to FIG. 2 , which is a schematic circuit block diagram of a power converter of a charging device in the prior art. The power converter 106A of the charging device is electrically connected to a DC input voltage (not shown), so as to convert and output the energy generated by the DC input voltage. The power converter 106A includes a full bridge switching circuit 1061A, a resonant circuit 1062A, a transformer 1063A, an overvoltage protection unit 1064A, a pulse width modulation control unit 1065A and a driving unit 1067A.

The full-bridge switching circuit 1061A includes two bridge arms (not shown) composed of four power switching elements for switching the DC input voltage into a square wave voltage (not shown). The resonant circuit 1062A is electrically connected to the full-bridge switching circuit 1061A to receive and convert the square wave voltage into a resonant voltage (not shown). Wherein, the resonant circuit 1062A includes a resonant capacitor Cr and two resonant inductors (respectively a leakage inductance Lr and a magnetizing inductor (not shown)), forming an LLC resonant circuit. The transformer 1063A has an input side and an output side, and the input side is electrically connected to the resonant circuit 1062A to receive the resonant voltage. Wherein, the input side includes at least one primary winding (not marked), and the output side includes at least one secondary winding (not marked). As mentioned above, the resonant inductance included in the resonant circuit 1062A is the leakage inductance Lr and the magnetizing inductance inside the primary side of the transformer 1063A.

The overvoltage protection unit 1064A is electrically connected to the output side of the transformer 1063A to detect the output voltage of the power converter 106A and generate an output voltage signal Sovp to provide overvoltage output protection for the power converter 106A. The pulse width modulation (PWM) control unit 1065A generates a pulse width modulation signal. Wherein, since the full-bridge switching circuit 1061A is composed of two groups of bridge arms, and each group of bridge arms is composed of two power switching elements, the pulse width modulation signal generated by the pulse width modulation control unit 1065A It includes a first pulse width modulation signal Spwm1 and a second pulse width modulation signal Spwm2, wherein the on and off of the first pulse width modulation signal Spwm1 and the second pulse width modulation signal Spwm2 are complementary level.

Wherein, when the overvoltage protection unit 1064A detects that the power converter 106A has an overvoltage output, the overvoltage protection unit 1064A generates the output voltage signal Sovp to disable the driving unit 1067A for the full bridge mode switching circuit 1061A driving. Conversely, when the over-voltage output condition is eliminated, the over-voltage protection unit 1064A detects that the power converter 106A is outputting an operating voltage, and the over-voltage protection unit 1064A generates the output voltage signal Sovp to enable (enable) the drive unit 1067A drives the full bridge switching circuit 1061A. In addition, the power converter 106A further includes an optical coupling unit 1068A, so that the overvoltage protection unit 1064A can transmit the output voltage signal Sovp to the driving unit 1067A through the optical coupling unit 1068A.

However, the above-mentioned output voltage signal Sovp disables or enables the driving unit 1067A, because when the overvoltage protection unit 1064A detects that the power converter 106A has an overvoltage output or when the overvoltage output condition is eliminated, a random shutdown occurs immediately. The action of breaking and opening randomly. For cooperation, refer to FIG. 3 , which is a control timing diagram of the pulse width modulation control unit and the drive unit in the prior art. As shown in the figure, from top to bottom respectively represent the first pulse width modulation signal Spwm1, the second pulse width modulation signal Spwm2, the short circuit prevention time Td, the output voltage signal Sovp, the gate driving signal Sga, Sgd and the gate drive signals Sgb, Sgc.

As mentioned above, the first pulse width modulation signal Spwm1 and the second pulse width modulation signal Spwm2 are complementary on and off, wherein the first pulse width modulation signal Spwm1 is a conduction signal in a time interval t10-t11 On state (at this time, the second pulse width modulation signal Spwm2 is off state); the second pulse width modulation signal Spwm2 is on state in a time interval t12～t13 (at this time, the first pulse width modulation signal The signal Spwm1 is turned off), and the first pulse width modulation signal Spwm1 and the second pulse width modulation signal Spwm2 are periodically and complementary switched on and off.

Furthermore, assuming that the power converter 106A produces an overvoltage output at a time tov, that is, when the overvoltage protection unit 1064A detects that the power converter 106A has an overvoltage output, therefore, the overvoltage protection unit 1064A The generated output voltage signal Sovp is a low level signal. Because when the overvoltage output occurs (that is, occurs in the time interval t12～t13), the second pulse width modulation signal Spwm2 is in a high-level conduction state (relatively, the first pulse width modulation signal Spwm1 is Therefore, the output voltage signal Sovp immediately changes from a high level to a low level, and the driving unit 1067A is disabled. Similarly, if an overvoltage output occurs at any time point within the time interval t12˜t13, the output voltage signal Sovp generated by the overvoltage protection unit 1064A randomly turns off the driving unit 1067A.

On the contrary, assuming that the power converter 106A eliminates the over-voltage output condition at a time tnv, that is, the over-voltage protection unit 1064A detects that the power converter 106A is outputting an operating voltage, therefore, the over-voltage protection unit 1064A generates The output voltage signal Sovp is a high level signal. Because when the working voltage output occurs (that is, occurs in the time interval t14-t15), the first pulse width modulation signal Spwm1 is in a high-level conduction state (relatively, the second pulse width modulation signal Spwm2 is Therefore, the output voltage signal Sovp immediately changes from a low level to a high level, thereby enabling the driving unit 1067A to drive the full-bridge switching circuit 1061A. Similarly, if the overvoltage output condition is excluded at any time point in the time interval t14˜t15, the output voltage signal Sovp generated by the overvoltage protection unit 1064A randomly turns on the driving unit 1067A.

Therefore, the duty cycle (duty cycle) of the square wave signal that will cause the disabling or enabling the driving unit 1067A is an incomplete cycle, that is, the square wave cycle that may be 5%, 10% or 15% is random. Turning off and turning on the driving unit 1067A at random, in this way, the energy stored in the energy storage element cannot be released in one working cycle, but the energy will be released instantaneously in the next cycle, resulting in short-circuit (short through) phenomenon. .

Therefore, how to design a power converter and its control method, when the overvoltage protection unit detects the overvoltage output of the power converter, the output voltage signal generated by the overvoltage protection unit controls the trigger control unit, so that the trigger control At the end of the duty cycle of the pulse width modulation signal, the unit outputs a trigger control signal to disable the driving unit, which is a major problem that the creators of this project want to overcome and solve.

Contents of the invention

An object of the present invention is to provide a power converter to overcome the problems of the prior art.

The power converter of the present invention includes a full bridge switching circuit, a resonant circuit, a transformer, an overvoltage protection unit, a pulse width modulation control unit, a trigger control unit and a drive unit.

The full bridge switching circuit converts a DC input voltage into a square wave voltage. The resonant circuit is electrically connected to the full bridge switching circuit, receives the square wave voltage and converts it into a resonant voltage. The transformer has an input side and an output side, and the input side is electrically connected to the resonant circuit to receive the resonant voltage. The overvoltage protection unit is electrically connected to the output side, detects an output voltage of the output side, and generates an output voltage signal. The PWM control unit generates a PWM signal. The trigger control unit receives the output voltage signal and the pulse width modulation signal, and generates a trigger control signal. The driving unit receives the trigger control signal and the pulse width modulation signal to drive the full-bridge switching circuit to be turned on and off.

Wherein, when the overvoltage protection unit detects that the output voltage is an overvoltage, the trigger control unit outputs the low level trigger control signal to disable ( disable) the drive unit.

Another object of the present invention is to provide a control method of a power converter to overcome the problems of the prior art. Therefore, the steps of the control method of the power converter of the present invention include: (a) providing a full-bridge switching circuit, a resonant circuit and a transformer; (b) providing an overvoltage protection unit to detect an output voltage of the power converter , and generate an output voltage signal; (c) provide a pulse width modulation control unit to generate a pulse width modulation signal; (d) provide a trigger control unit to receive the output voltage signal and the pulse width modulation signal, And generate a trigger control signal; (e) provide a driving unit, receive the trigger control signal and the pulse width modulation signal, drive the full bridge switching circuit on and off; and (f) when the overvoltage protection unit When detecting that the output voltage is an overvoltage, the trigger control unit outputs the trigger control signal at a low level to disable the driving unit when the duty cycle of the PWM signal ends.

In order to further understand the technology, means and effects that the present invention adopts to achieve the predetermined purpose, please refer to the following detailed description and accompanying drawings of the present invention. It is believed that the purpose, characteristics and characteristics of the present invention can be obtained from this For specific understanding, the accompanying drawings are only for reference and illustration, and are not intended to limit the present invention.

Description of drawings

FIG. 1 is a schematic block diagram of a mobile vehicle charging device in the prior art;

2 is a schematic block diagram of a prior art LLC full-bridge series resonant converter;

FIG. 3 is a control timing diagram of the pulse width modulation control unit and the drive unit in the prior art;

Fig. 4 is a circuit block diagram of a power converter of the charging device of the present invention;

Fig. 5 is the circuit diagram of this trigger control unit of the present invention;

6 is a control timing diagram of the pulse width modulation control unit, the trigger control unit and the drive unit of the present invention; and

FIG. 7 is a flow chart of the control method of the power converter of the charging device according to the present invention.

Wherein, the reference signs are explained as follows:

﹝current technology﹞

10A charging device;

102A electromagnetic interference filter;

104A power factor corrector;

106A isolated power converter;

108A non-isolated power converter;

20A rechargeable battery;

1061A full bridge switching circuit;

1062A resonant circuit;

1063A transformer;

1064A overvoltage protection unit;

1065A pulse width modulation control unit;

1067A drive unit;

1068A optical coupling unit;

Vs external AC voltage;

Vo DC output voltage;

Cr resonant capacitor;

Lr resonant inductance;

Sovp output voltage signal;

Spwm1 first pulse width modulation signal;

Spwm2 second pulse width modulation signal;

Td short circuit prevention time;

Sga～Sgd gate drive signal;

t10～t15 time;

tov overvoltage output time;

tnv working voltage output time;

﹝this invention﹞

102 electromagnetic interference filter;

104 power factor corrector;

106 isolated power converters;

108 non-isolated power converters;

1061 full bridge switching circuit;

1062 resonant circuit;

1063 transformer;

1064 overvoltage protection unit;

1065 pulse width modulation control unit;

1066 trigger control unit;

1067 drive units;

1068 optical coupling unit;

10662 positive edge triggered D-type flip-flop;

10664 NOR gate;

Qa first power switching element;

Qb second power switching element;

Qc third power switching element;

Qd fourth power switching element;

Cr resonant capacitor;

Lr resonant inductance;

Sovp output voltage signal;

Spwm1 first pulse width modulation signal;

Spwm2 second pulse width modulation signal;

Td short circuit prevention time;

Ty1 delay time;

Ty2 delay time;

Sen triggers the control signal;

Sga first gate drive signal;

Sgb second gate drive signal;

Sgc third gate drive signal;

Sgd fourth gate drive signal;

D data input terminal;

CLK clock pulse input terminal;

Q output;

t20～t25 time;

tov overvoltage output time;

tnv working voltage output time;

Steps S100 to S600.

Detailed ways

Hereby, the technical content and detailed description of the present invention are described as follows in conjunction with the drawings:

Please refer to FIG. 4 , which is a schematic circuit block diagram of the power converter of the charging device of the present invention. Wherein, the charging device includes an electromagnetic interference filter, a power factor corrector 104, an isolated power converter 106 (isolated DC-to-DC converter) and a non-isolated power converter 108 (non-isolated DC- to-DC converter). Except for the isolated power converter 106 , the above-mentioned circuit device and its circuit structure are the same as those disclosed in the prior art, so details are not repeated here. In the following, the power converter 106 will be described in detail.

The power converter 106 of the charging device is electrically connected to a DC input voltage (not shown) to convert and output the energy generated by the DC input voltage. The power converter 106 includes a full bridge switching circuit 1061 , a resonant circuit 1062 , a transformer 1063 , an overvoltage protection unit 1064 , a PWM control unit 1065 , a trigger control unit 1066 and a drive unit 1067 .

The full-bridge switching circuit 1061 includes two bridge arms (not shown) composed of four power switching elements for switching the DC input voltage into a square wave voltage (not shown). That is, the full-bridge switching circuit 1061 has a first power switch element Qa, a second power switch element Qb, a third power switch element Qc, and a fourth power switch element Qd. In addition, the full-bridge switching circuit 1061 is composed of two sets of bridge arms (not shown), and each set of bridge arms is composed of the above two power switching elements. Wherein, the first power switch element Qa and the second power switch element Qb form a first bridge arm; the third power switch element Qc and the fourth power switch element Qd form a second bridge arm. It is worth mentioning that the first bridge arm and the second bridge arm of the full-bridge switching circuit 1061 are complementary on and off with a short-circuit prevention time (dead time) or dead time, so as to avoid The situation where two power switching elements are short-circuited in a non-completely on or off state.

The resonant circuit 1062 is electrically connected to the full-bridge switching circuit 1061 to receive and convert the square wave voltage into a resonant voltage (not shown). Wherein, the resonant circuit 1062 includes a resonant capacitor Cr and two resonant inductors (respectively a leakage inductance Lr and a magnetizing inductor (not shown)), forming an LLC resonant circuit.

The transformer 1063 has an input side and an output side, and the input side is electrically connected to the resonant circuit 1062 to receive the resonant voltage. Wherein, the input side includes at least one primary winding (not marked), and the output side includes at least one secondary winding (not marked). As mentioned above, the resonant inductance included in the resonant circuit 1062 is the leakage inductance Lr and the magnetizing inductance inside the primary side of the transformer 1063 .

The overvoltage protection unit 1064 is electrically connected to the output side of the transformer 1063 to detect the output voltage of the power converter 106 and generate an output voltage signal Sovp to provide overvoltage output protection for the power converter 106 . That is, when the power converter 106 has an abnormal voltage exceeding its operating voltage during operation, the overvoltage protection unit 1064 generates the output voltage signal Sovp, and then provides the power converter 106 with an overvoltage output signal. Protect. The pulse width modulation (PWM) control unit 1065 generates a pulse width modulation signal. Wherein, since the full-bridge switching circuit 1061 is composed of two groups of bridge arms, and each group of bridge arms is composed of two power switching elements, the pulse width modulation signal generated by the pulse width modulation control unit 1065 It includes a first pulse width modulation signal Spwm1 and a second pulse width modulation signal Spwm2, wherein the on and off of the first pulse width modulation signal Spwm1 and the second pulse width modulation signal Spwm2 are complementary level. Furthermore, taking this embodiment as an example, the first pulse width modulation signal Spwm1 controls the first power switch element Qa and the fourth power switch element Qd; the second pulse width modulation signal Spwm2 controls the second power The switching element Qb and the third power switching element Qc.

The trigger control unit 1066 receives the output voltage signal Sovp and the PWM signals Spwm1 , Spwm2 , and generates a trigger control signal Sen. The operation of the trigger control unit 1066 will be described in more detail later. The driving unit 1067 receives the trigger control signal Sen and the pulse width modulation signals Spwm1 , Spwm2 to generate gate driving signals Sga˜Sgd corresponding to driving the plurality of power switching elements Qa˜Qd on and off. That is, the first gate drive signal Sga drives the first power switch element Qa, the second gate drive signal Sgb drives the second power switch element Qb, and the third gate drive signal Sgc drives the third power switch element Qa. The switching element Qc and the fourth gate driving signal Sgd drive the fourth power switching element Qd.

Wherein, when the overvoltage protection unit 1064 detects that the output voltage is an overvoltage, the output voltage signal Sovp generated by the overvoltage protection unit 1064 controls the trigger control unit 1066, so that the trigger control unit 1066 is within the pulse width When the duty cycle of the modulation signals Spwm1 and Spwm2 ends, the trigger control signal Sen is output to disable the drive unit 1067 from driving the full-bridge switching circuit 1061 . Conversely, when the over-voltage output condition is eliminated, the over-voltage protection unit 1064 detects that the power converter 106 is outputting an operating voltage, the output voltage signal Sovp generated by the over-voltage protection unit 1064 controls the trigger control unit 1066, so that The trigger control unit 1066 outputs the trigger control signal Sen to enable the driving unit 1067 to drive the full-bridge switching circuit 1061 when the duty cycle of the PWM signals Spwm1 and Spwm2 ends. The control of the trigger control signal Sen to disable or enable the trigger control unit 1066 will be described in more detail later. In addition, the power converter 106 further includes an optical coupling unit 1068 , so that the overvoltage protection unit 1064 can transmit the output voltage signal Sovp to the trigger control unit 1066 through the optical coupling unit 1068 .

Please refer to FIG. 5 which is a circuit diagram of the trigger control unit of the present invention. In this embodiment, the trigger control unit 1066 includes a leading-edge triggered D-type flip-flop (leading-edge triggered D-type flip-flop) 10662 and a NOR gate (NOR gate) 10664 . The positive-edge triggered D-type flip-flop 10662 includes a data input terminal D, a clock input terminal CLK and at least one output terminal Q. The NOR gate 10664 includes two input terminals (not labeled) and an output terminal (not labeled), and the output terminal is connected to the clock input terminal CLK. Wherein, the data input terminal D receives the output voltage signal Sovp generated by the overvoltage protection unit 1064 . The two input ends of the NOR gate 10664 receive the pulse width modulation signals Spwm1 and Spwm2 respectively.

Wherein, when the power converter 106 is an over-voltage output, and the first pulse width modulation signal Spwm1 and the second pulse width modulation signal Spwm2 are both low level, the positive-edge triggered D-type flip-flop 10662 outputs low level of the trigger control signal Sen to disable the drive unit 1067 from driving the full-bridge switching circuit. That is, when the overvoltage protection unit 1064 detects that the output voltage is the overvoltage, the output voltage signal Sovp generated by the overvoltage protection unit 1064 controls the trigger control unit 1066, so that the trigger control unit 1066 When the duty cycle of the width modulation signals Spwm1 and Spwm2 ends, the trigger control signal Sen is output at a low level to disable the driving unit 1067 from driving the full-bridge switching circuit 1061 .

In addition, when the power converter 106 outputs the working voltage, and the first pulse width modulation signal Spwm1 and the second pulse width modulation signal Spwm2 are both at low level, the positive-edge triggered D-type flip-flop 10662 outputs high Level of the trigger control signal Sen, so as to enable the driving unit 1067 to drive the full-bridge switching circuit 1061 . That is, when the overvoltage output condition is eliminated, when the overvoltage protection unit 1064 detects that the power converter 106 is outputting a working voltage, the output voltage signal Sovp generated by the overvoltage protection unit 1064 controls the trigger control unit 1066, The trigger control unit 1066 outputs the high level trigger control signal Sen to enable the driving unit 1067 to drive the full-bridge switching circuit 1061 when the duty cycle of the PWM signals Spwm1 and Spwm2 ends. As for the above-mentioned control method, it will be described in detail later in conjunction with the timing diagram.

Please refer to FIG. 6 which is a control timing diagram of the pulse width modulation control unit, the trigger control unit and the driving unit of the present invention. As shown in the figure, from top to bottom respectively represent the first pulse width modulation signal Spwm1, the second pulse width modulation signal Spwm2, the short circuit prevention time Td, the trigger control signal Sen, the gate drive signal Sga, Sgd and the gate drive signals Sgb, Sgc.

As mentioned above, the first pulse width modulation signal Spwm1 and the second pulse width modulation signal Spwm2 are complementary on and off, wherein the first pulse width modulation signal Spwm1 is a conduction signal in a time interval t20-t21 On state (at this time, the second pulse width modulation signal Spwm2 is off state); the second pulse width modulation signal Spwm2 is on state in a time interval t22～t23 (at this time, the first pulse width modulation signal Spwm2 The signal Spwm1 is turned off), and the first pulse width modulation signal Spwm1 and the second pulse width modulation signal Spwm2 are periodically and complementary switched on and off. In addition, a time interval t21-t22 is the short-circuit prevention time Td.

Furthermore, assuming that the power converter 106 is an overvoltage output at a time tov, that is, when the overvoltage protection unit 1064 detects that the power converter 106 is an overvoltage output, therefore, the overvoltage protection unit 1064 The generated output voltage signal Sovp is a low level signal. Because when the overvoltage output occurs (that is, occurs in the time interval t22～t23), the second pulse width modulation signal Spwm2 is in a high-level conduction state (relatively, the first pulse width modulation signal Spwm1 is low level cut-off state), therefore, the levels received by the two input terminals of the NOR gate 10664 of the trigger control unit 1066 are logic 0 level and logic 1 level respectively, so the output of the NOR gate 10664 generates a logic 0 level. At this moment, the logic 0 level is provided to the clock input terminal CLK of the positive-edge triggered D-type flip-flop 10662 . In addition, it is assumed that the positive-edge trigger D-type flip-flop 10662 is a positive-edge trigger D-type flip-flop, and the initial output value is a logic 1 level. For the positive-edge trigger D-type flip-flop 10662, since the clock input terminal CLK is logic 0 level, the output of the positive-edge trigger D-type flip-flop 10662 is logic 1 level (that is, the initial output value) to keep enabling the operation of the driving unit 1067.

Until time t23, when the second pulse width modulation signal Spwm2 changes from a high level on state to a low level off state (at this time, the first pulse width modulation signal Spwm1 is still in a low level off state) Since the first pulse width modulation signal Spwm1 and the second pulse width modulation signal Spwm2 are at time t23 (that is, when the short circuit prevention time dead time occurs), the two signals both provide the input of the NOR gate 10664 Therefore, after the NOR logic operation, the output of the NOR gate 10664 generates a logic 1 level, which is provided to the clock input terminal CLK of the positive-edge triggered D-type flip-flop 10662 . For the positive-edge trigger D-type flip-flop 10662, since the clock input terminal CLK receives a high-level voltage, the output of the positive-edge trigger D-type flip-flop 10662 transitions to a logic 0 level (that is, The output voltage signal Sovp) is a low level signal to disable the operation of the driving unit 1067.

On the contrary, assuming that the power converter 106 eliminates the overvoltage output condition at a time tnv, that is, when the overvoltage protection unit 1064 detects that the power converter 106 is outputting an operating voltage, therefore, the overvoltage protection unit 1064 The generated output voltage signal Sovp is a high level signal. Because when the working voltage output occurs (that is, occurs in the time interval t24-t25), the first pulse width modulation signal Spwm1 is in a high-level conduction state (relatively, the second pulse width modulation signal Spwm2 is low level cut-off state), therefore, the levels received by the two input terminals of the NOR gate 10664 of the trigger control unit 1066 are logic 1 level and logic 0 level respectively, so the output of the NOR gate 10664 generates a logic 0 level. At this moment, the logic 0 level is provided to the clock input terminal CLK of the positive-edge triggered D-type flip-flop 10662 . For the positive-edge trigger D-type flip-flop 10662, since the clock input terminal CLK is logic 0 level, the output of the positive-edge trigger D-type flip-flop 10662 is logic 0 level (that is, to maintain the previous state logic 0 level output value) to keep the operation of the driving unit 1067 disabled.

Until time t25, when the first pulse width modulation signal Spwm1 changes from a high level on state to a low level off state (at this time, the second pulse width modulation signal Spwm2 is still in a low level off state) Since the first pulse width modulation signal Spwm1 and the second pulse width modulation signal Spwm2 are at time t25 (that is, when the short circuit prevention time dead time occurs), the two signals both provide the input of the NOR gate 10664 Therefore, after the NOR logic operation, the output of the NOR gate 10664 generates a logic 1 level, which is provided to the clock input terminal CLK of the positive-edge triggered D-type flip-flop 10662 . For the positive-edge trigger D-type flip-flop 10662, since the clock input terminal CLK receives a high-level voltage, the output of the positive-edge trigger D-type flip-flop 10662 transitions to a logic 1 level (that is, The output voltage signal Sovp) is a high level signal to enable the operation of the driving unit 1067.

In short, through the operation of the trigger control unit 1066, when the power converter 106 outputs an overvoltage at time tov, the trigger control unit 1066 will maintain the original high level of the trigger control signal Sen to maintain Enabling the drive unit 1067 to drive the full-bridge switching circuit 1061; until after a delay time Ty1 (that is, the delay time Ty1=t23-tov), the trigger control unit 1066 is in the pulse width modulation signal When the working cycle of Spwm1 and Spwm2 ends (that is, when the short-circuit prevention time occurs), the trigger control unit 1066 generates the trigger control signal Sen of low level to disable the driving unit 1067 for switching the full bridge The drive of circuit 1061. Conversely, when the power converter 106 outputs the working voltage at time tnv, the trigger control unit 1066 will maintain the trigger control signal Sen at the original low level, so as to keep the driving unit 1067 disabled for switching the full bridge The driving of the circuit 1061; until after a delay time Ty2 (that is, the delay time Ty2=t25-tnv), the trigger control unit 1066 is at the end of the duty cycle of the pulse width modulation signal Spwm1, Spwm2 (that is, When the short-circuit prevention time occurs), the trigger control unit 1066 generates the high-level trigger control signal Sen to enable the driving unit 1067 to drive the full-bridge switching circuit 1061 .

Please refer to FIG. 7 which is a flow chart of the control method of the power converter of the charging device according to the present invention. The control method includes the following steps: providing a full bridge switching circuit, a resonant circuit and a transformer (S100). Wherein, the full-bridge switching circuit includes two bridge arms composed of four power switching elements to switch the DC input voltage into a square wave voltage. The resonant circuit is electrically connected to the full-bridge switching circuit to receive and convert the square wave voltage into a resonant voltage. The transformer has an input side and an output side, and the input side is electrically connected to the resonant circuit to receive the resonant voltage. An overvoltage protection unit is provided to detect an output voltage of the power converter and generate an output voltage signal (S200). Wherein, the overvoltage protection unit is electrically connected to the output side of the transformer. A PWM control unit is provided to generate a PWM signal (S300). A trigger control unit is provided to receive the output voltage signal and the pulse width modulation signal, and generate a trigger control signal (S400). Wherein, the trigger control unit includes a leading-edge triggered D-type flip-flop and a NOR gate. The positive-edge triggered D-type flip-flop includes a data input terminal, a clock input terminal and at least one output terminal. The NOR gate includes two input terminals and an output terminal, and the output terminal is connected to the clock input terminal of the positive-edge triggered D-type flip-flop. The data input end receives the output voltage signal generated by the overvoltage protection unit; the two input ends of the NOR gate respectively receive the pulse width modulation signal.

A driving unit is provided to receive the trigger control signal and the pulse width modulation signal to drive the full-bridge switching circuit on and off (S500). When the overvoltage protection unit detects that the output voltage is an overvoltage, the output voltage signal generated by the overvoltage protection unit controls the trigger control unit, so that the trigger control unit ends the duty cycle of the pulse width modulation signal , outputting the trigger control signal to disable (disable) the drive unit from driving the full-bridge switching circuit (S600). Wherein when the overvoltage protection unit detects that the output voltage is the overvoltage output, the output voltage signal generated by the overvoltage protection unit is an overvoltage signal to control the trigger control unit to output a low level trigger control signal to disable the drive unit from driving the full-bridge switching circuit. Wherein, the overvoltage protection unit can transmit the output voltage signal to the trigger control unit through an optical coupling unit. When the power converter is an over-voltage output and the pulse width modulation signals are all at low level, the positive-edge triggered D-type flip-flop outputs the trigger control signal at low level to disable the drive unit for all Bridge switching circuit driver. In addition, the two bridge arms of the full-bridge switching circuit are complementary turned on and off at intervals of a short-circuit prevention time (dead time). Therefore, when the power converter is an overvoltage output and the short-circuit prevention time occurs, the positive The edge-triggered D-type flip-flop outputs the low-level trigger control signal to disable the drive unit from driving the full-bridge switching circuit.

When the overvoltage output condition is eliminated, when the overvoltage protection unit detects that the output voltage is a working voltage, the output voltage signal generated by the overvoltage protection unit controls the trigger control unit, so that the trigger control unit is at the pulse width When the duty cycle of the modulation signal ends, the trigger control signal is output to enable the drive unit to drive the full-bridge switching circuit. When the power converter is the working voltage output and the pulse width modulation signals are all at low level, the positive-edge triggered D-type flip-flop outputs the high-level trigger control signal, so as to enable the drive unit to control the full bridge drive of switching circuits. That is, when the power converter is the working voltage output and the short-circuit prevention time occurs, the positive-edge triggered D-type flip-flop outputs the high-level trigger control signal to enable the drive unit to switch the full-bridge circuit drive.

However, the above description is only a detailed description and drawings of preferred embodiments of the present invention, but the features of the present invention are not limited thereto, and are not intended to limit the present invention. The scope of the patent claims is the criterion, and all embodiments that meet the spirit of the scope of the patent claims of the present invention and its similar changes should be included in the scope of the present invention, and any skilled person in the field of the present invention can easily All conceivable changes or modifications can be covered by the scope of the patent claims of this case.

Claims (16)

1. A power converter comprising: A full-bridge switching circuit, which converts a DC input voltage into a square wave voltage; A resonant circuit, electrically connected to the full bridge switching circuit, receives the square wave voltage and converts it into a resonant voltage; A transformer has an input side and an output side, the input side is electrically connected to the resonant circuit, and receives the resonant voltage; An overvoltage protection unit, electrically connected to the output side, detects an output voltage of the output side, and generates an output voltage signal; a pulse width modulation control unit for generating a pulse width modulation signal; a trigger control unit, receiving the output voltage signal and the pulse width modulation signal, and generating a trigger control signal; and a driving unit, receiving the trigger control signal and the pulse width modulation signal to drive the full-bridge switching circuit to be turned on and off; Wherein, when the overvoltage protection unit detects that the output voltage is an overvoltage, the trigger control unit outputs the trigger control signal at a low level when the duty cycle of the pulse width modulation signal ends to disable the Drive unit. 2. The power converter as claimed in claim 1, wherein when the overvoltage protection unit detects that the output voltage is a working voltage, the trigger control unit outputs a high voltage when the duty cycle of the pulse width modulation signal ends. level of the trigger control signal to enable the driving unit. 3. The power converter as claimed in claim 2, wherein the trigger control unit comprises: A positive-edge triggered D-type flip-flop, including a data input terminal, a clock input terminal and at least one output terminal; and A NOR gate, including two input terminals and an output terminal, and the output terminal is connected to the clock input terminal; Wherein, the data input end receives the output voltage signal; the two input ends of the NOR gate respectively receive the pulse width modulation signal. 4. The power converter as claimed in claim 3, wherein when the output voltage is the overvoltage and the PWM signals are all at low level, the positive edge triggered D-type flip-flop outputs the low level Trigger the control signal to disable the drive unit. 5. The power converter as claimed in claim 3, wherein when the output voltage is the operating voltage and the pulse width modulation signals are both at low level, the positive edge triggered D-type flip-flop outputs the high level A control signal is triggered to enable the drive unit. 6. The power converter as claimed in claim 1, wherein the overvoltage protection unit transmits the output voltage signal to the trigger control unit through an optical coupling unit. 7. The power converter as claimed in claim 3, wherein the full-bridge switching circuit comprises two bridge arms composed of four power switching elements; the two bridge arms are complementarily turned on and off at intervals of a short-circuit prevention time; when the When the output voltage is the overvoltage and the short-circuit prevention time occurs, the positive-edge triggered D-type flip-flop outputs the trigger control signal of low level to disable the driving unit. 8. The power converter as claimed in claim 3, wherein the full-bridge switching circuit comprises two bridge arms composed of four power switching elements; the two bridge arms are complementarily turned on and off at intervals of a short-circuit prevention time; when the When the output voltage is the working voltage and the short-circuit prevention time occurs, the positive-edge triggered D-type flip-flop outputs the high-level trigger control signal to enable the driving unit. 9. A control method for a power converter, the control method comprising the following steps: (a) providing a full bridge switching circuit, a resonant circuit and a transformer; (b) providing an overvoltage protection unit, detecting an output voltage of the power converter, and generating an output voltage signal; (c) providing a pulse width modulation control unit to generate a pulse width modulation signal; (d) providing a trigger control unit, receiving the output voltage signal and the pulse width modulation signal, and generating a trigger control signal; (e) providing a driving unit, receiving the trigger control signal and the pulse width modulation signal, and driving the full-bridge switching circuit to be turned on and off; and (f) When the overvoltage protection unit detects that the output voltage is an overvoltage, the trigger control unit outputs the trigger control signal at a low level when the duty cycle of the pulse width modulation signal ends to disable the drive unit. 10. The power converter control method as claimed in claim 9, wherein after the step (f), it also includes: (g) When the overvoltage protection unit detects that the output voltage is a working voltage, the trigger control unit outputs the high level trigger control signal at the end of the duty cycle of the pulse width modulation signal to enable the Drive unit. 11. The power converter control method as claimed in claim 10, wherein the trigger control unit comprises: A positive-edge triggered D-type flip-flop, including a data input terminal, a clock input terminal and at least one output terminal; and A NOR gate, including two input terminals and an output terminal, and the output terminal is connected to the clock input terminal; Wherein, the data input end receives the output voltage signal; the two input ends of the NOR gate respectively receive the pulse width modulation signal. 12. The control method of the power converter as claimed in claim 11, wherein when the output voltage is the overvoltage and the pulse width modulation signals are all at low level, the positive-edge triggered D-type flip-flop outputs a low level The trigger control signal to disable the drive unit. 13. The power converter control method as claimed in claim 11, wherein when the output voltage is the operating voltage and the pulse width modulation signals are all at low level, the positive-edge triggered D-type flip-flop outputs a high level The trigger control signal to enable the drive unit. 14. The power converter control method as claimed in claim 9, wherein the overvoltage protection unit transmits the output voltage signal to the trigger control unit through an optical coupling unit. 15. The power converter control method as claimed in claim 11, wherein the full-bridge switching circuit comprises two bridge arms composed of four power switching elements; the two bridge arms are complementarily turned on and off at intervals of a short-circuit prevention time; When the output voltage is the overvoltage and the short-circuit prevention time occurs, the positive-edge triggered D-type flip-flop outputs the trigger control signal at a low level to disable the driving unit. 16. The power converter control method as claimed in claim 11, wherein the full-bridge switching circuit comprises two bridge arms composed of four power switching elements; the two bridge arms are complementarily turned on and off at intervals of a short-circuit prevention time; When the output voltage is the working voltage and the short-circuit prevention time occurs, the positive-edge triggered D-type flip-flop outputs the high-level trigger control signal to enable the driving unit.

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