CN103426854A - 一种基于柔性基板封装的散热结构及其制作工艺 - Google Patents
一种基于柔性基板封装的散热结构及其制作工艺 Download PDFInfo
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- CN103426854A CN103426854A CN201210163031XA CN201210163031A CN103426854A CN 103426854 A CN103426854 A CN 103426854A CN 201210163031X A CN201210163031X A CN 201210163031XA CN 201210163031 A CN201210163031 A CN 201210163031A CN 103426854 A CN103426854 A CN 103426854A
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- board
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210163031XA CN103426854A (zh) | 2012-05-23 | 2012-05-23 | 一种基于柔性基板封装的散热结构及其制作工艺 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210163031XA CN103426854A (zh) | 2012-05-23 | 2012-05-23 | 一种基于柔性基板封装的散热结构及其制作工艺 |
Publications (1)
Publication Number | Publication Date |
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CN103426854A true CN103426854A (zh) | 2013-12-04 |
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CN201210163031XA Pending CN103426854A (zh) | 2012-05-23 | 2012-05-23 | 一种基于柔性基板封装的散热结构及其制作工艺 |
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CN (1) | CN103426854A (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111968944A (zh) * | 2020-08-24 | 2020-11-20 | 浙江集迈科微电子有限公司 | 一种射频模组超薄堆叠工艺 |
CN119252809A (zh) * | 2024-09-29 | 2025-01-03 | 南通大学 | 一种基于柔性基板的新型三维封装结构及芯片散热方法 |
CN119480821A (zh) * | 2025-01-14 | 2025-02-18 | 上海安理创科技有限公司 | 一种多芯片封装结构及封装工艺 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5740527A (en) * | 1994-11-24 | 1998-04-14 | Nec Corporation | Transceiver |
US5926369A (en) * | 1998-01-22 | 1999-07-20 | International Business Machines Corporation | Vertically integrated multi-chip circuit package with heat-sink support |
US20010006252A1 (en) * | 1996-12-13 | 2001-07-05 | Young Kim | Stacked microelectronic assembly and method therefor |
CN1756474A (zh) * | 2004-09-28 | 2006-04-05 | 夏普株式会社 | 射频模块及其制造方法 |
KR20060031343A (ko) * | 2004-10-08 | 2006-04-12 | 주식회사 넥트론 | 플렉시블 집적회로 패키지 |
US20080218974A1 (en) * | 2007-03-06 | 2008-09-11 | Gerald Keith Bartley | Method and Structure for Connecting, Stacking, and Cooling Chips on a Flexible Carrier |
-
2012
- 2012-05-23 CN CN201210163031XA patent/CN103426854A/zh active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5740527A (en) * | 1994-11-24 | 1998-04-14 | Nec Corporation | Transceiver |
US20010006252A1 (en) * | 1996-12-13 | 2001-07-05 | Young Kim | Stacked microelectronic assembly and method therefor |
US5926369A (en) * | 1998-01-22 | 1999-07-20 | International Business Machines Corporation | Vertically integrated multi-chip circuit package with heat-sink support |
CN1756474A (zh) * | 2004-09-28 | 2006-04-05 | 夏普株式会社 | 射频模块及其制造方法 |
KR20060031343A (ko) * | 2004-10-08 | 2006-04-12 | 주식회사 넥트론 | 플렉시블 집적회로 패키지 |
US20080218974A1 (en) * | 2007-03-06 | 2008-09-11 | Gerald Keith Bartley | Method and Structure for Connecting, Stacking, and Cooling Chips on a Flexible Carrier |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111968944A (zh) * | 2020-08-24 | 2020-11-20 | 浙江集迈科微电子有限公司 | 一种射频模组超薄堆叠工艺 |
CN119252809A (zh) * | 2024-09-29 | 2025-01-03 | 南通大学 | 一种基于柔性基板的新型三维封装结构及芯片散热方法 |
CN119480821A (zh) * | 2025-01-14 | 2025-02-18 | 上海安理创科技有限公司 | 一种多芯片封装结构及封装工艺 |
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Owner name: NATIONAL CENTER FOR ADVANCED PACKAGING Free format text: FORMER OWNER: INST OF MICROELECTRONICS, C. A. S Effective date: 20150228 |
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Free format text: CORRECT: ADDRESS; FROM: 100029 CHAOYANG, BEIJING TO: 214135 WUXI, JIANGSU PROVINCE |
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Effective date of registration: 20150228 Address after: Taihu international science and Technology Park in Jiangsu province Wuxi City Linghu road 214135 Wuxi national hi tech Industrial Development Zone No. 200 Chinese Sensor Network International Innovation Park building D1 Applicant after: National Center for Advanced Packaging Co.,Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Applicant before: Institute of Microelectronics of the Chinese Academy of Sciences |
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C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20131204 |