CN103426753B - The preparation method of source-drain area and MOS device - Google Patents
The preparation method of source-drain area and MOS device Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 54
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 41
- 239000010703 silicon Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 33
- 239000007943 implant Substances 0.000 claims abstract description 18
- 230000008021 deposition Effects 0.000 claims abstract description 10
- 150000002500 ions Chemical class 0.000 claims abstract description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 8
- 238000004904 shortening Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 14
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- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
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- 238000001020 plasma etching Methods 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
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- 238000006243 chemical reaction Methods 0.000 description 2
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- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
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- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
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- 239000000377 silicon dioxide Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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Abstract
The invention discloses the preparation method of a kind of source-drain area and the MOS device manufactured according to the method, the method includes: the structure before source-drain area is prepared in offer, carries out back carving to form groove being formed on the substrate of source-drain area；Silicon oxide layer is formed at body structure surface；Deposition silicon seed layer；Deposition mask layer, and utilize mask layer to fill up groove；Part mask layer in the mask layer being in outside groove and groove is removed；To be in mask layer in groove for stopping, remove silicon seed layer and silicon oxide layer, expose the lightly doped drain being in below side wall；Remove remaining mask layer；Carry out the epitaxial growth of silicon in the trench, and groove is filled up and the lightly doped drain being in below side wall is buried, form pre-implant district；Pre-implant district is carried out ion implanting and forms source-drain area。The MOS device that the present invention manufactures, inhibits the shortening along with grid length because of the partial occlusion of silicon oxide layer between source-drain area and electric leakage that the short-channel effect that produces causes, and then reduces the power consumption of MOS device。
Description
Technical field
The present invention relates to semiconductor fabrication, particularly to a kind of MOS(MetallicOxideSemiconductor, metal-oxide semiconductor (MOS)) preparation method in device source drain region and the MOS device that manufactures according to the method。
Background technology
The conventional manufacturing process of existing a kind of MOS device contains following steps。
Thering is provided substrate 1, such as silicon substrate, on described substrate 1, formation shallow trench isolates (STI) 2, as shown in Figure 1。To substrate 1 carrying out ion implanting to form N trap and/or p-well, and carry out threshold voltage adjustment。
Forming gate insulation layer 3 and grid 4 on described substrate 1, wherein gate insulation layer 3 is generally silicon oxide, and grid 4 is such as polysilicon gate or metal gates, as shown in Figure 2。
The substrate 1 of grid 4 both sides is carried out ion implanting formation lightly doped drain (LDD, LightlyDopedDrain) 5, as shown in Figure 3。Lightly-doped drain zone structure, is MOSFET(MetallicOxideSemiconductorFieldEffectTransistor, mos field effect transistor) in order to weaken drain region electric field, to improve a kind of structure that thermoelectron degradation effect is taked。Namely being be arranged around a low-doped drain region near what drain in conducting channel, allow this low-doped drain region be also subjected to portion voltage, this structure can prevent thermoelectron degradation effect。
Side wall (spacer) 6 is formed, as shown in Figure 4 in described grid 4 both sides。The material of side wall 6 can be silicon oxide, and it is mainly through silicon oxide layer deposited and carries out back carving formation。In prior art, side wall 6 may be used without other structures, and such as isolation side walls (offsetspacer)+master wall (mainspacer) structure, wherein isolation side walls is generally adopted silicon nitride material, and master wall adopts silica material。
After forming side wall 6, the substrate 1 of grid 4 both sides is carried out ion implanting formation source-drain area 7, as shown in Figure 5。
Along with the shortening of MOS device grid length, the MOS device that said process is made in manufacture of semiconductor technique, its short-channel effect constantly strengthens, and leaks electricity increasing, result in increasing power consumption accordingly, and then shortens the stand-by time of produced electronic product。
Summary of the invention
In view of this, the present invention provides the preparation method of a kind of source-drain area and the MOS device of foundation the method manufacture, produce, along with the shortening of grid length, the electric leakage that short-channel effect causes to reduce, and then reduce the power consumption of made MOS device, extend the stand-by time of produced electronic product。
The technical scheme is that and be achieved in that:
A kind of preparation method of source-drain area, including:
The structure before source-drain area is prepared in offer, carries out back carving to form groove being formed on the substrate of source-drain area；
Silicon oxide layer is formed at the body structure surface including described grooved inner surface；
Described silicon oxide layer deposits silicon seed layer；
Deposition mask layer in described silicon seed layer, and utilize described mask layer to fill up described groove；
Return and carve described mask layer, the mask layer being in outside described groove and the part mask layer being in described groove are removed；
To be in mask layer in groove for stopping, remove the silicon seed layer and the silicon oxide layer that are exposed at body structure surface, until the lightly doped drain being in below side wall is exposed；
Remove remaining mask layer in described groove；
Silicon seed layer in the trench carries out the epitaxial growth of silicon, until being filled up by groove and being buried the lightly doped drain being in below side wall, forms pre-implant district；
Described pre-implant district is carried out ion implanting and forms source-drain area。
Further, described gash depth is 800 ~ 2000 angstroms。
Further, described silicon oxide layer thickness is 50 ~ 300 angstroms。
Further, described silicon seed layer thickness is 50 ~ 100 angstroms, adopts ald ALD method deposition。
Further, described mask layer is silicon nitride, and thickness is 500 ~ 3000 angstroms。
A kind of MOS device, including:
Substrate；
It is formed at the grid on described substrate；
It is formed at the side wall of described grid both sides；
It is arranged in the lightly doped drain of described side wall base substrate；
It is arranged in the source-drain area of grid both sides substrate；
Wherein, described source-drain area connects with described lightly doped drain；
It is additionally provided with silicon oxide layer between described source-drain area and substrate。
Can be seen that from such scheme, in the preparation method of source-drain area of the present invention and MOS device, it is provided with silicon oxide layer between the source-drain area and substrate of grid both sides, and source-drain area and lightly doped drain connect, the isolation of silicon oxide layer is not had between the lightly doped drain and substrate of gate bottom, so between the substrate at grid two ends, because the existence of silicon oxide layer, make to be partially isolate between source-drain area and substrate, the lightly doped drain only passing through to connect is connected with substrate, so just inhibit the electric leakage that the short-channel effect produced along with the shortening of grid length between source-drain area causes between source-drain area below grid because of the partial occlusion of silicon oxide layer, and then reduce the power consumption of MOS device, extend the stand-by time of the electronic product manufactured by MOS device adopting the present invention。
Accompanying drawing explanation
Fig. 1 is that prior art manufactures the device architecture schematic diagram forming shallow trench isolation in MOS process on substrate；
Fig. 2 is the device architecture schematic diagram that prior art manufactures after forming grid in MOS process in structure shown in Fig. 1；
Fig. 3 is the device architecture schematic diagram that prior art manufactures after forming lightly doped drain in MOS process in structure shown in Fig. 2；
Fig. 4 is the device architecture schematic diagram that prior art manufactures after forming side wall in MOS process in structure shown in Fig. 3；
Fig. 5 is the device architecture schematic diagram that prior art manufactures after forming source-drain area in MOS process in structure shown in Fig. 4；
Fig. 6 is the preparation method flow chart of source-drain area of the present invention；
Fig. 7 is the device architecture schematic diagram after the present invention forms groove in structure shown in Fig. 4；
Fig. 8 is the device architecture schematic diagram after forming silicon oxide layer in structure shown in Fig. 7 of the present invention；
Fig. 9 is the device architecture schematic diagram after forming silicon seed layer in structure shown in Fig. 8 of the present invention；
Figure 10 is the device architecture schematic diagram after forming mask layer in structure shown in Fig. 9 of the present invention；
Figure 11 is the device architecture schematic diagram after structure shown in Figure 10 of the present invention removes part mask layer；
Figure 12 is the device architecture schematic diagram after structure shown in Figure 11 of the present invention removes silicon seed layer and silicon oxide layer；
Figure 13 is the device architecture schematic diagram after structure shown in Figure 12 of the present invention removes residue mask layer；
Figure 14 is the device architecture schematic diagram after structure shown in Figure 13 of the present invention forms pre-implant district；
Figure 15 is the device architecture schematic diagram after structure shown in Figure 14 of the present invention forms source-drain area。
Detailed description of the invention
For making the purpose of the present invention, technical scheme and advantage clearly understand, develop simultaneously embodiment referring to accompanying drawing, the present invention is described in further detail。
As shown in Figure 6, the preparation method of the source-drain area of the present invention, comprise the following steps:
Step 1: the structure before source-drain area is prepared in offer, carries out back on the substrate of source-drain area carving to form groove being formed；
Step 2: form silicon oxide layer at the body structure surface including described grooved inner surface；
Step 3: deposit silicon seed layer on described silicon oxide layer；
Step 4: deposition mask layer in described silicon seed layer, and utilize described mask layer to fill up described groove；
Step 5: return and carve described mask layer, removes the mask layer being in outside described groove and the part mask layer being in described groove；
Step 6: to be in mask layer in groove for stopping, remove the silicon seed layer and the silicon oxide layer that are exposed at body structure surface, until the lightly doped drain being in below side wall is exposed；
Step 7: remove remaining mask layer in described groove；
Step 8: carry out the epitaxial growth of silicon in silicon seed layer in the trench, until being filled up by groove and being buried the lightly doped drain being in below side wall, forms pre-implant district；
Step 9: described pre-implant district is carried out ion implanting and forms source-drain area。
Below in conjunction with Fig. 7 to Figure 15, above steps is specifically described。
Step 1: the structure before source-drain area is prepared in offer, carries out back carving to form groove 8, as shown in Figure 7 on the substrate 1 will be formed source-drain area 7。
Wherein, preparing the structure before source-drain area shown in Figure 4, this structure includes the substrate 1 isolating 2 already formed with shallow trench, such as silicon substrate, the material such as silicon oxide of shallow trench isolation 2；Already formed with gate insulation layer 3 and grid 4 on substrate 1, the material of gate insulation layer 3 such as silicon oxide, grid 4 can be polysilicon gate or metal gates；The substrate 1 of grid 4 both sides is formed with lightly doped drain 5；It is formed with side wall 6 in the both sides of grid 4。About the structure before source-drain area, those skilled in the art can adopt existing conventional means to be prepared, and repeats no more herein。
The substrate 1 will be formed source-drain area 7 carries out back carve and form groove 8, be carry out on the substrate already formed with lightly doped drain 5。As shown in Figure 7; because being formed with side wall 6 in the both sides of grid 4; therefore part lightly doped drain 5 is in side wall less than 6, so when substrate 1 carries out back carving formation groove 8, the lightly doped drain 5 being in side wall less than 6 is subjected to the protection of side wall 6 without being etched away。
In this step, carrying out back substrate 1 carving and form groove 8 method that can adopt dry etching, such as RIE(ReactiveIonEtching, reactive ion etching) method carries out, and etching gas can adopt the gas rich in halogen especially fluorine element；Returning of substrate 1 is carved the method that may be used without wet etching, as passed through that existing method has anisotropic KOH(potassium hydroxide) solution and/or TMAH(Tetramethylammonium hydroxide) solution performs etching, and the degree of depth of described groove 8 is 800 ~ 2000 angstroms。
Step 2: form silicon oxide layer 9 on the total surface including groove 8 inner surface, as shown in Figure 8。
In this step 2, the inner surface of groove 8 includes bottom land and the sidewall of groove 8, silicon oxide layer 9 is formed and existing conventional method can be adopted to be formed, as at 700 ~ 1100 DEG C with the low thermal oxidation (LowTemperatureOxidation) of dry method or wet oxidation, or the method such as high-temperature thermal oxidation (HighTemperatureOxidation)。The process forming silicon oxide layer 9 carries out over the entire structure, so except the inner surface of groove 8 is oxidized, and the outer surface of the remainder of structure such as grid 4 also oxidized formation silicon oxide layer 9 simultaneously。After step 2, all oxidized silicon of the outer surface of total is covered。The thickness of silicon oxide layer 9 can be 50 ~ 300 angstroms。
Step 3: deposit silicon seed layer 10 on silicon oxide layer 9。
In this step 3, as it is shown in figure 9, silicon seed layer 10 is because being be deposited on silicon oxide layer 9, so the silicon seed layer 10 after deposition is just covered in total surface。The deposition of silicon seed layer 10 can adopt conventional ALD(AtomicLayerDeposition, ald) or CVD(ChemicalVaporDeposition, chemical vapour deposition (CVD)) method carries out, decompose using silane or silicon chloride and hydrogen are as reacting gas, ALD technique has the Step Coverage ability being better than other techniques, and silicon seed layer 10 thickness is 50 ~ 100 angstroms。
Step 4: deposition mask layer 11 in silicon seed layer 10, and utilize mask layer 11 to fill up groove 8, as shown in Figure 10。
In this step 4, mask layer 11 is silicon nitride material, existing common process can be adopted, such as LPCVD(LowPressureChemicalVaporDeposition, low-pressure chemical vapor deposition) method is at 700 ~ 1000 DEG C, being deposited using silicon chloride and ammonia as reacting gas, the thickness of mask layer 11 is 500 ~ 3000 angstroms。Because mask layer 11 is to be deposited in silicon seed layer 10, so as shown in Figure 10, mask layer 11 has covered the surface of total。
Step 5: return and carve described mask layer 11, removes the mask layer 11 being in outside groove 8 and the part mask layer 11 being in groove 8, as shown in figure 11。
In this step 5, as shown in figure 11, after later step removes the silicon seed layer 10 and the silicon oxide layer 9 that are exposed at body structure surface, the lightly doped drain 5 being in side wall less than 6 can be exposed, mask layer 11 in groove 8 is carried out part removal by this step 5, removes the lower end lower than side wall 6 of mask layer 11 height after part mask layer 11。
The etching of mask layer 11 can adopt the method for wet etching, utilizes hot phosphoric acid to carry out, needs the thickness according to mask layer 11, calculate etch period in etching process, to avoid the mask layer 11 in groove 8 by overetch；Mask layer 11 may be used without reaction rate to carry out back carving higher than the reactive ion etching method of particle bombardment speed, to ensure isotropic etching speed, thus realizing the above results。
Step 6: to be in mask layer 11 in groove 8 for stopping, remove the silicon seed layer 10 and the silicon oxide layer 9 that are exposed at body structure surface, until the lightly doped drain 5 being in side wall less than 6 is exposed, as shown in figure 12。
In this step 6, the method that the removal of silicon seed layer 10 and silicon oxide layer 9 can be adopted wet etching, dilute hydrofluoric acid solution is utilized to carry out, may be used without reaction rate to carry out back silicon seed layer 10 and silicon oxide layer 9 carving to ensure isotropic etching speed higher than the reactive ion etching of particle bombardment speed, thus realizing the above results。
In this step 6, when removing silicon seed layer 10 and silicon oxide layer 9, it is necessary to note the overetch preventing side wall 6 and silicon oxide layer 9 around grid 4, to protect grid 4 not to be destroyed。
Step 7: remove remaining mask layer 11 in groove 8, as shown in figure 13。
In this step 7, adopt wet etch process, utilize hot phosphoric acid to remove remaining mask layer 11 in groove 8。When performing this step 7, side wall 6 and silicon oxide layer 9 around grid 4 can protect grid 4 not to be destroyed。
Step 8: carry out the epitaxial growth of silicon in the silicon seed layer 10 in groove 8, until being filled up by groove 8 and being buried the lightly doped drain 5 being in side wall less than 6, forms pre-implant district 12, as shown in figure 14。
In this step 8, pre-implant district 12 adopts silicon epitaxy commonly used in the art or silicon germanium epitaxial method to grow, it is preferable that implements such as selective epitaxial growth (SEG) and generates unadulterated silicon epitaxy。Formed behind pre-implant district 12 through this step, silicon oxide layer 9 in primitive groove groove 8 is just located between pre-implant district 12 and substrate 1, and pre-implant district 12 and lightly doped drain 5 connect, bottom grid 4, between lightly doped drain 5 and substrate 1, there is no the isolation of silicon oxide layer 9。So between the substrate 1 at grid 4 two ends, because existence of silicon oxide layer 9 so that be partially isolate between pre-implant district 12 and substrate 1, the lightly doped drain 5 only passing through to connect is connected with substrate 1。
Step 9: pre-implant district 12 is carried out ion implanting, to form source-drain area 7, as shown in figure 15。
In this step 9, the ion implanting carried out, the conventional ion method for implanting of existing formation source-drain area 7 can be adopted。The source-drain area 7 formed is positioned at pre-implant district 12, in other words, the source-drain area 7 formed substitutes original pre-implant district 12, therefore as shown in figure 15, between the source-drain area 7 and substrate 1 of grid 4 both sides, it is folded with the silicon oxide layer 9 being previously formed, and source-drain area 7 and lightly doped drain 5 connect, bottom grid 4, between lightly doped drain 5 and substrate 1, there is no the isolation of silicon oxide layer 9。So between the substrate 1 at grid 4 two ends, because existence of silicon oxide layer 9 so that be partially isolate between source-drain area 7 and substrate 1, the lightly doped drain 5 only passing through to connect is connected with substrate 1。Owing to silicon oxide layer 9 belongs to insulant, so in substrate 1, just inhibit and produce, along with the shortening of grid length, the electric leakage that short-channel effect causes because of the partial occlusion of silicon oxide layer 9 between source-drain electrode between the source-drain area 7 of grid less than 4, and then reduce the power consumption of MOS device, extend the stand-by time adopting the electronic product manufactured by the inventive method。
The MOS device structure formed through above-mentioned steps 1 to step 9 as shown in figure 15, comprising: substrate 1；It is formed at the grid 4 on substrate 1；It is formed at the side wall 6 of grid 4 both sides；It is arranged in the lightly doped drain 5 of side wall 6 base substrate 1；It is arranged in the source-drain area 7 of grid 4 both sides substrate 1；Wherein, source-drain area 7 connects with lightly doped drain 5；Silicon oxide layer 9 it is additionally provided with between source-drain area 7 and substrate 1。This silicon oxide layer 9 is completely not completely isolated to carrying out between source-drain area 7 and substrate 1, but be partially isolate, silicon oxide layer 9 is provided with opening in the joint of source-drain area 7 with lightly doped drain 5 so that it is the conducting channel between source-drain area 7 that the lightly doped drain 5 that source-drain area 7 can pass through to connect with it is in the substrate 1 on the downside of grid 4 with the substrate 1(being on the downside of grid 4) connect。In this structure, between lightly doped drain 5 and substrate 1, do not set silicon oxide layer 9。Due to, between the substrate 1 at grid 4 two ends, because the existence of silicon oxide layer 9, make to be partially isolate between source-drain area 7 and substrate 1, the lightly doped drain 5 only passing through to connect is connected with substrate 1, therefore in substrate 1, just inhibit the electric leakage that the short-channel effect produced between source-drain area 7 causes along with the shortening of grid length because of the partial occlusion of silicon oxide layer 9 between the source-drain area 7 of grid less than 4, and then reduce the power consumption of MOS device, extend the stand-by time of the electronic product manufactured by MOS device adopting the present invention。
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all within the spirit and principles in the present invention, any amendment of making, equivalent replacement, improvement etc., should be included within the scope of protection of the invention。
Claims (4)
1. a preparation method for source-drain area, including:
The structure before source-drain area is prepared in offer, carries out back carving to form groove being formed on the substrate of source-drain area；
Silicon oxide layer is formed at the body structure surface including described grooved inner surface；
Described silicon oxide layer deposits silicon seed layer；
Deposition mask layer in described silicon seed layer, and utilize described mask layer to fill up described groove；
Return and carve described mask layer, the mask layer being in outside described groove and the part mask layer being in described groove are removed；
To be in mask layer in groove for stopping, remove the silicon seed layer and the silicon oxide layer that are exposed at body structure surface, until the lightly doped drain being in below side wall is exposed；
Remove remaining mask layer in described groove；
Silicon seed layer in the trench carries out the epitaxial growth of silicon, until being filled up by groove and being buried the lightly doped drain being in below side wall, forms pre-implant district；
Described pre-implant district is carried out ion implanting and forms source-drain area；
Wherein, described mask layer is silicon nitride, and thickness is 500～3000 angstroms。
2. the preparation method of source-drain area according to claim 1, it is characterised in that: described gash depth is 800～2000 angstroms。
3. the preparation method of source-drain area according to claim 1, it is characterised in that: described silicon oxide layer thickness is 50～300 angstroms。
4. the preparation method of source-drain area according to claim 1, it is characterised in that: described silicon seed layer thickness is 50～100 angstroms, adopts ald ALD method deposition。
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| CN105590840A (en) * | 2014-10-21 | 2016-05-18 | 上海华力微电子有限公司 | Method for preparing embedded SiGe |
| CN105529247A (en) * | 2014-10-21 | 2016-04-27 | 上海华力微电子有限公司 | Preparation method of embedded silicon-germanium |
| CN104392922B (en) * | 2014-11-26 | 2018-06-26 | 上海华力微电子有限公司 | The preparation method of embedded silicon carbide |
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| CN102339859A (en) * | 2010-07-16 | 2012-02-01 | 中国科学院微电子研究所 | Mos transistor and forming method thereof |
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