CN103413795B - The encapsulating structure of semiconductor device and the packaging technology flow process of semiconductor device - Google Patents

Abstract

The invention discloses a packaging structure of a semiconductor device and a packaging process flow of the semiconductor device, wherein the packaging structure includes: a base, the base has a plurality of conductive through holes, and the plurality of conductive through holes are electrically isolated from each other; at least one semiconductor device, Located on one side of the base structure and electrically connected to the conductive via. The present invention can simplify the packaging process of the semiconductor device by making the plurality of conductive vias in the packaging structure of the semiconductor device be located in the substrate, improve the flexibility of selecting the packaging process, and reduce the overall area of the packaged semiconductor device. In addition, , the semiconductor device can be electrically connected to the outside world through the conductive via hole.

Description

Packaging structure of semiconductor devices and packaging process flow of semiconductor devices

technical field

The present invention relates to the semiconductor field, and in particular, relates to a packaging structure of a semiconductor device and a packaging process flow of the semiconductor device.

Background technique

Piezoelectric film bulk acoustic resonators (FBARs) can replace surface acoustic wave devices and quartz crystal resonators in radio frequency communications and high-speed serial data applications. FBAR-based filters and/or duplexers can provide superior filtering characteristics for RF front-end modules, for example, can provide low insertion loss, steep transition band, large power capacity, strong anti-static discharge (ESD) capability, etc. The advantages of high-frequency FBARs with ultra-low frequency temperature drift are low phase noise, low power consumption, and large bandwidth modulation range. In addition, FBARs can be fabricated using complementary metal-oxide-semiconductor (CMOS)-compatible process technologies. Moreover, in the case of the integration of FBAR and CMOS circuits, the degree of integration of the circuits will be improved, the chip size will be reduced, and the manufacturing cost will be reduced.

FBAR is usually a three-layer structure in which a bottom electrode, a piezoelectric layer and an upper electrode are stacked and grown on a silicon base wafer. When a voltage signal of a certain frequency is applied between the upper and bottom electrodes, due to the inverse piezoelectric effect of the piezoelectric material, sound waves are generated between the two electrodes, and the sound waves are reflected back and forth in the FBAR and resonate at a certain frequency. When the FBAR device works, it is necessary to lead the electrical signal out of the cavity and form an interconnection with other circuit structures. Therefore, conductive interconnection is a basic requirement for FBAR device packaging.

The packaging structure of the sealed cavity required for the operation of FBAR devices is generally realized through wafer bonding. Common wafer bonding includes silicon-glass anodic bonding, silicon-silicon eutectic bonding, intermediary bonding techniques, etc. The dielectric materials bonded by the intermediate dielectric layer are generally divided into conductive media and non-conductive media. Conductive media such as gold, copper, aluminum, etc., non-conductive dielectric layers such as silicon dioxide, epoxy resin, etc.

As shown in Figure 1, it is the packaging structure of a common FBAR device. The main steps of packaging an FBAR device include:

fabricating cavities 11a on the base wafer;

Making the bottom electrode 11b, the piezoelectric layer 11c and the upper electrode 11d of the FBAR;

Fabricating a cavity 12a on the sealed wafer 12;

A sealed cavity is formed by wafer bonding;

By sealing the vias 13 on the wafer 12, the electrodes of the FBAR are connected to the outside world.

If a completely sealed cavity is to be formed, sealing bonding should also be performed around the conductive via 13 (the area 14 shown in FIG. 1 ). Such a packaging structure will occupy too much area, and this packaging method needs to form a sealed cavity and realize the connection of conductive vias at the same time, so the process is difficult to realize.

Aiming at the problems in the related art that the semiconductor device occupies a large area and the process of packaging the semiconductor device is relatively complicated, no effective solution has been proposed so far.

Contents of the invention

Aiming at the problem that the semiconductor device occupies a large area in the related art and the process of packaging the semiconductor device is relatively complicated, the present invention proposes a semiconductor device packaging structure and a process flow for packaging the semiconductor device, which can simplify the packaging process of the semiconductor device and reduce the The footprint of a completed semiconductor device in a small package.

Technical scheme of the present invention is realized like this:

According to one aspect of the present invention, a packaging structure of a semiconductor device is provided.

The package structure includes:

a substrate, the substrate has a plurality of conductive vias, and the plurality of conductive vias are electrically isolated from each other;

At least one semiconductor device is located on one side of the base structure and is electrically connected to the conductive via hole.

And, the encapsulation structure further includes:

The sealing member forms a sealed cavity with the base, wherein at least one semiconductor device is located in the formed sealed cavity.

Optionally, the above-mentioned semiconductor device includes at least one of the following:

FBAR devices, MEMS devices, active semiconductor devices, passive semiconductor devices.

According to one aspect of the present invention, a packaging structure of a semiconductor device is provided.

The packaging structure includes a plurality of stacked chip structures, wherein each chip structure includes:

a substrate, the substrate has a plurality of conductive vias, and the plurality of conductive vias are electrically isolated from each other;

At least one semiconductor device, located on one side of the base structure, is electrically connected to the conductive via;

Wherein, each chip structure is electrically connected to an adjacent chip structure through a conductive via.

And, the encapsulation structure further includes:

A plurality of sealing members are used to form a sealed cavity for each chip structure, so that at least one semiconductor device of each chip structure is located in the formed sealed cavity.

Wherein, the plurality of seals include at least one first seal, and the first seal is located between adjacent chip structures and forms a sealed cavity between the adjacent chip structures.

In addition, the plurality of encapsulations further includes at least one second encapsulation for forming a sealed cavity for the chip structure located at the end and the semiconductor located outside the encapsulation structure.

Optionally, multiple chip structures are stacked in the same direction or in different directions.

And, the semiconductor device includes at least one of the following:

FBAR devices, MEMS devices, active semiconductor devices, passive semiconductor devices.

According to one aspect of the present invention, a process flow for packaging a semiconductor device is provided.

The process flow includes:

provide the basis;

fabricating a plurality of conductive vias in the substrate, wherein the plurality of conductive vias are electrically isolated from each other;

At least one semiconductor device is manufactured on one side of the base structure, and the at least one semiconductor device is electrically connected to the conductive via hole.

Additionally, the process flow further includes:

provide seals;

The sealing member and the base form a sealed cavity, wherein at least one semiconductor device is located in the formed sealed cavity.

Further, manufacturing a plurality of conductive vias in the substrate includes:

forming a plurality of vias in the substrate;

Fill multiple vias with conductive material.

Optionally, the semiconductor device includes at least one of the following:

FBAR devices, MEMS devices, active semiconductor devices, passive semiconductor devices.

The present invention can simplify the packaging process of the semiconductor device, improve the flexibility of selecting the packaging process, and reduce the overall area of the packaged semiconductor device by making the plurality of conductive through holes in the packaging structure of the semiconductor device be located in the substrate. , the semiconductor device can be electrically connected to the outside world through the conductive via hole.

Description of drawings

Fig. 1 is the schematic diagram of the package structure of FBAR device in the prior art;

2 is a schematic diagram of a package structure of an FBAR device according to an embodiment of the present invention;

3 is a process flow diagram of packaging a semiconductor device according to an embodiment of the present invention;

4a-4d are specific schematic diagrams of the process flow of manufacturing a packaged semiconductor device according to an embodiment of the present invention;

5 is a schematic diagram of a packaging structure of a multi-layer chip FBAR device according to an embodiment of the present invention;

6 is a schematic diagram of a packaging structure of a semiconductor device of a multilayer chip according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a packaging structure of a double-layer chip FBAR device according to an embodiment of the present invention.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of the present invention belong to the protection scope of the present invention.

According to an embodiment of the present invention, a packaging structure of a semiconductor device is provided.

A package structure of a semiconductor device according to an embodiment of the present invention includes:

a substrate, the substrate has a plurality of conductive vias electrically isolated from each other, at least part of each conductive via is located in the substrate, and the portion of each conductive via in the substrate is separated from the The surface on one side extends to the surface on the other side;

At least one semiconductor device is located on one side of the base structure and is electrically connected to the conductive via hole.

Moreover, the packaging structure according to the embodiment of the present invention further includes: a sealing member forming a sealed cavity with the substrate, wherein at least one semiconductor device is located in the formed sealed cavity. The semiconductor device works in the sealed cavity formed by the substrate and the sealing member, which prevents the electrode from being corroded by impurities or water vapor, and the performance of the semiconductor device deteriorates.

In addition, the number of semiconductor devices, the electrical connection relationship between semiconductors, and the electrodes that each semiconductor device needs to be electrically connected to the outside world determine the number of conductive vias.

Optionally, the above-mentioned semiconductor device may include at least one of the following: FBAR device, MEMS device, active semiconductor device, and passive semiconductor device. Wherein, the FBAR device includes devices composed of FBAR known to those skilled in the art, for example, filters, resonators, oscillators and the like.

In practical applications, when the semiconductor device is an FBAR device, the packaging structure of the semiconductor device according to the embodiment of the present invention may be as shown in FIG. 2 . The packaging structure including semiconductor devices shown in FIG. 2 includes: a base wafer 20, two conductive vias 21, an acoustic reflection structure 22, a bottom electrode 23A, a piezoelectric layer 23B, an upper electrode 23C, a sealing material 24, and a packaging wafer. 25 and cavity 26. Two conductive vias 21 are located in the base wafer 20 , and the electrical connection between the bottom electrode 23A and one conductive via 21 and the electrical connection between the upper electrode 23C and the other conductive via 21 can ensure the conductive communication between the FBAR device and the outside world.

The bonding method of the packaging wafer 25 and the base wafer 20 can use silicon-glass anodic bonding, silicon-silicon eutectic bonding, interlayer bonding, and the like. And according to different bonding methods, different sealing materials 24 are selected. The sealing material 24 can be selected from conductive materials, such as gold, copper, aluminum, etc.; the sealing material 24 can also be selected from non-conductive materials, such as silicon dioxide, epoxy resin, etc. . This reflects the flexibility of bonding technology selection. In an embodiment not shown, the package wafer may be directly bonded to the base wafer, and the encapsulant 24 may be omitted. The bonding of the packaging wafer 25 and the base wafer 20 makes the FBAR device located in the sealed cavity 26, which ensures that the FBAR device works in a sealed cavity, and avoids the FBAR device from occurring when there are impurities or water vapor on the electrode surface. In case of frequency shift or degraded performance.

The electrodes of the FBAR device are respectively connected to the corresponding conductive vias 21 or to electrodes of other FBAR devices, wherein at least one electrode of the FBAR device is connected to one conductive via 21 .

According to one aspect of the present invention, a process flow for packaging a semiconductor device is provided.

As shown in FIG. 3, the process flow of packaging a semiconductor device according to an embodiment of the present invention may include:

Step 301, providing a substrate;

Step 303, manufacturing a plurality of conductive vias in the substrate, wherein the plurality of conductive vias are electrically isolated from each other;

Step 305 , fabricate at least one semiconductor device on one side of the base structure, and at least one semiconductor device is electrically connected to the conductive via hole.

In addition, the process flow according to the embodiment of the present invention may further include:

provide seals;

The sealing member and the base form a sealed cavity, wherein at least one semiconductor device is located in the formed sealed cavity.

Wherein, making a plurality of conductive vias in the substrate may include:

A plurality of through holes are formed in the substrate, and a plurality of through holes can be formed in the substrate by using deep silicon ion reactive etching (DRIE) and other methods for making through holes known in the art;

The plurality of via holes are filled with a conductive material, where the conductive material may include Cu, Au, or the like.

Optionally, the semiconductor device may include at least one of the following: FBAR device, micro-electromechanical device, active semiconductor device, and passive semiconductor device. Wherein, the FBAR device may include other devices composed of FBARs known to those skilled in the art, for example, filters, resonators, oscillators and so on.

According to the process flow of the embodiment of the present invention, Figure 4a-Figure 4d shows a packaging method for manufacturing the packaging structure shown in Figure 2, specifically including:

As shown in FIG. 4 a , two conductive vias 21 are fabricated on the base wafer 20 . The manufacturing process of the conductive via hole 21 is divided into: 1. Form a via hole on the base wafer by deep silicon ion reactive etching (DRIE) technology; 2. Fill the via hole with a conductive material: sputter a layer on the inner wall of the via hole The metal seed layer is then filled with metal in the through hole by electroplating, and the metals filled by electroplating are commonly used such as Cu, Au, etc. The upper ends of the conductive vias 21 are connected to the electrodes of the FBAR device (such as the bottom electrode 23A and the upper electrode 23C). The lower end of the conductive via hole 21 will be connected to other external substrates or circuit structures, and the connection method may be wire bonding, flip chip bonding, or other forms. Such a through-hole filling technology can form a through-hole with good electrical conductivity, so that the FBAR device can form a reliable electrical connection with the outside world.

As shown in Fig. 4b, a three-layer structure of the FBAR device is fabricated: a bottom electrode 23A, a piezoelectric layer 23B and an upper electrode 23C. The top and bottom electrodes of the FBAR device are respectively connected to different conductive vias to realize the interconnection of electrical signals. In this embodiment, the manufacturing process of the acoustic reflection structure is omitted.

As shown in FIG. 4 c , a sealing material 24 is fabricated on the base wafer 20 , and the material used for the sealing material 24 depends on the packaging wafer and packaging technology. In an embodiment not shown, the package wafer may be directly bonded to the base wafer, and the encapsulant 24 may be omitted.

As shown in FIG. 4 d , a cavity 26 is formed by bonding the packaged wafer 25 (or other packages) and the base wafer 20 . Usually, the packaging wafer 25 and the base wafer 20 are bonded through the encapsulant 24 .

According to the process flow of packaging a semiconductor device according to an embodiment of the present invention, a packaging method for manufacturing conductive vias on a base wafer in advance, and then manufacturing an FBAR device. The electrodes of the FBAR device are connected to the conductive vias to realize the extraction of electrical signals. Finally, the packaging wafer and the base wafer are bonded to form a sealed cavity to isolate the FBAR device from the outside world. Because this packaging structure separates the formation of the sealing member from the connection of electrical signals, it reduces the difficulty of implementing the packaging process and increases the flexibility of the choice of wafer bonding technology. In this packaging structure, since the conductive vias are made on the base wafer, no additional area around the conductive vias is required for sealing and bonding, so the packaging area of the overall semiconductor device can be reduced. In addition, since the FBAR device is processed after the conductive via hole is processed, the FBAR device will not be affected by harsh environments such as high temperature during processing the conductive via hole, which reduces the difficulty of the manufacturing process of the FBAR device.

According to one aspect of the present invention, a packaging structure of a semiconductor device is provided.

A packaging structure according to an embodiment of the present invention includes a plurality of stacked chip structures, wherein each chip structure includes:

a substrate, the substrate has a plurality of conductive vias, and the plurality of conductive vias are electrically isolated from each other;

At least one semiconductor device, located on one side of the base structure, is electrically connected to the conductive via;

Wherein, each chip structure is electrically connected to an adjacent chip structure through a conductive via.

And, the packaging structure according to the embodiment of the present invention may further include:

A plurality of sealing members are used to form a sealed cavity for each chip structure, so that at least one semiconductor device of each chip structure is located in the formed sealed cavity. Wherein, the plurality of sealing elements may include at least one first sealing element, and the first sealing element is located between adjacent chip structures and forms a sealed cavity between adjacent chip structures. In addition, the plurality of sealing members may further include at least one second sealing member for forming a sealed cavity for the chip structure located at the end and the semiconductor device located outside the package structure. Optionally, multiple chip structures can be stacked in the same direction or in different directions.

Also, the semiconductor device may include at least one of the following: FBAR device, MEMS device, active semiconductor device, and passive semiconductor device.

In practical applications, when the semiconductor device is an FBAR device, the packaging structure of the semiconductor device according to the embodiment of the present invention provides a packaging structure as shown in FIG. 5 . The package structure shown in FIG. 5 includes a plurality of chips stacked in the same direction, and some chips are omitted. Each chip includes a substrate, conductive vias, FBAR devices, and 33 structures used to seal adjacent chips. In addition, , further comprising a packaging wafer 50 for packaging the first chip. The packaging wafer 50 is bonded to the first chip 40 to provide a sealed cavity for the FBAR of the first chip. The electrodes of the first chip 40 are connected to the conductive vias 31 of the second chip 30 through the conductive vias 41, which may further include a bonding structure 34 for electrically conducting the conductive vias 41 and the conductive vias 31. In addition, the bonding The joint structure 34 and the sealing material 33 also play a certain structural support role, and there may be conductive parts and sealing materials between every two adjacent layers, which will not be described below. The first chip 40 is bonded to the second chip 30 to form a cavity 35 for the FBAR device of the second chip 30 . The electrodes of the second chip 30 are connected to the conductive vias of the underlying chip through the conductive vias 32 . In addition, in addition to the necessary electrical communication with the lower layer, the electrodes of any chip can also be connected with external circuits. By analogy, multiple chips are connected together.

According to the semiconductor device packaging structure of the embodiment of the present invention, various semiconductor devices can be packaged. The package structure shown in Figure 6 is basically the same as that in Figure 5, except that the packaged semiconductor structure (shown as semiconductor devices 11 and 21 in Figure 6) may include other semiconductor devices other than FBAR devices or any combination thereof, and the semiconductor device may include a microcomputer Electrical devices, active or passive semiconductor devices. The multi-chip stacked package structure has obvious advantages in reducing the size of the package and reducing the cost of the product.

The duplexer consists of a receive filter Rx and a transmit filter Tx. Since the frequencies of Rx and Tx are different, it is difficult to simultaneously manufacture Rx chips and Tx chips on the same wafer. A common practice is to manufacture the Rx chip and the Tx chip separately, and then package the two chips together. A conventional packaging structure is to place the Rx chip and the Tx chip horizontally, and then connect the two chips to the substrate by wire bonding or flip-chip bonding. The semiconductor device packaging structure according to the embodiment of the present invention can also provide a duplexer based on FBAR device packaging. Compared with the conventional horizontal package structure, the duplexer of the package-on-package structure according to the embodiment of the present invention reduces the area by half, and also reduces the use of package wafers.

In practical applications, when the semiconductor device is an FBAR device, the packaging structure of the semiconductor device according to the embodiment of the present invention provides a packaging structure as shown in FIG. 7 . The packaging structure shown in FIG. 7 includes two stacked chips in different directions, and the packaging structure includes: a first base wafer 70, a first FBAR device 70, a second base wafer 60, a sealing material 61, and a bonding structure 62 , the second FBAR device 63 and the conductive vias in the second base wafer 60 . The first base wafer 70 and the second base wafer 60 are bonded through the sealing material 61 to provide a common sealed cavity for the first FBAR device 71 and the second FBAR device 63 . The two electrodes of the first FBAR device 71 are respectively electrically connected to the two outer conductive vias located in the second base wafer 60 through two bonding structures 62 to achieve electrical communication with the outside world, while the second FBAR device 63 is It is directly electrically connected with the two inner conductive vias in the second base wafer 60 to achieve electrical communication with the outside.

According to an embodiment of the present invention, the package structure shown in FIG. 7 utilizes substrate wafer bonding of two chips to form a shared sealed cavity. The electrodes of the upper FABR device are connected to the conductive vias on the lower substrate wafer, so that electrical signals are led out of the sealed cavity. Such a packaging structure can reduce the usage of packaging wafers while reducing the package size. Meanwhile, the fabrication of conductive vias on the first base wafer is omitted. In addition, since the FBAR device is processed after the conductive via hole is processed, the FBAR device will not be affected by harsh environments such as high temperature during processing the conductive via hole, which reduces the difficulty of manufacturing the FBAR device. Therefore, the structure can not only reduce material cost and chip size, but also simplify process steps. .

The manufacturing method and wafer bonding method of the conductive vias in the embodiments shown in FIGS. 5-7 are basically the same as those in FIGS. 4a-4d.

In summary, with the help of the above technical solution of the present invention, the present invention can simplify the packaging process of the semiconductor device and improve the flexibility of selecting the packaging process by making a plurality of conductive vias in the packaging structure of the semiconductor device located in the substrate. and reduce the overall area of the packaged semiconductor device. In addition, the semiconductor device and the conductive via can realize the electrical connection between the semiconductor device and the outside world through the conductive via. Further, in the structure of multi-layer chip packaging, the application of packaged wafers can be reduced, the material cost can be reduced, the chip size can be reduced, and the formation of the sealed cavity can be separated from the manufacturing process of connecting via holes and electrodes, which can reduce the It reduces the difficulty of manufacturing semiconductor devices, improves the flexibility of wafer bonding technology selection, and reduces the overall packaging area.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of the present invention. within the scope of protection.

Claims (4)

1. A packaging structure for a semiconductor device, characterized in that it comprises a plurality of stacked chip structures, Among them, each chip structure includes: a substrate having a plurality of conductive vias electrically isolated from each other; At least one semiconductor device, located on one side of the base structure, is electrically connected to the conductive via; Wherein, each chip structure is electrically connected to an adjacent chip structure through a conductive via; And, a plurality of sealing members are used to form a sealed cavity for each chip structure, so that at least one semiconductor device of each chip structure is located in the formed sealed cavity; Wherein, the plurality of seals include at least one first seal, and the first seal is located between adjacent chip structures and forms a sealed cavity between adjacent chip structures; Wherein, the plurality of sealing members further include at least one second sealing member, the second sealing member is used to form a sealed cavity for the chip structure located at the end and the semiconductor device is located outside the packaging structure; Wherein, the plurality of chip structures are stacked in the same direction or in different directions. 2. The packaging structure according to claim 1, wherein the semiconductor device comprises: a micro-electro-mechanical system device. 3. A packaging process flow for a semiconductor device, characterized in that it comprises: Fabricate a chip comprising: provide the basis; fabricating a plurality of conductive vias in the substrate, wherein the plurality of conductive vias are electrically isolated from each other; Fabricating at least one semiconductor device on one side of the base structure, the at least one semiconductor device is electrically connected to a conductive via; stacking a plurality of chips, wherein each chip structure is electrically connected to an adjacent chip structure through conductive vias; and, providing seals; The sealing member and the substrate form a sealed cavity, wherein the at least one semiconductor device is located in the formed sealed cavity; Wherein, making a plurality of conductive vias in the substrate includes: forming a plurality of vias in the substrate; The plurality of via holes are filled with a conductive material. 4. The packaging process according to claim 3, wherein the semiconductor device comprises: a micro-electromechanical device.