CN1033912A - Three-phase curtain-type asynchronous superconductive motor - Google Patents

Abstract

A kind of curtain-type cryomotor belongs to heterogeneous asynchronous induction type motor.Its stator structure is identical with the stator of common phase asynchronous formula motor, the structure of rotor is then for being fixed on the iron core that is built up by silicon steel sheet in the rotating shaft, and vertically and the electric conductor that is located in the one-tenth even number in the iron core parallel to each other, each electric conductor is insulated from each other, and is uniform mutually.

Description

Three-phase curtain-type asynchronous superconductive motor

The present invention relates to telephone communication set and method, and, more precisely, relate to the babyphone system and the similar system that are often referred to key telephone system.

The telephone system of different scales also has corresponding different architecture.For example, central office is normally large-scale, and, it is characterized in that being predetermined to include the telephone line of concentrating in the network of switching through that is subjected to central controller controls, described central controller receives the visit of various peripheral controllers.For extreme reliability, central controller, switch through network, even some peripheral controllers all has backup, reach the reliability of function by means of redundancy.Provide large-scale function software handling these elements, though so that unavoidably can accidental break down or malfunctioning, can be constant basically to telephone subscriber's service.By comparison, various private branch exchanges (PBXs) tend to littler and more responsive to cost.The various architectures of PBX are similar to the architecture of central office usually, yet, have less backup and redundancy, thereby, less functional reliability had.Time-division multiplex commonly used, the advantage of pulse-code modulation transit exchange are a lot, but, one of outstanding advantage is: be applicable to and transmit sound and/or data-signal, generally with the basic rate of 64 kilobits/second, perhaps the standard of for example advising according to nearest ISDN(Integrated Service Digital Network) (ISDN) transmits.Another advantage of having demonstrated in common modern telephone switch is: when having only the single phone circuit that telephone set is linked switch actually, can manifest a plurality of telephone numbers or extension on any telephone set.

Some example of very small-sized telephone system is commonly referred to key telephone system.By convention, constitute key telephone system by the lead-in wire of the control between extension circuit and the key telephone set.Every the keyphone circuit extends to telephone exchange.Every telephone set comprises some push-button switches or key.Each push-button switch or key are used for telephone set is connected to the specific telephone wire of some telephone lines of delivering to key telephone set.The changing-over function that circuit between each key telephone set is selected provides with mechanical means and distributes.Must be in any feature that adds on every line tower foundation except that the plain language normal telephone service.The major advantage of these systems is economical and small-sized.Yet if require such system to expand along with the mechanism of its service, so, after a period of time, aspect every circuit and critical piece, it becomes more expensive more than private branch exchange at last.Also being the analog signal type on the key telephone system characteristic, therefore, is being unpractical aspect the connecting of the ISDN that may need with business user in the near future.

The purpose of this invention is to provide a kind of telephone system, in this system,, make the functional advantage and the digital signal communication coexistence of key telephone system by means of each key telephone set that is connected to separately with the single phone line in the described system.

In one embodiment, provide a kind of key telephone system, in this system, use one or more clock switches, exchange time-division multiplex signal between each telephone set.Each clock switch is modular, makes a clock switch module can only handle the traffic request of the group's telephone line that occurs.Therefore, the essential part of interconnecting device is the cordwood system type increment, so that the quantity of the expense key telephone set of being served with system basically is directly proportional.

According to the present invention, be used for the digital signal communication path is provided between the number of digital signalling arrangement, and be used between any digital signal equipment and the communication channel related, providing the key telephone system of communication line to comprise: send the practicable switching device that (TDMT) channel and time-devision system multipath reception (TDMR) interchannel provide communication path in the time-devision system multichannel with telephone exchange.Some time-devision system multichannels (TDM) communication path, every comprises n to TDMT and TDMR channel, transmits and receive bit stream respectively.Described each digital signal equipment can be connected with each key telephone system by a corresponding path in the number of digital signal communication path separately.One of internal port device and described TDM communication path interrelate.Be used for from some TDMR channel receiving informations, and corresponding information transferred to a fixed corresponding path in the number of digital signal communication path, and, be used for receiving information from path described in the described digital signal communication path, simultaneously, corresponding information is sent to each corresponding TDMT channel.External port means is coupling in the information signal of the communication channel that interrelates with telephone exchange and at least one pair of TDMR and TDMT interchannel.Call controller reacts to the signal from any digital signal terminal and telephone exchange, is used to handle the call proceeding operation of switching device.

The method that is used for control figure key telephone system digital signal communication path according to the present invention may further comprise the steps:

A) from first transmission medium of being worked out by consecutive frame and starting point channel, sequentially each bit status is sent in each special-purpose time slot in the transmission medium of being worked out by concurrent frame;

B) specify in the described time slot one at least, from the time slot of this appointment bit status is deposited in the first memory, the latter has many memory cell, each memory cell is corresponding to possible purpose channel in second transmission medium of being worked out by consecutive frame and channel, specify in the time slot of one of described memory cell and described appointment each to interrelate, and, when specified time slot occurs, described each bit status is deposited in described designated memory locations;

C) each corresponding memory cell appears synchronously reading in the channel with described second transmission medium;

D) when each designated memory locations is read, each bit status is added in the transmission medium of the second parallel establishment, and, also add the bit status that each is predetermined in addition;

E) when each bit status appears in the described second parallel transmission medium of working out, capture described each bit status, and, during the instant channel of second transmission medium of working out by consecutive frame and channel, add each serial data state that the above is captured at last, whereby, in the starting point channel, information is sent in the digital key system, then, from this digital key telephone system, sends to the purpose channel.

This method can also comprise following each step:

F) another time slot in described each time slot of appointment in this time slot, deposits each bit status in the second memory in, and the latter has a memory cell at least, and, described each bit status is deposited in wherein;

G) specify by a channel in second transmission medium of consecutive frame and channel establishment;

H) moment that specified channel occurs in corresponding to step g), each bit status in the memory cell that is stored in second memory is added in the 3rd matchmaker's medium of parallel establishment;

I) in second, third medium of the parallel establishment of selection, the foundation of selection is: corresponding each bit status that adds in this medium has high value, and

In step e), from the medium of described selection, capture described each bit status,

Whereby, select the information in one of two starting point channels, and, this information is delivered to described purpose channel from described digital telephone keyed system, so as with the corresponding substation of purpose channel on the function of videoconference is provided.

Below in conjunction with accompanying drawing embodiment is described, in the accompanying drawing:

Fig. 1 is the calcspar according to key telephone system of the present invention;

Fig. 2 is the operation timing pulse that produces of circuit handover module used in Fig. 1 and/or the picture specification of signal;

Fig. 3 provides the calcspar of timing sequence generator used in the circuit handover module of timing signal illustrated in fig. 2;

Fig. 4 is the block schematic diagram that is used for each counter of Fig. 1 circuit handover module and predetermined time slot that is provided for operating this circuit handover module and channel address;

Fig. 5 is the block schematic diagram that is used for the converter circuit of Fig. 1 circuit handover module;

Fig. 6 is the picture specification that is used for the various timing signals of application drawing 5 converter circuits;

Fig. 7 is the circuit handover module that is used for Fig. 1, so that the block schematic diagram of time switch circuit of the circuit of transfer message path is provided in digital key telephone system; And

Fig. 8 is the block schematic diagram of clock switch conference circuit in the circuit handover module, and this circuit is used for combining with the time switch circuit of Fig. 7, so that conference features is provided in digital key telephone system.

Among Fig. 1, digital key telephone system is for connecting for example with 13 and 14 illustrated various digital telephone devices, and for example create conditions with 15 and 17 illustrated various data terminals, special-purpose computer or analog, these equipments can communicate by optional each other object via this system, and, communicate by letter with other devices by circuit or trunk 23.Described each circuit and/or trunk line are used for connecting digital key telephone system and other telephone plants, for example, and general bureau or private branch exchange system (not shown).The Zhi Gan of digital key telephone system is made of short parallel time-division multiplex (TDM) bus 10, and bus 10 provides the broadband connections path at the circuit handover module 100 that reaches nine 64 channels between call controller 8 and the audio-source 26.If any in the audio-source 26 provides a kind of analog signal, then above-mentioned signal just is coupled in this system via lead-in wire 27.Bus 10 is called as bus one time, and secondary bus 20(is similar to bus 10 one time) one-way communication from call controller 8 is provided.Each module in the circuit handover module 100 sends serial channel to 64 ten bits and is coupled on the corresponding time slot predetermined in the bus 10, and, or in bus 10 or be coupled to 64 bits at nearly 64 the parallel selected TDM time slots on the bus 20 and receive on the serial channels.32 channels in serial transmission and the receive channel are coupled to internal port circuit 12 via serial TDM path 11.Remaining 32 serial transmission and receive channel are coupled to outside port circuit 22 via serial TDM path 21.In the described channel each can transmit the binary signal stream of pulses with the speed of 80 kilobits/second, simultaneously, as the channel that is used for pulse-code modulation (PCM) audio-frequency information or data message, at least can be with the speed of 64 kilobits/second.Remaining 16 kilobit can be put to communicate by letter with signaling with the supervision of PCM or data message combination, perhaps, can be used for other occasions easily.In the present embodiment, internal port circuit 12 is made of 16 TDM time compression multichannels (TCM) interface.The TCM signal transmission form often abbreviates " reciprocating type " (" ping pong ") transmission as.19 and two serial TDM interchannels predetermined and that fix of in these interfaces each each TCM network joint in serial TDM path 11 provide drive access.In a similar fashion, each analog signal is by means of the outside port 22 that is provided by the CODEC circuit, and via serial TDM path 21 dealings ground and various trunk lines or circuit 23, and/or driving or buffer circuit 24 and 25 link.On the other hand, by means of digital signal transmission network joint, for example T ₁Or DS30, the outside TDM port that is provided for being connected with other telephone plants may be favourable.Yet under this kind situation, the predetermined and fixing transmission of each CODEC circuit and IEEE Std serial highway 21 and receive channel are to linking.Therefore, for every kind of line status (promptly, the digital telephone device, or other digital devices, or digital connection or compatible circuit, trunk line, or the like may insert the place of described digital key telephone system), in a bus 10, have ten predetermined bit parallel time slots at least, the designated reception of the latter is from the information of described line status.In another embodiment, each time slot on bus 10 is the line status that information is sent to the there corresponding to some.But this paper does not further discuss above-mentioned another kind of embodiment.Call controller 8 and one or more audio-source 26 are connected on bus 10, are used for communicating via remaining 64 ten bit parallel time slots.Call controller 8 can receive whole ten bits of each time slot on the bus 10.Usually, for the purpose of calling out control, 8 dibit numbers that divide channel from bus 10 receptions corresponding to 16 kilobits again of call controller.When call controller 8 occurs at the time slot of line status purpose corresponding to expection, by means of circuit handover module 100(but not regularly conversion) communication be provided and monitor via secondary bus 20.Therefore, each circuit handover module 100 sends 10 bits to a bus 10, still, only receives 8 bits from a bus 10, and dibit receives via secondary bus 20 in addition.In embodiment, realized remarkable economic efficiency especially with this structure than this digital key telephone system on a small scale.Use in the hardwired time-division device of additive method this, this structure provides the circuit switching capability.If expand this digital key telephone system, so, as required, condition has been created for using other 64 TDM channel statuss in additional other circuit handover modules 100 and necessary inside and/or outside port 12 and 22.

Below with reference to Fig. 2-11, discuss the structure and the working condition of cordwood system type circuit handover module 100 in more detail.

In order to make each module in one or more circuit handover modules 100, can not have under the situation of contention, information is sent to parallel TDM bus 10 from serial TDM path 11 and 21, phased as shown in Figure 3 time sequencing device is present in each module in described each module 100, is used for the function of adjusting module.The prime frame pulse that illustrative waveform explanation occurs with 1 KHz frequency among Fig. 2, with the clock pulse that is numbered 0-27 of 5.12 mhz frequencies appearance, and machine state commutator pulse SMO-SM10.Under handover module 100 was installed to situation in the native system, preset started decode machine 101 and is connected to hardwire unit (not shown), and this decode machine provides identification code, that is, and and 4 fixing bit-binary word IDO-ID3.The combination of each bit signal state of described ID0-ID3 is a monodrome for each the possible handover module unit in the described digital key telephone system.Preset starts decode machine 101 responses bit status combination as shown in table 1, produces 5 bit-binary words on bus 102.Five bit counter 103 preset according to each appearance of prime frame pulse, so that corresponding to the word on the bus 102, after this, the increment along with the appearance of each clock pulse.The output 104 of counter 103 is deciphered by decode machine 105, and decode machine 105 produces reset signal along with each occurrence count 19 in the counter 103 on lead-in wire 106.So when next clock pulse occurred, counter 103 reset to count of zero.Thereby, provide mould 20 tally functions, the latter as illustrated in the table 1 by phased.

Table 1

Bus of circuit 102 TDM-11 TDM-21

The preset value that switches ID3 ID2 ID1 ID0 conform to frame and conform to frame with

Module time slot time slot

0 0 0 0 0 18 0 2

1 0 0 0 1 17 1 3

2 0 0 1 0 14 4 6

3 0 0 1 1 13 5 7

4 0 1 0 0 10 8 10

5 0 1 0 1 9 9 11

6 0 1 1 0 6 12 14

7 0 1 1 1 5 13 15

8 1 0 0 0 2 16 18

According to this table, for example, for circuit handover module 0, channel 0 on the serial TDM path 11 inserts in the time slot 0 on parallel TDM bus 10, channel 1 inserts in the time slot 20, by that analogy, and till channel to the last (being the channel 31 of serial TDM frame) inserts in the time slot 620.

Change a kind of saying, every TDM passage has 32 parallel ten bits that are assigned to it to accept channel on a bus 10, and each bar in these channels separates with another channel owing to the appearance of 19 other channels.

Decode machine 105 also produces the SMO commutator pulse, and this commutator pulse takes place simultaneously with the counting 19 that occurs in counter 103.Shift register 109 response SMO commutator pulse and clock pulse produce as at additional commutator pulse SM1-SM10 illustrated in fig. 2.

With reference to Fig. 4, the described time slot that appears on the parallel TDM bus 10 is followed the tracks of by parallel time slot counter, and this counter comprises mould 20 counters 111 and mould 32 counters 112.Counter 111 response 5.12 megahertz clock pulse provide 0 up to 19 repeat count on time slot 5 counting lead-in wire TSC0-4.Counter 112 resets along with each that occurs in counter 111 and obtains increment, on timing piece 5 counting lead-in wire TBC0-4, provide 0 until 31 repeat count, make up the binary signal on the TBC 0-4 lead whereby, define the address of 640 parallel time slots of every frame.Provide the serial channel counter function by counter 113, this counter provides 32 channel counter addresses on serial channel counting lead-in wire SCC0-4, with the appearance of channel in regulation serial TDM path 11 and 21.Counter 113 is along with the increment by the appearance of each indicated time block of commutator pulse SM6.All counters 111,112 and 113 reset along with each appearance of prime frame pulse.

Converter circuit illustrated in fig. 5 is present within the circuit handover module 100, and, for each bar channel of described 64 TDMT on TDM path 11 and 21 and 64 TDMR channels, both finished from serial-to-parallel conversion, finish again from parallel-to-serial conversion.As previously mentioned, each TDMT channel is introducing and conducts data or sound, add the signal bit that originates from terminal equipment, and each TDMR channel exported accordingly, leads to the terminal equipment of origin separately.Each input time slot comprises 10 binary bits, and the latter directly is converted to parallel form, and is being added to during the described predetermined time slot on bus 10.Each output time solt comprises 10 binary bits, latter system obtains from one or two source: source is the corresponding slot time on the secondary bus 20, another source is 8 bits from any slot time on bus 10, this 8 bit adds 2 bits from the described slot time that occurs corresponding to the TDMR channel on the secondary bus 20, and the cross-section described time switches.

Each timing signal below with reference to illustrated in fig. 6 discusses described converter circuit in more detail.For convenience's sake, some other waveform tracing among the system clock waveform shown in Fig. 6 top and Fig. 6 is become to have the part of vertical takeoff and landing (VTOL).In fact, be similar to illustrated in fig. 2ly, these waveforms all have the part of rising and falling of inclination, and the waveform shown in Fig. 2 is described more practically.Converter circuit comprises three respectively with the shift register of quadratures of 501,502 and 503 expressions.These three registers are finished desired from serial-to-parallel, and from parallel-to-serial conversion.In the shift register 501,502 and 503 of quadrature each and clock generator associated (not shown), this clock generator produces the timing signal of non-overlapping illustrated in fig. 6, is used for displacement and directed control.Vertical orientation control signal V ₁, V ₂And V ₃Be respectively applied for register 502,501 and 503 vertical sensing shift function.Horizontal orientation control signal H1, H2 and H3 are used for the level of register 502,501 and 503 and point to shift function.The actual loading of the D flip-flop element in the register 502,501 and 503 is by signal pulse S ₁, S ₂And S ₃Come timing.Control signal V ₂And V ₃Be shown in broken lines, to show: these signal pulses have 20 system clock cycles that take out from contiguous H2 and H3 signal pulse, therefore, each signal pulse is since 40 system clock intervals.Arrange the time of each bit of described TDMR serial bit stream, they are overlapped with the rising edge of serial digital loop clock signal C 690.Each bit of TDMT serial bit stream on path 11 and 21, by latch 511 and 521 samplings, and, be rearranged the time, so that overlap the samely with top.The half period of system clock has precedence over serial digital loop clock signal C 690, receives the poke that multiplexer 535 is selected the register 502 of (2 * 8) output, so that first bit of each channel in 11 and 12 the above TDMR channel to be provided.MUX SEL OUTGOING control signal shown in the selection response diagram 6 of described reception multiplexer is carried out.The time of arranging respectively to export bit by clock signal C 690 rising edges is to start the transmission of 10 bit time slots.Shortly after that, latch 511 and 521 utilizes the drop edge of same clock signal C 690 that the initial bits of corresponding TDMT channel is taken a sample.Then, the bit after the sampling is added to (2 * 2) input register 501.In described same 690 duration of clock signal C, multiplexer 532 is existing the poke of register 502 and input register 501 to be added in concurrently on the lead-in wire of a bus 10.Only this time slot of time slot (TS) 19(by Fig. 6 in the rising edge of decode18 show) moment of occurring, multiplexer 532 just can select to lead to the Z-bus signal condition of P bus 10.During the half period of the described same system clock signal after the drop edge of described same C690 clock signal, the register 501,502 and 503 of three quadratures is by timing, cause input register 501 to accept described initial bits, output register 503 is displaced to multiplexer 535 to the second output bit, and register 502 is shifted to multiplexer 532 to 8 bits of TDMT path 21.Simultaneously, input register 501 is shifted to multiplexer 532 to remaining two bits via multiplexer 533.Under the control of timing signal SM2 and SM6,, two output parallel information bytes that are right after are moved into register 502 via data holding register 504 and 505.At synchronization, as previously mentioned, initial two bits of every input of register 501 storages TDMT channel.In case initial two bits occur, register 501 and 503 no longer receives other clock signal, till next output time solt sequence starts when whole 10 bit parallels are shifted to P bus 10.

When the sequence of time slots that startup is right after, cause posting at device 501 and 503 (that is direction that makes progress among Fig. 5) on longitudinal direction and move their corresponding 2 bit pokes.After this, with TDMT8 the bit shift-in register 502 on longitudinal direction that is right after, and previous poke is moved out of, via multiplexer 535 and TDMR path 11 and 21 and transmit.Horizontal direction control signal and vertical direction control signal continue alternately to exist, thereby every TDM channel on TDM path 11 and 21 repeats from parallel-to-serial, and from serial-to-parallel circulation.

Time switch circuit among Fig. 7 is that condition has been created in following information transmission, promptly, the input that periodically is delivered to the parallel T bus of the parallel input multiplexer 506 of converter circuit among Fig. 5 from 8 information bits in one of 640 time slots on bus 10, and, guided according to call controller 8, thus, finally be delivered in the time slot of TDM path (11 or 21).The information bit of each time slot is temporarily captured by data input latch device circuit 710 on the P bus 10, after this, just is added to the input 702 of dual-port random access memory (RAM) 701.Two-port RAM 701 comprises output 703, and latter's response is added in 6 bit addresses on the read access address port 704 and drives T bus 770.The difference of described RAM701 and common both-end storage device is: in order to be stored in the information that its input 702 receives, it does not comprise common address decoding circuitry.And replace the decoding of each write address, and, be added to 64 at 706 places and allow to write on independent of lead-in wire.By means of allowing to write latch and gating circuit 720 and the time of the write address after arranging described decoding.Can there be any amount of lead-in wire that allows to write simultaneously in described circuit 720.Depend on the circumstances, described two-port RAM 701 is by being stored in the signal condition of described 8 bit informations corresponding memory cell (or each memory cell), comes to exist signal (or a plurality of signal) to make a response to allow to write in the lead-in wire any lead-in wire or institute at 64 at 706 places on leaded.For example, do not assert then do not have memory cell to be written into,, then write one or more corresponding memory cell if one or more lead-in wire is assert at 706 places if having lead-in wire at 706 places.At the latch 711 that triggers by signal SM2 and SM6 and in 32 TDM channel addresss that counter 113 orders produce in by Fig. 4, regular and periodically under the control of trigger (not shown) signal, call over 64 two-port RAM memory cell.

Connected storage 730 comprises the information about the actual time slot in described 640 P bus 10 time slots, and therefrom, the information bit state is stored in the two-port RAM 701.Connected storage 730 is made of content-addressed memory, and the latter comprises 11 Bit data input ports, 731,6 bit addresses ports 732 and 10 bit compare address ports 733.The general structure of content-addressed memory and operation are known.In the above-described embodiments, each address of P bus (information is what to prepare from this storage) is deposited in each memory cell of connected storage 730.Each memory cell (not shown) in 64 memory cell and 64 output leads at 736 places independent one corresponding.Each unit associated in digital comparator (not shown) and 64 memory cell compares with the information that is stored in 64 memory cell separately so that appear at each address of comparison port 733.Identical in the address of port 733 relatively with information in memory cell, and described memory cell also comprises each moment of a significant bit that adds, and the corresponding velamen that 736 places are stated in 64 output leads adds.This state that adds is passed to two-port RAM 701 via circuit 720 at last, and the latter replys as described above.

By the operation of call controller 8 manipulation digital key telephone systems, this controller uses 32 dedicated time slots on the p bus, by means of data-latching circuit 740 and address latch circuit 750, information is deposited in each memory cell of connected storage 730.By the form delivery information of call controller 8 with nybble, each byte takies the time slot 19 of the time block of 4 order appearance on the P bus 10.Described four bytes comprise: command byte, then be address byte, low data byte and high position data byte.Each and useful signal are added on one of two remaining lead-in wires of P bus 10 together in these bytes, and this shows that described byte is actually the instruction from call controller 8.A part or the regulation of command information group are write function, and perhaps regulation is read function, and these functions are intended to for connected storage, one of source connected storage or purpose connected storage usefulness.Comparator responds the remainder of described useful signal and command byte and the comparison between the ID0-3, the byte that the address latch storage is right after, i.e. address byte.After this, data latches 740 is captured 11 bit status of low level and upper byte, and as indicated in 6 address bits that added by address latch 750, described height is stated in the memory cell that high low byte sequentially is stored in connected storage 730.For call controller 8 has been taked measure, to determine the information poke of any address in the connected storage.In this case, function is read in described command byte indication, simultaneously, and the memory cell that the address byte indication is to be read.The low level of described order and high-order information sets are driven by information data output end 738, that stored from connected storage 730, then, arrive Z-bus via output latch 712 and buffer 713, be sent to P bus 10 aspects via the multiplexer among Fig. 5 532 therefrom again.

Clock switch conference circuit among Fig. 8 provides the tripartite talks feature in digital key telephone system.Described clock switch conference circuit increases a kind of ability, promptly, be used for and periodically be sent to described TDM channel interval at last from 8 information bits (for example, in front to related at the beginning in the discussion of Fig. 7) of other parts of 640 time slots on the bus 10.Very tout court, with the mode of foreword, by means of the T bus 770 of drawing, and meeting C bus 991, described each byte is offered multiplexer 992 from Fig. 7.4 significant bits the highest (not comprising sign bit) that in comparator 993, compare each byte, if be equal to or greater than value from 4 bits of T bus 995 from the value of 4 bits of C bus 991, then this comparator operations multiplexer 992 is added to 8 bits from C bus 991 on the T bus 540.If the value of T bus 995 is bigger, then multiplexer 992 is added to 8 bits from T bus 995 on the T bus 540.Like this, can realize tripartite videoconference, in the meeting, each side only listens and obtains talk a loudest side's sound of moment among other two sides.

Consider the clock switch conference circuit of Fig. 8 in more detail below, the information bit of each time slot is temporarily captured by pCM input latch 910 on the P bus 10, after this, just is added on the input port 902 of two-port RAM 901.Two-port RAM 901 comprises delivery outlet 903, and the latter cushions C bus 991 by means of pCM output latch circuit 990.Equally, T bus 770 cushions T bus 995 by means of latch circuit 994.Two-port RAM 901 is with the difference of two-port RAM 701: it has only 16 memory cell, and, lack in order to read the required common address decoding of information that these memory cell are stored.It is decoded that each writes the address, then, be added to 16 at 906 places allow to write in the lead-in wire independently on one; Equally, it is decoded that each reads the address, then, be added to 16 at 907 places allow to read in the lead-in wire independently on one.Arrange the time of the write address after the described decoding by means of allowing to write latch and gating circuit 920.Equally, read the address by means of allowing sensing latch device and gating circuit 970 to be timed after the described decoding.Allow sensing latch device and gating circuit 970 also to comprise EXCLUSIVE OR logical circuit (not shown), the latter is by replying the appearance that the address is read in single decoding allowing comparison signal to be added on the lead-in wire 971.Allow comparison signal to be used to drive the selection function of comparison circuit 993, this comparator circuit 993 only makes multiplexer 992 that T bus 995 bit status are added on the T bus 540 when not allowing comparison signal to occur.Therefore, were it not for reading the address or be added to and allow on sensing latch device and the gating circuit 970 conferencing function not to take place then after the decoding more than the address of reading after the decoding.Two-port RAM 901 responds the adding that allows to write signal on the lead-in wire at 906 places so that the signal condition of described 8 information bits is deposited in the respective memory unit mode.Equally, on going between, add the permission read output signal, and read memory cell in the two-port RAM 901 at 907 places.

Source connected storage 930 comprises about information in each actual time slot of P bus, and therefrom, various information bit states are deposited in the two-port RAM 901.Source connected storage 930 is made of the poke addressable memory (not shown) with 16 memory cell, and each memory cell is corresponding in 16 output leads in 936 places independent one.Source connected storage 930 comprises 11 bit ports, 931,6 bit addresses ports 932 and ten bit compare address ports 933.Each unit associated in digital comparator (not shown) and 16 memory cell is so that compare the address that appears at comparison port 933 separately with the information that is stored in each unit in 16 memory cell.Identical with information in the memory cell when the address of port 933 relatively, and when described memory cell also comprised a significant bit that adds, a corresponding velamen added signal in 16 output leads in 936 places.Write address after the state representation decoding that is added, the latter is sequentially delivered on the two-port RAM 901 via circuit 920, and the latter makes as described above and replying.

Purpose connected storage 980 comprises the information about each actual TDMR time slot on TDM path 11 and 21, can operate this by means of multiplexer 992 and T bus 540 and be stored in information in the two-port RAM 901.The similar of purpose connected storage 980 is in the structure of aforementioned source connected storage 930.The address that occurs at port 983 relatively separately with each unit that is stored in 16 memory cell in information compare.When the information of described relatively port 983 identical with information in the memory cell and, when described memory cell also comprised a significant bit that adds, a corresponding velamen added signal in 16 output leads in 986 places.Allow EXCLUSIVE OR logical circuit in sensing latch device and the gating circuit 970 make 907 corresponding places allow read lead-in wire and be coupled with signal, as previously mentioned, this makes two-port RAM 901 read 8 information bit states from corresponding memory cell.

The information that appears at comparison port 983 is coupled with by channel counter latch circuit 911 from channel counter bus lead-in wire SSC0-4.Described latch circuit 911 also comprises the trigger (not shown), and the latter is timed signal SM2 and SM6 and triggers, thereby, provide every frame 64 addresses, be similar to the relevant situation of foregoing and latch circuit 711.

In digital key telephone system, operate conferencing function by call controller 8, controller 8 is to be similar to the relevant mode of foregoing and connected storage 730, use the time slot of 32 special uses on the P bus 10, by means of data-latching circuit 940 and address latch circuit 950, information is deposited in each memory cell of source connected storage 930 and purpose connected storage 980.Equally, data output end 938, data output latch circuit 912, buffer circuit 913 and the Z-bus of call controller 8 by connecting like that as shown in Figure 8 can be determined the information poke of source connected storage 930.By the data output 988, data output latch circuit 914, buffer circuit 915 and the Z-bus that connect like that as shown in Figure 8, the information stores of destination connected storage 980 also can be used for call controller 8.

Claims (12)

1, a kind of by call controller handle, by means of the line status that the digital signal corresponding port is provided, the digital key telephone system of digital signal communication (DSC) communication between terminals path is provided, this system comprises:

Be connected to time-division multiplex (TDM) transmitted over serial transmission channel of predetermined some described digital signal ports, each that is used for providing some and described digital signal port has fixedly, and the time-division multiplex of pair relationhip sends (TDMT) and reception (TDMR) channel, described TDMT and TDMR channel are present in corresponding transmission and receive in the serial bit stream, and, has fixing slot time, this slot time is used to transmit the fixing many bits that surpass predetermined some m information bits and occurs

First transfer bus that comprises the some bar of m at least parallel signal paths,

Timing device, predetermined TDM frame period and channel that this device is used for regulation TDM serial transmission passage occur, and, being used to be defined in the time slot that equals the integral multiple that described channel occurs during one of described frame period occurs, the timing signal of response from call controller appears in this time slot, and, relevant with a TDM parallel bus

Be connected the circuit handover module between the TDM transmitted over serial transmission channel and first transfer bus,

The system is characterized in that also and comprise:

The module transfer bus that comprises some m bar parallel signal paths,

The translation circuit device, this device is used for the TDMT serial data stream mode that each channel occurs is sent to one of first transfer bus and module transfer bus, and be used in respective channel between the apparition, another the bit status of m bar parallel signal path in described first transfer bus and the module transfer bus is sent in the TDMR serial bit stream

The time switching device shifter, this device is connected between first transfer bus and the module transfer bus, be used to store the bit status from one of first bus and module bus, the latter is the bit status that occurs during the slot time of being stipulated by call controller, the channel that this device also is used to respond by described timing device regulation occurs, and the described bit status that has stored is sent in described each bus another.

2, a kind ofly handled by call controller, by means of the line status that the digital signal corresponding port is provided, provide the digital key telephone system of digital signal communication (DSC) communication between terminals path, this system comprises:

Comprise first transfer bus more than the parallel lead of m bar,

The TDM transmitted over serial transmission channel, this path have at least with described digital signal port in each have one of constant connection to send and receive channel, each bar in the described channel can be sent to quantitatively corresponding some bit status on the described parallel lead

Be connected the circuit handover module between first transfer bus and the TDM transmitted over serial transmission channel,

The system is characterized in that also and comprise:

Timing device, this device are used for regulation TDM frame period and serial channel address, and, be used to stipulate to equal during each TDM frame period the parallel time slot address of the integral multiple that described serial channel address occurs,

The module transfer bus that constitutes by the parallel lead of m bar,

Converting means, this device is used for during predetermined time slot, serial data state from each TDMT channel is sent to each parallel lead of first bus, and is used for that the bit status from the parallel lead of the m bar of module bus is sent to each TDMR channel and occurs

The time switching device shifter, this device reacts to timing device, be used for storing from first bus, appear at by the time slot of call controller regulation and by the bit status on the memory cell of call controller regulation, and the described memory cell that each bit status is entered from responding described serial channel address is sent to module bus.

3, digital key telephone system as defined in claim 2 is characterized in that: described translation circuit comprises:

First, second and the 3rd quadrature memory array,

Described first array is used for the bit status of serial received from every TDMT channel, and, one by one channel ground, sequentially the m bit status is sent to second array, so that parallel being added on the m root lead of first bus, simultaneously, at least 1 bit status that surpasses a described m bit status is added on the lead of correspondence of first bus

Described second array is used for the m bit status is added to first bus, and, just when being added to described m bit status on first bus, the parallel m bit status of accepting from module bus is followed, end at second array, sequentially described bit status is added to corresponding TDMT channel, prepares to be transferred to the digital signal corresponding port, simultaneously, at the other end of this array, be used to first array sequentially to receive the m bit of corresponding TDMT channel;

Described tri-array be used to accept from call controller former, an and predetermined bit status of using for corresponding TDMR channel, and, described bit status was added in the described TDMR channel spacing in the moment of being scheduled to.

4, as digital key telephone system claimed in claim 2, it is characterized in that: the circuit handover module provides connection for two TDM paths, and translation circuit is applicable to every a channel and carries out described TDMT and TDMR serial parallel transformation.

5, also comprise some circuit handover modules as digital key telephone system claimed in claim 2, each module is connected with hardwire monodrome identification code, it is characterized in that: the timing device in each circuit handover module, this device is known sign indicating number to described monodrome and is made a response, thereby related TDM frame has identical phase place; And

The maximum quantity that the described integer that defines described integral multiple is equivalent to be connected to the circuit handover module of first bus adds 1.

6, the method that is used for the control figure key telephone system is characterized in that may further comprise the steps:

A) channel spacing of X order in the frame period of definition of order and each frame period, and, during each channel spacing, receive m information bit and at least one other bit, and, be connected to the digital signal port position of corresponding fixing two channels and be connected between the circuit switching position of fixing X channel at X/2 and transmit m information bit and at least one other bit

B) in Y circuit switching position and related digital signal port position range execution in step a),

C) in each circuit switching position, when the fixing corresponding time slot in XY time slot of every frame period occurs occurred, the bit status that transmits in each channel spacing walked abreast to be added on the corresponding and line lead of first bus,

D) at call controller, read out state, as sequential encoding information relevant with telephone call, that interrelate with transmitting channel, simultaneously from described in addition each bit of first bus, being added to the digital signal port position as the final appropriate other bit status that receives

E) in each circuit switching position, by each time slot of call controller appointment between the apparition, capture m bit status from first bus, and, in the bit status that described m is captured each be stored in by call controller specified, with the X channel in each memory cell that X interrelates

F) with step a) in defined described x channel spacing in proper order synchronously each from x memory cell sequentially read m bit status,

G) reading under first kind of situation of designated memory cell, send signal every in the m bit status, so that the digital signal port unit in association receives, reading under second kind of situation of non-designated memory cell, m the predetermined bit status of the expression bell idles that transmitting channel is interior at interval, so that the digital signal port unit in association receives, simultaneously, under any circumstance send the described other bit status that provides by step d) moment, so that receive in the digital signal port unit of association.

7, the method that is used for control figure key telephone system digital communications path may further comprise the steps:

A) from first transmission medium, sequentially each bit status is sent in each special-purpose time slot of the transmission medium of being worked out by concurrent frame by consecutive frame and the establishment of initial channel,

B) specify in the described time slot at least one, from the time slot of this appointment bit status is deposited in the first memory, the latter has many memory cell, and each memory cell is corresponding to by the possible purpose channel in second transmission medium of consecutive frame and channel establishment; A unit in each memory cell that interrelates in appointment and the described assigned timeslot then, when specified time slot occurs at every turn, deposits described bit status in described designated memory locations,

C) synchronously read each corresponding memory cell with the appearance of the channel of second transmission medium,

D) each bit status when each designated memory locations is read, they are added in the transmission medium of the second parallel establishment, and, also add the bit status that each is predetermined,

E) when each bit status appears in the second parallel transmission medium of working out, capture described each bit status, and, during instantaneous channel, add each bit status of capturing at last serially, whereby by the correspondence of second transmission medium of consecutive frame and channel establishment, in initial channel, information is sent to digital key system, then, from digital key telephone system, deliver to the purpose channel.

8, be used for the digital signal communication path is provided between the number of digital signalling arrangement, and the key telephone system that is used between the communication channel that any described equipment and telephone exchange interrelate, providing communication line, it is characterized in that comprising:

Receive the switching device that (TDMR) interchannel provides communication path practically at time-division multiplex transmission (TDMT) channel and time-division multiplex,

Some time-division multiplexes (TDM) communication path, every TDM communication path comprises n to TDMT and TDMR channel, and they are serial transmission and reception bit stream respectively,

Number of digital signal communication path is used for one of digital signal equipment is connected to described key telephone system separately,

The internal port device that interrelates with one of some TDM communication paths, be used to receive the information of some TDMR channels, then, corresponding information is sent to a fixed corresponding path in the number of digital signal communication path, and, be used to receive information, simultaneously from a path described in the described digital signal communication path, corresponding information is sent to corresponding TDMT channel

External port means, be used to the to be coupled described communication channel that interrelates with described telephone exchange and the information signal of at least one pair of TDMR and TDMT interchannel,

Call controller, this controller reacts to the signal from any digital signal terminal and telephone exchange, is used to handle the call operation of switching device.

9, key telephone system as defined in claim 8, it is characterized in that: the n/2 digital signal communication path of most, via the internal port device separately with fixed TDMT and TDMR channel to interrelating, thereby, during work, can provide independently communication line in each digital signal equipment any one more than one coexistence.

10, key telephone system as defined in claim 8 is characterized in that described switching device shifter comprises:

Be used to provide the parallel bus with synchronous m the bit time slots of the bit frequency of described serial bit stream,

Be used for information is passed to first transfer device of parallel bus from serial bit stream,

Be used for information is passed to from parallel bus second transfer device of serial bit stream.

11, the method that is used for the control figure communication path as defined in claim 7 is characterized in that further comprising the steps of:

F) specify another time slot in described each time slot, from the time slot of this appointment each bit status is deposited in the second memory, the latter has a memory cell at least, and, just store described each bit status therein,

G) specify by a channel in second transmission medium of consecutive frame and channel establishment,

H) moment that specified channel occurs in corresponding to step g) is added to each bit status that is stored in the memory cell of second memory in the medium of the 3rd parallel establishment,

I) according to which has than higher value in the corresponding bits state in the medium that is added to the second and the 3rd parallel establishment, and a kind of in selected described two kinds of mediums, and

In step e), capture described each bit status from selected medium,

Whereby, the information in one of two initial channels is selected, and, from digital key telephone system, delivered in the described purpose channel, so that the function of videoconference is provided on the substation corresponding with the purpose channel.

12, a kind of digital telephone system that communication path is provided between circuit occurs by the call controller manipulation, this system comprises:

Comprise first transfer bus that surpasses the parallel lead of m root,

Have at least one in occurring with some circuits each the TDM transmitted over serial transmission channel of transmission (T) channel and reception (R) channel of constant connection is arranged, each bar in the described channel can send the suitable bit status of quantity to described parallel lead,

Be connected the circuit changing switch between first transfer bus and the TDM transmitted over serial transmission channel, it is characterized in that also comprising:

Timing device, this device are used for regulation TDM frame period and serial channel address, and, be used to stipulate during each TDM frame period, equal the parallel time slot address of integral multiple of the appearance of described serial channel address,

First and second module transfer bus that each free m root lead constitutes,

Converting means, this device is used at predetermined time slot, and the serial data state from every TDMT channel is sent to each parallel lead of first bus, and, being used for that each bit status from the parallel lead of the m root of the arbitrary bus of each module bus is sent to each TDMR channel occurs

Very first time switching device shifter, this device is made a response to timing device, be used for each bit status that appears at time slot in first transfer bus by the call controller regulation, store in the memory cell corresponding to the TDMR channel of stipulating by call controller, and be used for bit status is sent to first module bus from the described memory cell by described serial channel address regulation

The second time switching device shifter, this device is made a response to timing device, be used for each bit status that appears at time slot in first transfer bus by the call controller regulation, store corresponding in the memory cell by the call controller regulation, and, be used for come free call controller appointment, with one of described memory cell that interrelates of described serial channel address in bit status, be sent to second module bus

Choice device, this device is made a response to the value of the bit status that occurs simultaneously on first and second module bus, be used for the manipulated device, so that only transmit bit status from one of first and second module bus, thereby, in the contactor module, be provided at described circuit occur in the conference communication ability of any three party.

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