CN103391090A - Circuit capable of recognizing three states of input signals - Google Patents
Circuit capable of recognizing three states of input signals Download PDFInfo
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- CN103391090A CN103391090A CN201310302278XA CN201310302278A CN103391090A CN 103391090 A CN103391090 A CN 103391090A CN 201310302278X A CN201310302278X A CN 201310302278XA CN 201310302278 A CN201310302278 A CN 201310302278A CN 103391090 A CN103391090 A CN 103391090A
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Abstract
The invention discloses a circuit capable of recognizing three states of input signals. The circuit is provided with the high frequency sampling signal input end, the signal input end, a first switch, a second switch, a first triode and a second triode. The first switch is used for high-level input, and the second switch is used for low-level input. The circuit can recognize the three states, hardware circuits for recognizing the high-level input and the low-level input respectively are not required to be designed, input ports can be reused, and duration for occupying system resources is shortened.
Description
Technical field
The present invention relates to the circuit recognition technology, relate in particular to a kind of circuit of realizing three kinds of state recognitions of input signal.
Background technology
At present, most circuit can only be realized the identification of two kinds of signals, be high level and low level state, for the third state-vacant state, generally to realize identification, be generally a kind of overlapping with in vacant state and high level or low level, think a kind of state, as only to the circuit shown in the effective Fig. 1 a of high level input with only to the circuit shown in the effective Fig. 1 b of low level input.
The existing technical problem of above-mentioned technology is: 1) circuit can not be identified three kinds of states; 2) must design respectively identification high level and the effective hardware circuit of low level input; 3) input port can not be multiplexing, and occupying system resources is more.
Summary of the invention
In view of this, the present invention proposes a kind of circuit of realizing three kinds of state recognitions of input signal, the problem of can not identify three kinds of states to solve in prior art, must design respectively identification high level and the effective hardware circuit of low level input, input port can not be multiplexing, occupying system resources is more.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of circuit of realizing three kinds of state recognitions of input signal, wherein, have high frequency sampled signal input and signal input part, the first switch, second switch, the first triode and the second triode, described the first switch is used for providing the high level input switch, and described second switch is used for providing the low level input switch;
Described the first triode has the first electrode, the second electrode and third electrode, described the second triode has the 4th electrode, the 5th electrode and the 6th electrode, after obtaining the input signal of described high frequency sampled signal input by described the first electrode, export described the 6th electrode grounding by described the 5th electrode after described the second electrode, described the 4th electrode; Described signal input part connects described the 4th electrode;
Drawing voltage on the high level voltage that described the first switch is controlled and the described third electrode of described the first triode is same voltage.
The above-mentioned circuit of realizing three kinds of state recognitions of input signal, wherein, described the first triode is the positive-negative-positive triode, described the second triode is NPN type triode.
The above-mentioned circuit of realizing three kinds of state recognitions of input signal, wherein, the signal frequency of described high frequency sampled signal input input is higher than 5 times of the signal frequency of described signal input part.
The above-mentioned circuit of realizing three kinds of state recognitions of input signal, wherein, when described signal input part is high level, described output output low level; When described signal input part is low level, described output output high level; When described signal input part is vacant state, described output output sampling clock, the frequency of described sampling clock is 5 times～10 times of the high level voltage frequency controlled of described the first switch.
The above-mentioned circuit of realizing three kinds of state recognitions of input signal, wherein, described the first switch is closed, when described second switch is opened, is high level or vacant state; Described the first switch opens, when described second switch is closed, be low level or vacant state; When described the first switch and described second switch are all opened, be vacant state.
With respect to prior art, the present invention has following advantage:
Can identify three kinds of states, need not to design respectively identification high level and the effective hardware circuit of low level input again, input port can be multiplexing, shortened the duration of occupying system resources.
Description of drawings
The accompanying drawing that forms a part of the present invention is used to provide a further understanding of the present invention, and illustrative examples of the present invention and explanation thereof are used for explaining the present invention, do not form improper restriction of the present invention.In the accompanying drawings:
Fig. 1 a is only to the effective circuit diagram of high level input in prior art;
Fig. 1 b is only to the effective circuit diagram of low level input in prior art;
Fig. 2 is the circuit structure diagram that the present invention realizes the circuit embodiments of three kinds of state recognitions of input signal;
Fig. 3 a is the oscillogram that the present invention realizes the input signal that the first switch of the circuit embodiments of three kinds of state recognitions of input signal is controlled;
Fig. 3 b is the oscillogram that the present invention realizes the input signal that the second switch of the circuit embodiments of three kinds of state recognitions of input signal is controlled;
Fig. 3 c is the oscillogram of the output signal of the present invention's circuit embodiments of realizing three kinds of state recognitions of input signal;
Fig. 3 d is the waveform schematic diagram of the output sampling clock of the present invention's circuit embodiments of realizing three kinds of state recognitions of input signal.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills, not making under the creative work prerequisite the every other embodiment that obtains, belong to the scope of protection of the invention.
Need to prove, in the situation that do not conflict, embodiment and the feature in embodiment in the present invention can make up mutually.
Basic thought of the present invention is: a kind of circuit that can support three kinds of state recognitions is provided, need not to design respectively identification high level and the effective hardware circuit of low level input, input port can be multiplexing, shortens the duration of occupying system resources.
Below in conjunction with accompanying drawing, each preferred embodiment of the present invention is described further:
With reference to Fig. 2, the present invention realizes the circuit of three kinds of state recognitions of input signal, have high frequency sampled signal input SAMP_CLK and signal input part IN, the first interrupteur SW 4, second switch SW3, the first triode Q4 and the second triode Q3, the first interrupteur SW 4 is used for providing the high level input switch, and second switch SW3 is used for providing the low level input switch.
The first triode Q4 has the first electrode, the second electrode and third electrode, and in a preferred embodiment of the invention, the first triode Q4 is positive-negative-positive, and the first electrode is base stage b, and the second electrode is collector electrode c, and third electrode is emitter e.The second triode Q3 is the NPN type, has the 4th electrode, the 5th electrode and the 6th electrode, and preferably, the 4th electrode is base stage b, and the 5th electrode is collector electrode c, and the 6th electrode is emitter e.Obtain the input signal of high frequency sampled signal input SAMP_CLK by the first electrode b after, export by the 5th electrode c after the second electrode c, the 4th electrode b, the 6th electrode e ground connection, signal input part IN meets the 4th electrode b.With reference to Fig. 2, connect by resistance between each triode, R8 by 20K between the c utmost point of the first triode Q4 and input IN is connected, R7 by 20K between the b utmost point of input IN and the second triode Q3 is connected, the second triode Q3 has the pull-up resistor R9 of 20K, in addition, the R10 that has 2K between high frequency sampled signal input SAMP_CLK and the first triode Q4.Certainly, above-mentioned resistance value size is not limited to the numerical value of enumerating.
Drawing voltage VDD on the high level voltage VDD that the first interrupteur SW 4 is controlled and the third electrode of the first triode Q4 is same voltage, this key point 1 for indicating in figure.
The signal frequency of high frequency sampled signal input SAMP_CLK input is higher than 5 times of the signal frequency of signal input part, and the signal frequency of SAMP_CLK input is larger, and the resolution of circuit is just higher, this key point 2 for indicating in figure.
The first interrupteur SW 4 closures, when second switch SW3 opened, signal input IN was high level or vacant state; The first interrupteur SW 4 is opened, and when second switch SW3 was closed, signal input IN was low level or vacant state; When the first interrupteur SW 4 and second switch SW3 all open, it is vacant state.With reference to Fig. 3 a, Fig. 3 b and Fig. 3 c, when signal input part is high level, output OUT output low level signal; When signal input part IN was low level, output OUT exported high level; When signal input part IN is vacant state, output OUT exports sampling clock, the frequency of sampling clock is 5 times～10 times of the high level voltage frequency controlled of the first switch, and such as the frequency of the input voltage of SW4 is 100Hz, the frequency of sampling clock is 500Hz～1000Hz.
The frequency of sampling clock is random predetermined, and its waveform is with reference to shown in Fig. 3 d.According to or the door theory, during signal intensity, sampling pulse can be clamped by signal, in addition,, according to frequency and the state of composite signal, can judge the state of signal.
If regard circuit of the present invention as an input data processing module, the output signal after the notebook data processing module is processed can be used as the input signal of other programming modules.
In sum, the present invention is transformed to discontinuous high-frequency signal with continuous signal, can identify high level, low level and unsettled three kinds of states, need not to design respectively again identification high level and the effective hardware circuit of low level input, input port can be multiplexing, shortened the duration of occupying system resources.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (5)
1. circuit of realizing three kinds of state recognitions of input signal, it is characterized in that, have high frequency sampled signal input (SAMP_CLK) and signal input part (IN), the first switch (SW4), second switch (SW3), the first triode (Q4) and the second triode (Q3), described the first switch (SW4) is used for providing the high level input switch, and described second switch (SW3) is used for providing the low level input switch;
Described the first triode (Q4) has the first electrode, the second electrode and third electrode, described the second triode (Q3) has the 4th electrode, the 5th electrode and the 6th electrode, after obtaining the input signal of described high frequency sampled signal input by described the first electrode, export described the 6th electrode grounding by described the 5th electrode after described the second electrode, described the 4th electrode; Described signal input part connects described the 4th electrode;
Drawing voltage on the described third electrode of the high level voltage that described the first switch (SW4) is controlled and described the first triode (Q4) is same voltage.
2. realize according to claim 1 the circuit of three kinds of state recognitions of input signal, it is characterized in that, described the first triode (Q4) is the positive-negative-positive triode, and described the second triode (Q3) is NPN type triode.
3. realize according to claim 1 the circuit of three kinds of state recognitions of input signal, it is characterized in that, the signal frequency of described high frequency sampled signal input (SAMP_CLK) input is higher than described signal input part (SW4; SW3) 5 times of signal frequency.
4. realize according to claim 3 the circuit of three kinds of state recognitions of input signal, it is characterized in that, described signal input part (SW4; While SW3) being high level, described output (OUT) output low level; Described signal input part (SW4; While SW3) being low level, described output (OUT) output high level; Described signal input part (SW4; While SW3) being vacant state, described output (OUT) output sampling clock, the frequency of described sampling clock is 5 times～10 times of the high level voltage frequency controlled of described the first switch (SW4).
5. realize according to claim 4 the circuit of three kinds of state recognitions of input signal, it is characterized in that, described the first switch (SW4) closure, described second switch (SW3) while opening, is high level or vacant state; Described the first switch (SW4) is opened, and when described second switch (SW3) is closed, is low level or vacant state; Described the first switch (SW4) and described second switch (SW3) while all opening, are vacant state.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310302278.XA CN103391090B (en) | 2013-07-15 | 2013-07-15 | A kind of circuit of realizing three kinds of state recognitions of input signal |
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| CN201310302278.XA CN103391090B (en) | 2013-07-15 | 2013-07-15 | A kind of circuit of realizing three kinds of state recognitions of input signal |
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| CN103391090A true CN103391090A (en) | 2013-11-13 |
| CN103391090B CN103391090B (en) | 2016-05-11 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104808561A (en) * | 2015-04-25 | 2015-07-29 | 航天科技控股集团股份有限公司 | Multi-state switch state collection device and method |
| CN108733587A (en) * | 2017-04-20 | 2018-11-02 | 中兴通讯股份有限公司 | Sub- equipment localization method and system |
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| JP3159247B2 (en) * | 1997-09-29 | 2001-04-23 | 日本電気株式会社 | Input circuit |
| CN2842887Y (en) * | 2005-05-23 | 2006-11-29 | 海尔集团公司 | Multi plexing communication interface circuit |
| US20080074148A1 (en) * | 2006-08-23 | 2008-03-27 | Stmicroelectronics Pvt. Ltd. | High speed level shifter |
| CN102201807A (en) * | 2011-04-11 | 2011-09-28 | 长沙景嘉微电子有限公司 | Simple tristate input circuit |
| CN202093346U (en) * | 2011-05-30 | 2011-12-28 | 深圳市博巨兴实业发展有限公司 | Status selection circuit for IO (input/output) port of single-chip microcomputer |
| CN102931971A (en) * | 2012-11-07 | 2013-02-13 | 长沙景嘉微电子股份有限公司 | Three-state control signal input/output (IO) circuit |
| CN202872406U (en) * | 2012-09-19 | 2013-04-10 | 青岛海信移动通信技术股份有限公司 | Interface multiplexing circuit and mobile terminal |
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2013
- 2013-07-15 CN CN201310302278.XA patent/CN103391090B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3159247B2 (en) * | 1997-09-29 | 2001-04-23 | 日本電気株式会社 | Input circuit |
| CN1103140C (en) * | 1997-09-29 | 2003-03-12 | 日本电气株式会社 | Input circuit |
| CN2842887Y (en) * | 2005-05-23 | 2006-11-29 | 海尔集团公司 | Multi plexing communication interface circuit |
| US20080074148A1 (en) * | 2006-08-23 | 2008-03-27 | Stmicroelectronics Pvt. Ltd. | High speed level shifter |
| CN102201807A (en) * | 2011-04-11 | 2011-09-28 | 长沙景嘉微电子有限公司 | Simple tristate input circuit |
| CN202093346U (en) * | 2011-05-30 | 2011-12-28 | 深圳市博巨兴实业发展有限公司 | Status selection circuit for IO (input/output) port of single-chip microcomputer |
| CN202872406U (en) * | 2012-09-19 | 2013-04-10 | 青岛海信移动通信技术股份有限公司 | Interface multiplexing circuit and mobile terminal |
| CN102931971A (en) * | 2012-11-07 | 2013-02-13 | 长沙景嘉微电子股份有限公司 | Three-state control signal input/output (IO) circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104808561A (en) * | 2015-04-25 | 2015-07-29 | 航天科技控股集团股份有限公司 | Multi-state switch state collection device and method |
| CN104808561B (en) * | 2015-04-25 | 2017-06-20 | 航天科技控股集团股份有限公司 | Multistate switch state collecting device and method |
| CN108733587A (en) * | 2017-04-20 | 2018-11-02 | 中兴通讯股份有限公司 | Sub- equipment localization method and system |
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| CN103391090B (en) | 2016-05-11 |
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