CN103390548A - Method for preparing gate silicon oxide layers and method for processing semiconductor substrate - Google Patents
Method for preparing gate silicon oxide layers and method for processing semiconductor substrate Download PDFInfo
- Publication number
- CN103390548A CN103390548A CN2012101434668A CN201210143466A CN103390548A CN 103390548 A CN103390548 A CN 103390548A CN 2012101434668 A CN2012101434668 A CN 2012101434668A CN 201210143466 A CN201210143466 A CN 201210143466A CN 103390548 A CN103390548 A CN 103390548A
- Authority
- CN
- China
- Prior art keywords
- voltage device
- silicon oxide
- semiconductor substrate
- high voltage
- oxide layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 112
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 title claims abstract description 88
- 229910052814 silicon oxide Inorganic materials 0.000 title claims abstract description 88
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000000034 method Methods 0.000 title abstract description 43
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 150
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 78
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 72
- 239000010703 silicon Substances 0.000 claims abstract description 72
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 63
- 230000012010 growth Effects 0.000 claims abstract description 50
- 238000002347 injection Methods 0.000 claims abstract description 41
- 239000007924 injection Substances 0.000 claims abstract description 41
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims abstract description 39
- 230000003647 oxidation Effects 0.000 claims abstract description 39
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 39
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 21
- -1 Nitrogen ions Chemical class 0.000 claims abstract description 18
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 17
- 238000000137 annealing Methods 0.000 claims abstract description 15
- 238000002513 implantation Methods 0.000 claims description 51
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 30
- 229910052760 oxygen Inorganic materials 0.000 claims description 30
- 239000001301 oxygen Substances 0.000 claims description 30
- 238000002360 preparation method Methods 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 12
- 238000003672 processing method Methods 0.000 claims description 12
- 238000002955 isolation Methods 0.000 claims description 9
- 229910052731 fluorine Inorganic materials 0.000 abstract description 32
- 239000011737 fluorine Substances 0.000 abstract description 32
- 229910052796 boron Inorganic materials 0.000 abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 9
- 230000035515 penetration Effects 0.000 abstract description 9
- 238000001953 recrystallisation Methods 0.000 abstract description 7
- 238000009826 distribution Methods 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 31
- 238000005516 engineering process Methods 0.000 description 12
- 238000005468 ion implantation Methods 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 10
- 230000002708 enhancing effect Effects 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 230000005465 channeling Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 230000009977 dual effect Effects 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- YPDSOAPSWYHANB-UHFFFAOYSA-N [N].[F] Chemical compound [N].[F] YPDSOAPSWYHANB-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002829 nitrogen Chemical class 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910008065 Si-SiO Inorganic materials 0.000 description 1
- 229910006405 Si—SiO Inorganic materials 0.000 description 1
- 150000001638 boron Chemical class 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a method for preparing gate silicon oxide layers and a method for processing a semiconductor substrate. Nitrogen ions are injected into a low-pressure device area in advance and fluorine ions are injected in a high-pressure device area in advance, so that when the gate silicon oxide layers grow on the surface of the thermal oxidation semiconductor substrate, growth of the gate silicon oxide layers in the low-pressure device area is restrained, growth of the gate silicon oxide layers in the high-pressure device area is promoted, therefore, the gate silicon oxide layers with different thicknesses are formed, and the technological process is greatly simplified; further germanium and/or silicon is injected into the semiconductor substrate in a pre-non-crystallizing mode, and the channel carrier mobility is improved; in the annealing recrystallization process after non-crystallizing injection and nitrogen and fluoride ion injection, the characteristics of the surface of the silicon substrate are optimized, and the method is beneficial to improving the reliability of the gate oxide layers. The fabrication processing enables the peak value of the nitrogen concentration distribution of the low-pressure device area to be close to the surfaces of the gate silicon oxide layers, the follow-up boron penetration from P+ polycrystalline silicon can be effectively blocked, and the reliability of the thin gate silicon oxide layers in the low-pressure device area can be enhanced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of preparation method and Semiconductor substrate processing method of grid silicon oxide layer.
Background technology
Along with microelectronic industry, the develop rapidly of very lagre scale integrated circuit (VLSIC) (ULSI), Dual Gate Oxide technique (Dual Gate Oxide, DGO) high tension apparatus and low-voltage device are integrated on same chip, be the key process technology in producing process of deep submicron integrated circuit, directly affect and determined electrology characteristic and the reliability of device.Its need to grow simultaneously on same chip grid silicon oxide layer of two kinds of thickness, with the transistor of preparation work in different voltages.
As shown in Figure 1, in prior art, CMOS high voltage integrated circuit (High-Voltage Integrated Circuits with the standard CMOS process compatibility, HVIC) in, partly produce control signal by low voltage logic and control high-pressure section work, its output rises to a level high by the high-voltage driving circuit that comprises high tension apparatus.So CMOS manufacturing technology of high voltage integrated circuit, general high voltage device regions II, the III that isolates at the device isolation structure 101 of substrate 100 makes high pressure NMOS and the PMOS device that is used for realizing input/output operations, at core devices (Core device) the district I that device isolation structure 101 isolates, makes for the low voltage CMOS device of realizing the logic control high-pressure section.Because the grid source of high voltage PMOS need to be worked under the high pressure of 100V left and right, thereby high voltage PMOS device need adopt thick grid oxygen technique (as shown in Fig. 1 104) to realize that high grid source is withstand voltage.And low voltage CMOS device and high pressure NMOS can adopt thin grid oxygen technique (as shown in Fig. 1 102,103) to realize.And require to contain a small amount of nitrogen element in wherein thin-grid silicon oxide layer 102, to stop the boron penetration (B penetration) from the P+ polycrystalline and to improve Si-SiO between substrate silicon and grid silicon oxide layer
2Interfacial characteristics, the reliability of enhancing thin-grid silicon oxide layer 102.
In order to achieve the above object, nitrogen element in thin-grid silicon oxide layer distributes and wishes to meet following the requirement: the peak value that the nitrogen concentration of element distributes is near grid silicon oxide layer surface (being the interface of polysilicon and grid oxide layer), and the atom content of 1%-3% is arranged, can effectively stop like this boron penetration from the P+ polycrystalline; On the other hand, the interface between grid oxide layer and substrate silicon only needs a small amount of nitrogen element, both can improve the interfacial characteristics between substrate silicon and grid oxide layer, strengthens the reliability of thin-grid silicon oxide layer, can not affect again the mobility of charge carrier in following raceway groove.But in present technique, the peak value that the nitrogen concentration of element distributes is always at the interface near between grid silicon oxide layer and substrate silicon, rather than the ideal distribution of foregoing description, and such distribution can reduce the mobility of charge carrier in raceway groove.yet, the Dual Gate Oxide technique of commonly using now, all generally Mr. voltage device region II that grows tall, after the thick gate oxidation silicon 104 and the first thin oxide gate silicon 103 of III, the thickness of second thin oxide gate silicon 102(the second thin oxide gate silicon 102 of regrowth low-voltage device district I is relatively minimum, the thickness of the first thin oxide gate silicon 103 is placed in the middle, the thickness of thick gate oxidation silicon 104 is relatively maximum), and then the second thin oxide gate silicon 102 is carried out nitrogen treatment, thereby make thick, nitrogen concentration of element distribution peak value in thin two kinds of gate oxidation silicon is all in close silicon face one side, have a strong impact on thick, the mobility of two kinds of transistorized channel carriers of thin grid, this Dual Gate Oxide technique of while, repeatedly thermal oxidation technology and repeatedly wet etching or Self-aligned etching technique, make technique very complicated usually.
Summary of the invention
The object of the present invention is to provide a kind of preparation method and Semiconductor substrate processing method of grid silicon oxide layer, can be by thermal oxidation technology and on a chip grid silicon oxide layer of a plurality of different-thickness of growth, technique is simple.
In order to address the above problem, the invention provides a kind of preparation method of grid silicon oxide layer, comprise the following steps:
Semiconductor substrate with low-voltage device district and high voltage device regions is provided;
Semiconductor substrate surface in described low-voltage device district carries out the nitrogen Implantation, carries out fluorine ion at the semiconductor substrate surface of described high voltage device regions and injects;
The described semiconductor substrate surface of thermal oxidation is with the growth grid silicon oxide layer, and described high voltage device regions is thicker than the grid silicon oxide layer in low-voltage device district.
Further, before described nitrogen Implantation and fluorine ion inject, the semiconductor substrate surface of described low-voltage device district and high voltage device regions is carried out germanium and/or the pre-amorphous injection of silicon ion.
Further, the energy of described pre-amorphous injection is 10KeV ~ 50KeV, and dosage is 1E14/cm
2~ 1.5E15/cm
2, angle is 2 ~ 30 °.
Further, the energy of described nitrogen Implantation is 0.2KeV ~ 3KeV, and dosage is 1E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
Further, the energy that described fluorine ion injects is 0.2KeV ~ 10KeV, and dosage is 1E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
Further, described high voltage device regions comprises the first high voltage device regions and the second high voltage device regions, and described the second high voltage device regions is larger than the dosage that the fluorine ion of the first high voltage device regions injects so that the grid silicon oxide layer that thermal oxidation forms in the second high voltage device regions thick than in the first high voltage device regions.
Further, the energy that the fluorine ion of described the first high voltage device regions injects is 0.2KeV ~ 5KeV, and dosage is 1E14/cm
2~ 1.5E15/cm
2, angle is 2 ~ 30 °; The energy that the fluorine ion of described the second high voltage device regions injects is 1KeV ~ 10KeV, and dosage is 3E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
Further, provide the step of the Semiconductor substrate with low-voltage device district and high voltage device regions to comprise:
Silicon substrate is provided, forms device isolation structure in described silicon substrate, to keep apart low-voltage device district and high voltage device regions;
Form pad oxide on described silicon substrate;
Carry out trap Implantation and annealing in described silicon substrate;
The described pad oxide of etching, to expose the channel region of low-voltage device district and high voltage device regions.
Further, described nitrogen Implantation and fluorine ion carry out before or after being infused in the described pad oxide of etching.
Further, the technical recipe of described thermal oxidation comprises dried oxygen and wet oxygen growth, and the technological parameter of described dried oxide growth comprises: oxygen flow is 0.3L/min ~ 1.5L/min, and nitrogen flow is 1L/min ~ 20L/min, air pressure is 0.5atm ~ 1.5atm, temperature 700 ~ 800oC; The technological parameter of described wet oxygen growth: the steam flow is 0.1L/min ~ 1L/min, and nitrogen flow is 1L/min ~ 20L/min, and air pressure is 0.5atm ~ 1.5atm, 700 ~ 800 ° of C of temperature.
The present invention also provides a kind of Semiconductor substrate processing method, comprises the following steps:
Semiconductor substrate is provided, and described Semiconductor substrate comprises a plurality of subregions;
The nitrogen Implantation is carried out on a subregion surface in described Semiconductor substrate, carries out fluorine ion on another subregion surface of described Semiconductor substrate and injects;
The described semiconductor substrate surface of thermal oxidation is with the growth oxide layer, and the subregion that described fluorine ion injects is than the oxidation bed thickness of the subregion of described nitrogen Implantation.
Further, before described nitrogen Implantation and fluorine ion injection, described semiconductor substrate surface is carried out germanium and/or the pre-amorphous injection of silicon ion.
Further, the energy of described pre-amorphous injection is 10KeV ~ 50KeV, and dosage is 1E14/cm
2~ 1.5E15/cm
2, angle is 2 ~ 30 °.
Further, the energy of described nitrogen Implantation is 0.2KeV ~ 3KeV, and dosage is 1E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
Further, the energy that described fluorine ion injects is 0.2KeV ~ 10KeV, and dosage is 1E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
Further, the technical recipe of described thermal oxidation comprises dried oxygen and wet oxygen growth, and the technological parameter of described dried oxide growth comprises: oxygen flow is 0.3L/min ~ 1.5L/min, and nitrogen flow is 1L/min ~ 20L/min, air pressure is 0.5atm ~ 1.5atm, temperature 700 ~ 800oC; The technological parameter of described wet oxygen growth: the steam flow is 0.1L/min ~ 1L/min, and nitrogen flow is 1L/min ~ 20L/min, and air pressure is 0.5atm ~ 1.5atm, 700 ~ 800 ° of C of temperature.
Compared with prior art, the preparation of grid silicon oxide layer provided by the invention and Semiconductor substrate processing method, inject fluorine ion at low-voltage device district injecting nitrogen ion and in high voltage device regions in advance, make when thermal oxidation semiconductor substrate surface growth oxide layer, the growth of the oxide layer in low-voltage device district is inhibited, the growth of the oxide layer of high voltage device regions is promoted, and then can form the oxide layer of different-thickness in a thermal oxide growth technique, has greatly simplified technological process; Further, the pre-amorphous injection of germanium and/or silicon in Semiconductor substrate, the channeling effect of reduction Implantation, reduce the diffusion of follow-up ion, improved the channel carrier mobility; And the annealing recrystallization process after decrystallized injection and fluorine, nitrogen Implantation, the surface of silicon characteristic can be optimized, and the reliability that is conducive to oxide layer subsequently improves; And the peak value that this PROCESS FOR TREATMENT makes low-voltage device district nitrogen concentration profile can effectively stop follow-up boron penetration from the P+ polysilicon near the grid silicon oxide layer surface, the reliability of enhancing low-voltage device district thin-grid silicon oxide layer.
Description of drawings
Fig. 1 is the sectional structure chart of the CMOS high voltage integrated circuit structure of a kind of of prior art and standard CMOS process compatibility;
Fig. 2 is preparation method's flow chart of the grid silicon oxide layer of the embodiment of the present invention one;
Fig. 3 A ~ 3C is the device architecture cutaway view in the preparation process of grid silicon oxide layer of the embodiment of the present invention one;
Fig. 4 is preparation method's flow chart of the grid silicon oxide layer of the embodiment of the present invention two;
Fig. 5 A ~ 5C is the device architecture cutaway view in the preparation process of grid silicon oxide layer of the embodiment of the present invention two;
Fig. 6 is the variation schematic diagram of silicon oxide layer thickness with nitrogen ion implantation dosage and fluorine ion implantation dosage;
Fig. 7 is the Semiconductor substrate process flow figure of the embodiment of the present invention three.
Embodiment
Preparation method to the grid silicon oxide layer of the present invention's proposition is described in further detail below in conjunction with the drawings and specific embodiments.
Embodiment one
As shown in Figure 2, this enforcement provides a kind of preparation method of grid silicon oxide layer, comprises the following steps:
S21, provide silicon substrate, forms device isolation structure in described silicon substrate, to keep apart low-voltage device district and high voltage device regions;
S22, form pad oxide on described silicon substrate;
S23, carry out trap Implantation and annealing in described silicon substrate;
S24, the described pad oxide of etching, to expose the channel region of low-voltage device district and high voltage device regions;
S25, carry out the pre-amorphous injection of germanium ion to the semiconductor substrate surface of described low-voltage device district and high voltage device regions;
S26, the semiconductor substrate surface in described low-voltage device district carries out the nitrogen Implantation, carries out fluorine ion at the semiconductor substrate surface of described high voltage device regions and injects;
S27, the described semiconductor substrate surface of thermal oxidation is with the growth grid silicon oxide layer, and described high voltage device regions is thicker than the grid silicon oxide layer in low-voltage device district.
Please refer to Fig. 3 A, in step S21, the silicon substrate 300 that provides can be the pure silicon substrate, it can be also germanium silicon (SiGe) substrate, can also be silicon-on-insulator substrate, then etch silicon substrate 300 forms shallow trench, and fill oxide in the shallow trench after etching, form fleet plough groove isolation structure (STI) 301, by STI 301, isolate low-voltage device district I, the first high voltage device regions II and the second high voltage device regions III.
Please continue the 3A with reference to figure, in step S22, by techniques such as ald, plasma enhanced chemical vapor deposition and physical vapor depositions, form pad oxide 302 on described silicon substrate 300.Described pad oxide 302 provides buffering for the hard mask layer that forms before follow-up Implantation, can also be as the stop-layer in follow-up removal hard mask layer step.
Please continue the 3A with reference to figure, in step S23, first form the hard mask layer of well region Implantation on pad oxide 302, then carry out boron and inject to form P well region (not shown) in described silicon substrate 300, and carry out arsenic or phosphorus injection N well region (not shown); Then remove the hard mask layer of the well region Implantation that forms.
Please continue the 3A with reference to figure, in step S24, the described pad oxide 302 of etching, to expose low-voltage device district I, the first high voltage device regions II and the second high voltage device regions III, that is, only keep the pad oxide 302 on STI 301.
Please continue the 3A with reference to figure, in step S25, form pre-amorphous injection hard mask layer on pad oxide 302, then take the pre-amorphous injection hard mask layer that forms as mask, carry out germanium (Ge) or the pre-amorphous injection of silicon ion on silicon substrate 300 surfaces that expose low-voltage device district I, the first high voltage device regions II and the second high voltage device regions III, and carry out annealing, make the silicon on silicon substrate 300 surfaces become noncrystalline state by monocrystalline state.Before follow-up Implantation, the germanium that injects or silicon ion make silicon substrate 300 surfaces pre-amorphous, can reduce the channeling effect of follow-up Implantation, reduce Impurity Diffusion, therefore pre-amorphous injection can realize shallow junction and precipitous Impurity Distribution, and can improve impurity activation by the annealing process after pre-amorphous Implantation; Then remove the pre-amorphous injection hard mask layer that forms.
Preferably, the energy of the pre-amorphous injection of described germanium ion is 10KeV ~ 50KeV, and dosage is 1E14/cm
2~ 1.5E15/cm
2, angle is 2 ~ 30 °.
Please refer to Fig. 3 B, in step S26, form nitrogen and inject the hard mask layer (not shown) on pad oxide 302, this nitrogen injects hard mask layer and exposes the channel region of low-voltage device district I, then inject hard mask layer as mask take the nitrogen that forms, at the channel region that exposes low-voltage device district I, inject the nitrogen plasma; Then, remove the nitrogen that forms and inject hard mask layer; Then, form the first fluorine and inject the hard mask layer (not shown) on pad oxide 302, this first fluorine injects hard mask layer and exposes the channel region of the first high voltage device regions II, then inject hard mask layer as mask take the first fluorine that forms, at the channel region that exposes the first high voltage device regions II, inject the fluorine plasma; Then, remove the first fluorine that forms and inject hard mask layer; Then, form the second fluorine and inject the hard mask layer (not shown) on pad oxide 302, this second fluorine injects hard mask layer and exposes the channel region of the second high voltage device regions III, then inject hard mask layer as mask take the second fluorine that forms,, with the fluorine ion implantation dosage larger than the first high voltage device regions, at the channel region that exposes the second high voltage device regions III, inject the fluorine plasma; Then, remove the second fluorine that forms and inject hard mask layer.The fluorine of the pre-amorphous injection of germanium in step S25 and/or silicon and step S26, the annealing recrystallization process after the nitrogen Implantation, the substrate surface characteristic can be optimized, and the reliability that is conducive to gate oxide subsequently improves; And the peak value that this PROCESS FOR TREATMENT makes low-voltage device district nitrogen concentration profile can effectively stop follow-up boron penetration from the P+ polysilicon near the grid silicon oxide layer surface, the reliability of enhancing low-voltage device district thin-grid silicon oxide layer.
Please refer to Fig. 3 C, in step S27, thickness requirement according to the gate oxide of low-voltage device and high tension apparatus, set corresponding thermal oxidation technology formula (gate oxide recipe), according to this technical recipe thermal oxidation silicon substrate surface, and then grow the grid silicon oxide layer of low-voltage device district I, the first high voltage device regions II and the second high voltage device regions III.
Need to prove, as shown in Figure 6, find after tested, in the situation that other technological parameters are identical, for example the nitrogen Implantation Energy is that 0.7KeV or fluorine inject 1KeV, the thickness of thermal oxidation silicon substrate growing silicon oxide layer reduces with the increase of nitrogen (N) ion implantation dosage, increase with fluorine (F) ion implantation dosage increases, and the thermal oxidation technology parameter of adjusting nitrogen (N) ion implantation dosage, fluorine (F) ion implantation dosage and corresponding Controlling Growth Rate just can be adjusted the device grid silicon oxide layer thickness of thermal oxide growth.Therefore.Please refer to Fig. 3 C, by the thermal oxidation technology formula set can so that the thickness of the grid silicon oxide layer 304 of low-voltage device district I less than the thickness of the grid silicon oxide layer 305 of the first high voltage device regions II, the thickness of the grid silicon oxide layer 305 of the first high voltage device regions II is less than the thickness of the grid silicon oxide layer 306 of the second high voltage device regions III.
Preferably, the energy of described nitrogen Implantation is 0.2KeV ~ 3KeV, and dosage is 1E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
Preferably, the energy that the fluorine ion of described the first high voltage device regions injects is 0.2KeV ~ 5KeV, and dosage is 1E14/cm
2~ 1.5E15/cm
2, angle is 2 ~ 30 °; The energy that the fluorine ion of described the second high voltage device regions injects is 1KeV ~ 10KeV, and dosage is 3E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
Preferably, the technical recipe of described thermal oxidation comprises dried oxygen and wet oxygen growth, and the technological parameter of described dried oxide growth comprises: oxygen flow is 0.3L/min ~ 1.5L/min, and nitrogen flow is 1L/min ~ 20L/min, air pressure is 0.5atm ~ 1.5atm, temperature 700 ~ 800oC; The technological parameter of described wet oxygen growth: the steam flow is 0.1L/min ~ 1L/min, and nitrogen flow is 1L/min ~ 20L/min, and air pressure is 0.5atm ~ 1.5atm, 700 ~ 800 ° of C of temperature.
In the successive process of CMOS integrated circuit, can carry out polysilicon deposition, then etch polysilicon and grid silicon oxide layer 304,305,306 on the device architecture that step S27 forms, to form the stacked gate architectures of low-voltage device district I, the first high voltage device regions II and the second high voltage device regions III.
The preparation method of the grid silicon oxide layer that provides of the present embodiment, the pre-amorphous injection of germanium and/or silicon in Semiconductor substrate, then at low-voltage device district injecting nitrogen ion and in high voltage device regions, inject fluorine ion, make when thermal oxidation semiconductor substrate surface growth grid silicon oxide layer, the growth of the grid silicon oxide layer in low-voltage device district is inhibited, the growth of the grid silicon oxide layer of high voltage device regions is promoted, and then can form the grid silicon oxide layer of different-thickness in a thermal oxide growth technique, greatly simplified technological process; The pre-amorphous injection of germanium and/or silicon simultaneously reduces the channeling effect of Implantation, reduce the diffusion of follow-up ion, improved the channel carrier mobility, and the annealing recrystallization process after decrystallized injection and fluorine, nitrogen Implantation, the substrate surface characteristic can be optimized, and the reliability that is conducive to grid silicon oxide layer subsequently improves; And the peak value that this PROCESS FOR TREATMENT makes low-voltage device district nitrogen concentration profile can effectively stop follow-up boron penetration from the P+ polysilicon near the grid silicon oxide layer surface, the reliability of enhancing low-voltage device district thin-grid silicon oxide layer.
Embodiment two
As shown in Figure 4, this enforcement provides a kind of preparation method of grid silicon oxide layer, comprises the following steps:
S41, provide silicon substrate, forms device isolation structure in described silicon substrate, to keep apart low-voltage device district and high voltage device regions;
S42, form pad oxide on described silicon substrate;
S43, carry out trap Implantation and annealing in described silicon substrate;
S44, carry out the pre-amorphous injection of germanium ion to the semiconductor substrate surface of described low-voltage device district and high voltage device regions;
S45, the semiconductor substrate surface in described low-voltage device district carries out the nitrogen Implantation, carries out fluorine ion at the semiconductor substrate surface of described high voltage device regions and injects;
S46, the described pad oxide of etching, to expose the channel region of low-voltage device district and high voltage device regions;
S47, the described semiconductor substrate surface of thermal oxidation is with the growth grid silicon oxide layer, and described high voltage device regions is thicker than the grid silicon oxide layer in low-voltage device district.
Please refer to Fig. 5 A, in step S41, the silicon substrate 500 that provides can be the pure silicon substrate, it can be also germanium silicon (SiGe) substrate, can also be silicon-on-insulator substrate, then can form shallow trench by etch silicon substrate 500, and fill oxide in the shallow trench after etching, form fleet plough groove isolation structure (STI) 501, by STI 501, isolate low-voltage device district I, the first high voltage device regions II and the second high voltage device regions III.
Please continue the 5A with reference to figure, in step S42, by techniques such as ald, plasma enhanced chemical vapor deposition and physical vapor depositions, form pad oxide 502 on described silicon substrate 500.Described pad oxide 502 provides resilient coating for the hard mask layer that forms before follow-up Implantation and can be used as stop-layer in follow-up removal hard mask layer step.
Please continue the 5A with reference to figure, in step S43, first form the hard mask layer of well region Implantation on pad oxide 502, then carry out boron and inject to form P well region (not shown) in described silicon substrate 500, and carry out arsenic or phosphorus injection N well region (not shown); Then remove the hard mask layer of the well region Implantation that forms.
Please continue the 5A with reference to figure, in step S44, form pre-amorphous injection hard mask layer on pad oxide 502, then take the pre-amorphous injection hard mask layer that forms as mask, carry out germanium (Ge) or the pre-amorphous injection of silicon ion on silicon substrate 500 surfaces that expose low-voltage device district I, the first high voltage device regions II and the second high voltage device regions III, and carry out annealing, make the silicon on silicon substrate 500 surfaces become noncrystalline state by monocrystalline state.Before follow-up Implantation, the germanium that injects or silicon ion make silicon substrate 500 surfaces pre-amorphous, can reduce the channeling effect of follow-up Implantation, reduce Impurity Diffusion, therefore pre-amorphous injection can realize shallow junction and precipitous Impurity Distribution, and can improve impurity activation by the annealing process after pre-amorphous Implantation; Then remove the pre-amorphous injection hard mask layer that forms.
Preferably, the energy of the pre-amorphous injection of described germanium ion is 10KeV ~ 50KeV, and dosage is 1E14/cm
2~ 1.5E15/cm
2, angle is 2 ~ 30 °.
Please refer to Fig. 5 B, in step S45, form nitrogen and inject the hard mask layer (not shown) on pad oxide 502, this nitrogen injects hard mask layer and exposes the channel region of low-voltage device district I, then inject hard mask layer as mask take the nitrogen that forms, at the channel region that exposes low-voltage device district I, inject the nitrogen plasma; Then, remove the nitrogen that forms and inject hard mask layer; Then, form the first fluorine and inject the hard mask layer (not shown) on pad oxide 502, this first fluorine injects hard mask layer and exposes the channel region of the first high voltage device regions II, then inject hard mask layer as mask take the first fluorine that forms, at the channel region that exposes the first high voltage device regions II, inject the fluorine plasma; Then, remove the first fluorine that forms and inject hard mask layer; Then, form the second fluorine and inject the hard mask layer (not shown) on pad oxide 502, this second fluorine injects hard mask layer and exposes the channel region of the second high voltage device regions III, then inject hard mask layer as mask take the second fluorine that forms,, with the fluorine ion implantation dosage larger than the first high voltage device regions, at the channel region that exposes the second high voltage device regions III, inject the fluorine plasma; Then, remove the second fluorine that forms and inject hard mask layer.Annealing recrystallization process after the fluorine nitrogen Implantation of the pre-amorphous injection of germanium in step S44 and/or silicon and step S45, the surface of silicon characteristic can be optimized, and the reliability that is conducive to gate oxide subsequently improves; And the peak value that this PROCESS FOR TREATMENT makes low-voltage device district nitrogen concentration profile can effectively stop follow-up boron penetration from the P+ polysilicon near the grid silicon oxide layer surface, the reliability of enhancing low-voltage device district thin-grid silicon oxide layer.
Please refer to Fig. 5 C, in step S46, the described pad oxide 502 of etching, to expose low-voltage device district I, the first high voltage device regions II and the second high voltage device regions III.
Please refer to Fig. 5 C, in step S47, thickness requirement according to the gate oxide of low-voltage device and high tension apparatus, set corresponding thermal oxidation technology formula (gate oxide recipe), according to this technical recipe thermal oxidation silicon substrate surface, and then grow the grid silicon oxide layer of low-voltage device district I, the first high voltage device regions II and the second high voltage device regions III.Wherein, the thickness of the grid silicon oxide layer 504 of low-voltage device district I is less than the thickness of the grid silicon oxide layer 505 of the first high voltage device regions II, and the thickness of the grid silicon oxide layer 505 of the first high voltage device regions II is less than the thickness of the grid silicon oxide layer 506 of the second high voltage device regions III.
Preferably, the energy of described nitrogen Implantation is 0.2KeV ~ 3KeV, and dosage is 1E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
Preferably, the energy that the fluorine ion of described the first high voltage device regions injects is 0.2KeV ~ 5KeV, and dosage is 1E14/cm
2~ 1.5E15/cm
2, angle is 2 ~ 30 °; The energy that the fluorine ion of described the second high voltage device regions injects is 1KeV～10KeV, and dosage is 3E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
Preferably, the technical recipe of described thermal oxidation comprises dried oxygen and wet oxygen growth, and the technological parameter of described dried oxide growth comprises: oxygen flow is 0.3L/min～1.5L/min, and nitrogen flow is 1L/min ~ 20L/min, air pressure is 0.5atm～1.5atm, temperature 700 ~ 800oC; The technological parameter of described wet oxygen growth: the steam flow is 0.1L/min ~ 1L/min, and nitrogen flow is 1L/min ~ 20L/min, and air pressure is 0.5atm～1.5atm, 700 ~ 800 ° of C of temperature.
In the successive process of CMOS integrated circuit, can carry out polysilicon deposition, then etch polysilicon and grid silicon oxide layer 504,505,506 on the device architecture that step S47 forms, to form the stacked gate architectures of low-voltage device district I, the first high voltage device regions II and the second high voltage device regions III.
The preparation method of the grid silicon oxide layer that the present embodiment provides, compare with embodiment one, before the etching of pad oxide is adjusted to thermal oxide growth gate oxidation silicon, equally also only need one thermal oxidation technology can obtain the grid silicon oxide layer of low-voltage device district and high voltage device regions different-thickness.
Embodiment three
As shown in Figure 7, the present embodiment provides a kind of Semiconductor substrate processing method, comprises the following steps:
S71, provide Semiconductor substrate, and described Semiconductor substrate comprises a plurality of subregions;
S72, carry out the nitrogen Implantation on a subregion surface of described Semiconductor substrate, carries out fluorine ion on another subregion surface of described Semiconductor substrate and inject;
S73, the described semiconductor substrate surface of thermal oxidation is with the growth oxide layer, and the subregion that described fluorine ion injects is than the oxidation bed thickness of the subregion of described nitrogen Implantation.
The Semiconductor substrate that provides in step S71 comprises a plurality of subregions, and these subregions can be the high voltage device regions described in embodiment one and embodiment two and low-voltage device district, also can be the device isolation groove.
The concrete operations of step S72 can reference example one step S26 and the step S45 of embodiment two; The concrete operations of step S63 can reference example one step S27 and the step S47 of embodiment two.
Need to prove, as shown in Figure 6, find after tested, in the situation that other technological parameters are identical, for example the nitrogen Implantation Energy is that 0.7KeV or fluorine inject 1KeV, the thickness of thermal oxidation substrate growth oxide layer reduces with the increase of nitrogen (N) ion implantation dosage, increase with fluorine (F) ion implantation dosage increases, and adjusts the thermal oxidation technology parameter of nitrogen (N) ion implantation dosage, fluorine (F) ion implantation dosage and corresponding Controlling Growth Rate and just can adjust the oxidated layer thickness of thermal oxide growth.
Preferably, the energy of described nitrogen Implantation is 0.2KeV ~ 3KeV, and dosage is 1E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °; The energy that described fluorine ion injects is 0.2KeV ~ 10KeV, and dosage is 1E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
Preferably, before described nitrogen Implantation and fluorine ion injection, described semiconductor substrate surface is carried out germanium and/or the pre-amorphous injection of silicon ion, to reduce the channeling effect of Implantation, reduce the diffusion of follow-up ion, improved the channel carrier mobility, preferred, the energy of described pre-amorphous injection is 10KeV ~ 50KeV, and dosage is 1E14/cm
2~ 1.5E15/cm
2, angle is 2 ~ 30 °.
Preferably, the technical recipe of described thermal oxidation comprises dried oxygen and wet oxygen growth, and the technological parameter of described dried oxide growth comprises: oxygen flow is 0.3L/min ~ 1.5L/min, and nitrogen flow is 1L/min ~ 20L/min, air pressure is 0.5atm ~ 1.5atm, temperature 700 ~ 800oC; The technological parameter of described wet oxygen growth: the steam flow is 0.1L/min ~ 1L/min, and nitrogen flow is 1L/min ~ 20L/min, and air pressure is 0.5atm ~ 1.5atm, 700 ~ 800 ° of C of temperature.
The semiconductor processing that the present embodiment provides, inject nitrogen and the fluorine of variable concentrations by the subregion different, just can go out the oxide layer of different-thickness at different subregion thermal oxide growths, greatly simplify the oxide layer manufacturing process flow in same substrate different-thickness zone; Annealing recrystallization process after while germanium and/or the pre-amorphous injection of silicon and fluorine, nitrogen Implantation, the substrate surface characteristic can be optimized, and is conducive to the reliability of the oxide layer of thermal oxide growth subsequently and improves.
In sum, the preparation method of grid silicon oxide layer and Semiconductor substrate processing method, inject fluorine ion at low-voltage device district injecting nitrogen ion and in high voltage device regions in advance, make when thermal oxidation semiconductor substrate surface growth grid silicon oxide layer, the growth of the grid silicon oxide layer in low-voltage device district is inhibited, the growth of the grid silicon oxide layer of high voltage device regions is promoted, and then forms the grid silicon oxide layer of different-thickness, has greatly simplified technological process; The further pre-amorphous injection of germanium and/or silicon in Semiconductor substrate, improved the channel carrier mobility; And the annealing recrystallization process after decrystallized injection and fluorine nitrogen Implantation, the surface of silicon characteristic can be optimized, and the reliability that is conducive to gate oxide subsequently improves; And the peak value that this PROCESS FOR TREATMENT makes low-voltage device district nitrogen concentration profile can effectively stop follow-up boron penetration from the P+ polysilicon near the grid silicon oxide layer surface, the reliability of enhancing low-voltage device district thin-grid silicon oxide layer.
Obviously, those skilled in the art can carry out various changes and modification and not break away from the spirit and scope of the present invention invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention also is intended to comprise these changes and modification interior.
Claims (16)
1. the preparation method of a grid silicon oxide layer, is characterized in that, comprising:
Semiconductor substrate with low-voltage device district and high voltage device regions is provided;
Semiconductor substrate surface in described low-voltage device district carries out the nitrogen Implantation, carries out fluorine ion at the semiconductor substrate surface of described high voltage device regions and injects;
The described semiconductor substrate surface of thermal oxidation is with the growth grid silicon oxide layer, and described high voltage device regions is thicker than the grid silicon oxide layer in low-voltage device district.
2. the preparation method of grid silicon oxide layer as claimed in claim 1, is characterized in that, before described nitrogen Implantation and fluorine ion inject, the semiconductor substrate surface of described low-voltage device district and high voltage device regions carried out germanium and/or the pre-amorphous injection of silicon ion.
3. the preparation method of grid silicon oxide layer as claimed in claim 2, is characterized in that, the energy of described pre-amorphous injection is 10KeV ~ 50KeV, and dosage is 1E14/cm
2～1.5E15/cm
2, angle is 2 ~ 30 °.
4. the preparation method of grid silicon oxide layer as claimed in claim 1, is characterized in that, the energy of described nitrogen Implantation is 0.2KeV ~ 3KeV, and dosage is 1E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
5. the preparation method of grid silicon oxide layer as claimed in claim 1, is characterized in that, the energy that described fluorine ion injects is 0.2KeV ~ 10KeV, and dosage is 1E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
6. the preparation method of grid silicon oxide layer as claimed in claim 1, it is characterized in that, described high voltage device regions comprises the first high voltage device regions and the second high voltage device regions, and described the second high voltage device regions is larger than the dosage that the fluorine ion of the first high voltage device regions injects, so that the grid silicon oxide layer that thermal oxidation forms is large at the thickness of the first high voltage device regions at the second high voltage device regions ratio.
7. the preparation method of grid silicon oxide layer as claimed in claim 6, is characterized in that, the energy that the fluorine ion of described the first high voltage device regions injects is 0.2KeV ~ 5KeV, and dosage is 1E14/cm
2~ 1.5E15/cm
2, angle is 2 ~ 30 °; The energy that the fluorine ion of described the second high voltage device regions injects is 1KeV ~ 10KeV, and dosage is 3E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
8. the preparation method of grid silicon oxide layer as claimed in claim 1, is characterized in that, provides the step of the Semiconductor substrate with low-voltage device district and high voltage device regions to comprise:
Silicon substrate is provided, forms device isolation structure in described silicon substrate, to keep apart low-voltage device district and high voltage device regions;
Form pad oxide on described silicon substrate;
Carry out trap Implantation and annealing in described silicon substrate;
The described pad oxide of etching, to expose the channel region of low-voltage device district and high voltage device regions.
9. the preparation method of grid silicon oxide layer as claimed in claim 8, is characterized in that, described nitrogen Implantation and fluorine ion carry out before or after being infused in the described pad oxide of etching.
10. the preparation method of grid silicon oxide layer as claimed in claim 1, it is characterized in that, the technical recipe of described thermal oxidation comprises dried oxygen and wet oxygen growth, the technological parameter of described dried oxide growth comprises: oxygen flow is 0.3L/min ~ 1.5L/min, nitrogen flow is 1L/min ~ 20L/min, air pressure is 0.5atm ~ 1.5atm, temperature 700 ~ 800oC; The technological parameter of described wet oxygen growth: the steam flow is 0.1L/min ~ 1L/min, and nitrogen flow is 1L/min ~ 20L/min, and air pressure is 0.5atm ~ 1.5atm, 700 ~ 800 ° of C of temperature.
11. a Semiconductor substrate processing method, is characterized in that, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises a plurality of subregions;
The nitrogen Implantation is carried out on a subregion surface in described Semiconductor substrate, carries out fluorine ion on another subregion surface of described Semiconductor substrate and injects;
The described semiconductor substrate surface of thermal oxidation is with the growth oxide layer, and the subregion that described fluorine ion injects is than the oxidation bed thickness of the subregion of described nitrogen Implantation.
12. Semiconductor substrate processing method as claimed in claim 11, is characterized in that, before described nitrogen Implantation and fluorine ion injection, described semiconductor substrate surface carried out germanium and/or the pre-amorphous injection of silicon ion.
13. Semiconductor substrate processing method as claimed in claim 12, is characterized in that, the energy of described pre-amorphous injection is 10KeV ~ 50KeV, and dosage is 1E14/cm
2～1.5E15/cm
2, angle is 2 ~ 30 °.
14. Semiconductor substrate processing method as claimed in claim 11, is characterized in that, the energy of described nitrogen Implantation is 0.2KeV ~ 3KeV, and dosage is 1E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
15. Semiconductor substrate processing method as claimed in claim 11, is characterized in that, the energy that described fluorine ion injects is 0.2KeV ~ 10KeV, and dosage is 1E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
16. the preparation method of grid silicon oxide layer as claimed in claim 11, it is characterized in that, the technical recipe of described thermal oxidation comprises dried oxygen and wet oxygen growth, the technological parameter of described dried oxide growth comprises: oxygen flow is 0.3L/min ~ 1.5L/min, nitrogen flow is 1L/min ~ 20L/min, air pressure is 0.5atm ~ 1.5atm, temperature 700 ~ 800oC; The technological parameter of described wet oxygen growth: the steam flow is 0.1L/min ~ 1L/min, and nitrogen flow is 1L/min ~ 20L/min, and air pressure is 0.5atm ~ 1.5atm, 700 ~ 800 ° of C of temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101434668A CN103390548A (en) | 2012-05-09 | 2012-05-09 | Method for preparing gate silicon oxide layers and method for processing semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101434668A CN103390548A (en) | 2012-05-09 | 2012-05-09 | Method for preparing gate silicon oxide layers and method for processing semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103390548A true CN103390548A (en) | 2013-11-13 |
Family
ID=49534783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012101434668A Pending CN103390548A (en) | 2012-05-09 | 2012-05-09 | Method for preparing gate silicon oxide layers and method for processing semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103390548A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112289682A (en) * | 2020-10-30 | 2021-01-29 | 上海华力微电子有限公司 | Method for forming grid oxide layer |
| CN112382612A (en) * | 2020-11-04 | 2021-02-19 | 上海华力集成电路制造有限公司 | Method for preparing gate oxide layer |
| CN112582272A (en) * | 2020-12-11 | 2021-03-30 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
| CN113380799A (en) * | 2021-05-28 | 2021-09-10 | 重庆中科渝芯电子有限公司 | Low dislocation density high reliability high and low voltage CMOS self-aligned double-well process and device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6399448B1 (en) * | 1999-11-19 | 2002-06-04 | Chartered Semiconductor Manufacturing Ltd. | Method for forming dual gate oxide |
| KR20040000238A (en) * | 2002-06-24 | 2004-01-03 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
| KR20050009482A (en) * | 2003-07-16 | 2005-01-25 | 매그나칩 반도체 유한회사 | Method of manufacturing a semiconductor device |
| KR20060036281A (en) * | 2004-10-25 | 2006-04-28 | 매그나칩 반도체 유한회사 | Dual Gate Oxide Method for Semiconductor Devices |
| US20090179255A1 (en) * | 2007-12-28 | 2009-07-16 | Magnachip Semiconductor, Ltd. | Method for forming gate oxide of semiconductor device |
-
2012
- 2012-05-09 CN CN2012101434668A patent/CN103390548A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6399448B1 (en) * | 1999-11-19 | 2002-06-04 | Chartered Semiconductor Manufacturing Ltd. | Method for forming dual gate oxide |
| KR20040000238A (en) * | 2002-06-24 | 2004-01-03 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
| KR20050009482A (en) * | 2003-07-16 | 2005-01-25 | 매그나칩 반도체 유한회사 | Method of manufacturing a semiconductor device |
| KR20060036281A (en) * | 2004-10-25 | 2006-04-28 | 매그나칩 반도체 유한회사 | Dual Gate Oxide Method for Semiconductor Devices |
| US20090179255A1 (en) * | 2007-12-28 | 2009-07-16 | Magnachip Semiconductor, Ltd. | Method for forming gate oxide of semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112289682A (en) * | 2020-10-30 | 2021-01-29 | 上海华力微电子有限公司 | Method for forming grid oxide layer |
| CN112289682B (en) * | 2020-10-30 | 2023-11-17 | 上海华力微电子有限公司 | Method for forming gate oxide layer |
| CN112382612A (en) * | 2020-11-04 | 2021-02-19 | 上海华力集成电路制造有限公司 | Method for preparing gate oxide layer |
| CN112582272A (en) * | 2020-12-11 | 2021-03-30 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
| CN113380799A (en) * | 2021-05-28 | 2021-09-10 | 重庆中科渝芯电子有限公司 | Low dislocation density high reliability high and low voltage CMOS self-aligned double-well process and device |
| CN113380799B (en) * | 2021-05-28 | 2022-06-14 | 重庆中科渝芯电子有限公司 | Low dislocation density, high reliability, high and low voltage CMOS self-aligned double well process method and device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100954874B1 (en) | Semiconductor device with retrograde dopant profile in channel region and method for manufacturing same | |
| US7439140B2 (en) | Formation of standard voltage threshold and low voltage threshold MOSFET devices | |
| US8580663B2 (en) | Formation of shallow junctions by diffusion from a dielectronic doped by cluster or molecular ion beams | |
| CN101840889B (en) | Method of manufacturing semiconductor device | |
| JP2005522038A (en) | Semiconductor device with retrograde dopant distribution in channel region and method for manufacturing such semiconductor device | |
| CN101517741A (en) | A transistor having a strained channel region including a performance enhancing material composition | |
| CN103390548A (en) | Method for preparing gate silicon oxide layers and method for processing semiconductor substrate | |
| US9362399B2 (en) | Well implant through dummy gate oxide in gate-last process | |
| US20120034749A1 (en) | Method for manufacturing a strained semiconductor device | |
| CN102097376B (en) | Method for manufacturing semiconductor device | |
| US20150349065A1 (en) | Transistor structure including epitaxial channel layers and raised source/drain regions | |
| CN102054678A (en) | Oxidation method | |
| CN106158657A (en) | The forming method of MOS transistor | |
| JP2007005627A (en) | Method for manufacturing semiconductor device | |
| KR100840684B1 (en) | Manufacturing method of semiconductor device | |
| US8501603B2 (en) | Method for fabricating high voltage transistor | |
| CN106328534B (en) | MOS transistor and method of forming the same | |
| CN101577230B (en) | Manufacturing method of semiconductor device | |
| CN102543824B (en) | Manufacturing method of STI (shallow trench insulation) | |
| US6284608B1 (en) | Method for making accumulation mode N-channel SOI | |
| CN101577229A (en) | Semiconductor element and manufacturing method thereof | |
| US7101746B2 (en) | Method to lower work function of gate electrode through Ge implantation | |
| KR20100079139A (en) | Method for manufacturing semiconductor device | |
| KR100679812B1 (en) | MOS transistor and its manufacturing method | |
| KR20050091496A (en) | Forming method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20131113 |
|
| RJ01 | Rejection of invention patent application after publication |