CN103377884B - Hard mask layer structure and low K dielectric layer lithographic method - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000010949 copper Substances 0.000 claims abstract description 47
- 150000004767 nitrides Chemical class 0.000 claims abstract description 35
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 30
- 238000001039 wet etching Methods 0.000 claims abstract description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052802 copper Inorganic materials 0.000 claims abstract description 17
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 13
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 7
- 239000007789 gas Substances 0.000 claims description 7
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 20
- 230000008569 process Effects 0.000 abstract description 14
- 238000005516 engineering process Methods 0.000 abstract description 11
- 238000009713 electroplating Methods 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 4
- 230000001771 impaired effect Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 118
- 239000002184 metal Substances 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 15
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 6
- 230000009977 dual effect Effects 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229920002521 macromolecule Polymers 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 150000005846 sugar alcohols Polymers 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a kind of hard mask layer structure and low K dielectric layer lithographic method, by using cuprous nitride (Cu
3n) hard mask layer, avoids inorganic Ti in existing low-K dielectric lithographic technique
xf
ythe formation of residue, and cuprous nitride (Cu
3n) hard mask layer is easy to remove, thus inhibits the formation of the hole defect in subsequent copper electroplating technology, improves device electromigration and reliability, improves product yield; Further, on the etching inwall of low K dielectric layer, form barrier layer by the nitrogen treatment technique after etching, relaxed low K dielectric layer and cuprous nitride (Cu
3n) the wet etching Selection radio difference of hard mask layer, avoids low K dielectric layer to remove cuprous nitride (Cu at wet etching
3n) impaired during hard mask layer, effectively increase the process window after the etching of low K dielectric layer.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of hard mask layer structure and low K dielectric layer lithographic method.
Background technology
At present in integrated circuit metal interconnection line manufactures, low-K dielectric material is widely used in alternative SiO
2to shorten RC time delay.Due to the reduction of K value, low-k dielectric films is more responsive to physics and chemistry damage.The damage that etching technics causes is proved to be the reason that in integrated circuit structure, k value local increases and/or reliability reduces, and this can slacken the advantage adopting low-K dielectric material.And metal hard mask has diverse chemical property, traditional SiO can be substituted
2with SiC inorganic hardmasks layer, in selectivity and anisotropic etching, there is better performance, stop the generation of plasma damage in patterning process, excellent CD performance and pattern can be provided to control, retain the K value of low-k dielectric materials, to improve speed and the rate of finished products of chip simultaneously.
TiN, with advantages such as its low-resistivity, low diffusion coefficient and high rigidity, is widely used in metal hard mask Damascus dual-damascene technics (i.e. low K dual damascene copper wiring technique).Figure 1 shows that a kind of typical low K dual damascene copper wiring technique device architecture cutaway view, usual using plasma dry method etch technology, using TiN layer 102 as metal hard mask, etching low K dielectric layer 101, forms groove 103 and the through hole 104 of upright side walls.TiN layer 102 continues to diffuse in low K dielectric layer 101 in processing step (particularly wet-cleaned and copper electroplating technology) process subsequently as the anti-sealing of protective layer and movable ion.
But above-mentioned TiN metal hard mask plasma etch process often produces a lot of residue, comprises Cu
xo
y, sidewall macromolecule polyalcohol and inorganic Ti
xf
ydeng residue, inorganic Ti
xf
yresidue 105 can grow along with the time, becomes fine and close, makes to produce cavity blemish (voiddefect) in the copper electroplating technology of follow-up groove and through hole, increase the resistance of device, affect electromigration and the reliability of device; Meanwhile, TiN layer is difficult to be removed by wet etching, needs longer etching time, easily destroys the process window of groove and through hole.
Summary of the invention
The object of the present invention is to provide a kind of hard mask layer structure and low K dielectric layer lithographic method, can Ti be avoided
xf
ythe generation of etch residue, increases the process window after etching, improves the cavity blemish in copper electroplating technology, improves the yield of product.
In order to solve the problem, the invention provides a kind of hard mask layer structure, comprising metal hard mask layer, described metal hard mask layer is cuprous nitride (Cu
3n).
Further, described hard mask layer structure also comprises: the TEOS hard mask layer formed before described metal hard mask layer.
Accordingly, the present invention also provides a kind of low K dielectric layer lithographic method, comprises the following steps:
The Semiconductor substrate that one is formed with low K dielectric layer is provided;
Described low K dielectric layer is formed TEOS hard mask layer;
Described TEOS hard mask layer forms cuprous nitride (Cu
3n) hard mask layer;
With described cuprous nitride (Cu
3n) hard mask layer and TEOS hard mask layer are hard mask, low K dielectric layer described in dry etching.
Further, the thickness of described TEOS hard mask layer is
Further, copper target, argon gas and nitrogen is adopted to carry out rf magnetron sputtering to form described cuprous nitride (Cu
3n) hard mask layer.
Further, described low K dielectric layer lithographic method also comprises:
After described dry etching, adopt low K dielectric layer described in nitrogen treatment, so that the surface exposed at described low K dielectric layer to form one deck barrier layer;
Described cuprous nitride (Cu is removed by wet etching
3n) hard mask layer.
Further, the technological parameter of described nitrogen treatment comprises: pressure is 10 ~ 100mTorr; Radio-frequency power is 100 ~-500W; Rf frequency is 2 ~ 60MHz; Gas flow is 100 ~ 500sccm; Processing time is 10 ~ 300secs.
Further, adopt hydrochloric acid solution to described cuprous nitride (Cu
3n) hard mask layer carries out wet etching.
Further, the concentration of described hydrochloric acid solution is 10 ~ 100g/L; The wet etching time is 5 ~ 50secs.
Compared with prior art, hard mask layer structure provided by the invention and low K dielectric layer lithographic method, by using cuprous nitride hard mask layer, avoid inorganic Ti in existing low-K dielectric lithographic technique
xf
ythe formation of residue, and cuprous nitride hard mask layer is easy to remove, thus inhibit the formation of the hole defect in subsequent copper electroplating technology, improve device electromigration and and reliability, improve product yield; Further, on the etching inwall of low K dielectric layer, barrier layer is formed by the nitrogen treatment technique after etching, relax the wet etching Selection radio difference of low K dielectric layer and cuprous nitride hard mask layer, avoid low K dielectric layer impaired when wet etching removes cuprous nitride hard mask layer, effectively increase the process window after the etching of low K dielectric layer.
Accompanying drawing explanation
Fig. 1 is the semiconductor device sectional structure chart of a kind of dual daascence interconnection technique of prior art;
Fig. 2 is the schematic diagram of the hard mask layer structure of the specific embodiment of the invention;
Fig. 3 is the low K dielectric layer lithographic method flow chart of the specific embodiment of the invention;
Fig. 4 A ~ 4E is the device architecture cutaway view in the low K dielectric layer etching process of the specific embodiment of the invention.
Embodiment
The hard mask layer structure proposed the present invention below in conjunction with the drawings and specific embodiments and low K dielectric layer lithographic method are described in further detail.
As shown in Figure 2, the invention provides a kind of hard mask layer structure 2, comprise metal hard mask layer 203, described metal hard mask layer is cuprous nitride (Cu
3n).
In this embodiment, described hard mask layer structure 2 also comprises: the TEOS hard mask layer 202 formed before described metal hard mask layer 203.
Hard mask layer structure 2 of the present invention may be used for the etching of low K dielectric layer 201 in the dual-damascene technics of Damascus.As shown in Figure 2, with hard mask layer structure 2 for mask, the low K dielectric layer 201 on etch semiconductor substrates 200 can form through hole (Via) and the groove (Trench) of Damascus dual-damascene technics.
As shown in Figure 3, the present invention also provides a kind of low K dielectric layer lithographic method, comprises the following steps:
S1, provides the Semiconductor substrate that is formed with low K dielectric layer;
S2, described low K dielectric layer is formed TEOS hard mask layer;
S3, described TEOS hard mask layer forms cuprous nitride (Cu
3n) hard mask layer;
S4, with described cuprous nitride (Cu
3n) hard mask layer and TEOS hard mask layer are hard mask, low K dielectric layer described in dry etching;
S5, adopts low K dielectric layer described in nitrogen treatment, so that the surface exposed at described low K dielectric layer to form one deck barrier layer;
S6, removes described cuprous nitride (Cu by wet etching
3n) hard mask layer.
Please refer to Fig. 4 A, in step S1, the Semiconductor substrate 400 provided can be silicon substrate, silicon-on-insulator substrate etc., and Semiconductor substrate 400 is formed low K dielectric layer 401.In the present embodiment, the Semiconductor substrate 400 provided is the interconnection layer substrate in the dual damascene copper interconnect processing procedure of Damascus, such as, comprise the substrate of bottom metal layer M1, also can be other metal levels Mx substrate or via layer Vx substrate; Low K dielectric layer 401 can be carbon-doped silicon oxide (SiOCH), porous material, organic polymer etc.
Please refer to Fig. 4 B, in step s 2, pass into tetraethoxysilane (TEOS) and the inert gas such as helium, argon gas, also pass into oxygen or ozone to provide oxygen plasma, carry out plasma enhanced deposition (PECVD), to form TEOS hard mask layer 402 on described low K dielectric layer 401, reaction equation is as follows:
TEOS++O+He/Ar → SiO
2+ accessory substance
When adopting TEOS to make raw material growing silicon oxide film, because the surface mobility of TEOS is large, the generation in density regions or cavity can be avoided, the interconnection line space that depth-width ratio reaches 1: 1 can be covered.In the present embodiment, the thickness forming TEOS hard mask layer 402 is
plasma enhanced deposition technique due to TEOS hard mask layer 402 is hard masking process conventional in prior art, does not repeat them here.
Please continue to refer to Fig. 4 B, the present embodiment is the hard masking process in dual damascene copper interconnect technique before through hole and/or etching groove step, needs plated metal hard mask layer on TEOS hard mask layer 402.Therefore in step s3, cuprous nitride (Cu can be formed by adopting copper target, argon gas and nitrogen to carry out rf magnetron sputtering on described TEOS hard mask layer
3n) hard mask layer 403.Due to cuprous nitride (Cu
3n) hardness of hard mask layer 403 is 8.8GPa (Cu is 1.7GPa), at room temperature quite stable and heat decomposition temperature lower (about 300 DEG C), Cu and nitrogen can be decomposed into, simultaneously very easily by acid corrosion (and Cu is extremely difficult and acid reaction).Therefore cuprous nitride (Cu
3n) hard mask layer 403 is compared with the TiN hard mask layer of prior art, can not form inorganic Ti in subsequent etching processes
xf
yresidue, and be easy to remove, thus can improve the cavity blemish (voiddefect) in the copper electroplating technology of follow-up groove and through hole, improve electromigration and the reliability of device.
Please refer to Fig. 4 C, in step s 4 which, be hard mask with metal hard mask layer 403 and TEOS hard mask layer 402, low K dielectric layer 401 described in dry etching, forms through hole 404 and groove 405 in low K dielectric layer 401.Owing to have employed cuprous nitride (Cu
3n), therefore dry etching low K dielectric layer 401 time not-inorganic Ti can be formed
xf
yresidue, can improve the cavity blemish (voiddefect) in the copper electroplating technology of follow-up groove and through hole, improves electromigration and the reliability of device.
Please refer to Fig. 4 D and 4E, in the present embodiment, after the dry etching of step S4, perform step S5: adopt nitrogen treatment (Post-etching) described low K dielectric layer 401, the surface that described low K dielectric layer 401 exposes and nitrogen react, form one deck barrier layer 406, namely on the madial wall of through hole 404 and groove 405, form one deck nitride-barrier; And then perform step S6: remove described cuprous nitride (Cu by wet etching
3n) hard mask layer 403.
In the present embodiment, the technological parameter of the nitrogen treatment of step S5 comprises: pressure is 10 ~ 100mTorr; Radio-frequency power is 100 ~ 500W; Rf frequency is 2 ~ 60MHz; Gas flow is 100 ~ 500sccm; Processing time is 10 ~ 300secs.The reagent of the wet etching of step S6 is hydrochloric acid solution, and concentration is 10 ~ 100g/L; The wet etching time is 5 ~ 50secs.
Due to cuprous nitride (Cu
3n) hard mask layer 403 is very easily by hcl corrosion, and barrier layer 406 prevents the water in wet etching and movable ion from entering low K dielectric layer as protective layer, has relaxed low K dielectric layer and cuprous nitride (Cu simultaneously
3n) the wet etching Selection radio difference of hard mask layer, avoids low K dielectric layer to remove cuprous nitride (Cu at wet etching
3n) impaired during hard mask layer, effectively increase the process window after the etching of low K dielectric layer, provide guarantee for follow-up copper plating fill process can obtain good filling capacity.Thus the copper filling defect that in prior art, the hard mask wet etching of TiN brings can not be introduced.
In sum, hard mask layer structure provided by the invention and low K dielectric layer lithographic method, by using cuprous nitride (Cu
3n) hard mask layer, avoids inorganic Ti in existing low-K dielectric lithographic technique
xf
ythe formation of residue, and cuprous nitride (Cu
3n) hard mask layer is easy to remove, thus inhibits the formation of the hole defect in subsequent copper electroplating technology, improve device electromigration and and reliability, improve product yield; Further, on the etching inwall of low K dielectric layer, form barrier layer by the nitrogen treatment technique after etching, relaxed low K dielectric layer and cuprous nitride (Cu
3n) the wet etching Selection radio difference of hard mask layer, avoids low K dielectric layer to remove cuprous nitride (Cu at wet etching
3n) impaired during hard mask layer, effectively increase the process window after the etching of low K dielectric layer.
Obviously, those skilled in the art can carry out various change and modification to invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (6)
1. a low K dielectric layer lithographic method, is characterized in that, comprising:
The Semiconductor substrate that one is formed with low K dielectric layer is provided;
Described low K dielectric layer is formed TEOS hard mask layer;
Described TEOS hard mask layer forms cuprous nitride hard mask layer;
Be hard mask with described cuprous nitride hard mask layer and TEOS hard mask layer, low K dielectric layer described in dry etching;
Adopt low K dielectric layer described in nitrogen treatment, so that the surface exposed at described low K dielectric layer to form one deck barrier layer;
Described cuprous nitride hard mask layer is removed by wet etching.
2. low K dielectric layer lithographic method as claimed in claim 1, it is characterized in that, the thickness of described TEOS hard mask layer is
3. low K dielectric layer lithographic method as claimed in claim 1, is characterized in that, adopts copper target, argon gas and nitrogen to carry out rf magnetron sputtering to form described cuprous nitride hard mask layer.
4. low K dielectric layer lithographic method as claimed in claim 1, it is characterized in that, the technological parameter of described nitrogen treatment comprises: pressure is 10 ~ 100mTorr; Radio-frequency power is 100 ~ 500W; Rf frequency is 2 ~ 60MHz; Gas flow is 100 ~ 500sccm; Processing time is 10 ~ 300secs.
5. low K dielectric layer lithographic method as claimed in claim 1, is characterized in that, adopts hydrochloric acid solution to carry out wet etching to described cuprous nitride hard mask layer.
6. low K dielectric layer lithographic method as claimed in claim 5, it is characterized in that, the concentration of described hydrochloric acid solution is 10 ~ 100g/L; The wet etching time is 5 ~ 50secs.
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| CN103377884B true CN103377884B (en) | 2016-02-03 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1196572A (en) * | 1997-03-31 | 1998-10-21 | 日本电气株式会社 | A semiconductor device with protected interlayer insulating film and its manufacturing method |
| CN102187276A (en) * | 2008-10-14 | 2011-09-14 | 旭化成株式会社 | Thermally reactive resist material, laminated body for thermal lithography using the material, and mold manufacturing method using the material and the laminated body |
| CN102403269A (en) * | 2011-11-30 | 2012-04-04 | 上海华力微电子有限公司 | Method for dry etching of first metal layer |
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| US7749906B2 (en) * | 2006-02-22 | 2010-07-06 | Intel Corporation | Using unstable nitrides to form semiconductor structures |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1196572A (en) * | 1997-03-31 | 1998-10-21 | 日本电气株式会社 | A semiconductor device with protected interlayer insulating film and its manufacturing method |
| CN102187276A (en) * | 2008-10-14 | 2011-09-14 | 旭化成株式会社 | Thermally reactive resist material, laminated body for thermal lithography using the material, and mold manufacturing method using the material and the laminated body |
| CN102403269A (en) * | 2011-11-30 | 2012-04-04 | 上海华力微电子有限公司 | Method for dry etching of first metal layer |
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