CN103377135B - Addressing method, Apparatus and system - Google Patents
Addressing method, Apparatus and system Download PDFInfo
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Abstract
The invention provides a kind of addressing method, Apparatus and system.Method comprises: obtain addressing instruction; The the first physical address subspace selected is determined according to the settings of a BSR; The mapping relations of the first logical address subspace in the first physical address subspace setting up described selection and the logical address space built in advance; Determine the logical address that described addressing instruction is corresponding; If described logical address is positioned at described first logical address subspace, then according to the first physical address subspace of described selection and the mapping relations of the first logical address subspace, determine the physical address in the first physical address subspace of the described selection that described logical address is corresponding; If described logical address is positioned at the second logical address subspace of the described logical address space built in advance, then according to the mapping relations of the second physical address subspace of setting up in advance and described second logical address subspace, determine the physical address in the described second physical address subspace that described logical address is corresponding.
Description
Technical field
The present invention relates to addressing technique, particularly relate to a kind of addressing method, Apparatus and system.
Background technology
The application of microprocessor is increasingly extensive, also constantly increases the demand of data space.But due to the command bits tolerance system of microprocessor, limit to the addressing range of addressing instruction to data space.Now, the addressing range of addressing instruction can not cover whole data space, can only addressable portion region.For example, data space is 2
10=1024 bytes, address realm 000H ~ 3FFH, the addressing instruction bit wide of microprocessor is 16, comprises 9 bit instruction codes and 7 positional operands, and wherein, 7 positional operands represent the address information of addressing, and addressing range is 2
7=128 bytes.Fig. 1 is the schematic diagram of 16 bit addressing instructions in prior art.
Data space is usually by universal random access memory (GeneralPurposeRandomAccessMemory is called for short GPR) and specified register (SpecialFunctionRegister is called for short SFR) composition.The addressing scheme of GPR and SFR in data space has two kinds: alternating expression addressing and unified addressing.In the scheme of alternating expression addressing, no matter be directly address or indirect addressing, the distribution mode that GPR and SFR is in all the time " discrete ".Although the GPR in each data storage area (BANK) is address continuous print, there is not continuity in the GPR address in adjacent BANK.And the discontinuous shortcoming in GPR address, microprocessor will be caused better cannot to support the high level languages such as C language, because high level language needs to use Large-scale array and structure, and large-scale array and structure need to take a large amount of continuous print GPR.
In the scheme of unified addressing, due to the address continuity of GPR, greatly facilitate the support to Large-scale array, structure and the support to higher level lanquage, but, when needs carry out data transmission and processing between different B ANK time, need to switch BANK operation very frequently.During directly address, need to arrange memory block mask register (BankSelectRegister is called for short BSR) frequently, these operate the instruction execution efficiency that all greatly can reduce microprocessor frequently.
Summary of the invention
The invention provides a kind of addressing method, Apparatus and system, when carrying out data transmission and processing in unified addressing scheme in order to solve in prior art between different B ANK, directly address frequently need arrange the problem of BSR.
One aspect of the present invention is to provide a kind of addressing method, comprising:
Obtain addressing instruction;
The the first physical address subspace selected is determined according to the settings of the first memory block mask register BSR;
The mapping relations of the first logical address subspace in the first physical address subspace setting up described selection and the logical address space built in advance;
Determine the logical address that described addressing instruction is corresponding;
If described logical address is positioned at described first logical address subspace, then according to the first physical address subspace of described selection and the mapping relations of the first logical address subspace, determine the physical address in the first physical address subspace of the described selection that described logical address is corresponding;
If described logical address is positioned at the second logical address subspace of the described logical address space built in advance, then according to the mapping relations of the second physical address subspace of setting up in advance and described second logical address subspace, determine the physical address in the described second physical address subspace that described logical address is corresponding.
Another aspect of the present invention is to provide a kind of device for addressing, comprising:
Acquisition module, for obtaining addressing instruction;
Select module, for determining the first physical address subspace selected according to the settings of the first memory block mask register BSR;
Mapping block, for the mapping relations of the first logical address subspace in the first physical address subspace of setting up described selection and the logical address space built in advance;
Determination module, for determining the logical address that described addressing instruction is corresponding;
Addressed module, if be positioned at described first logical address subspace for described logical address, then according to the first physical address subspace of described selection and the mapping relations of the first logical address subspace, determine the physical address in the first physical address subspace of the described selection that described logical address is corresponding; If described logical address is positioned at the second logical address subspace of the described logical address space built in advance, then according to the mapping relations of the second physical address subspace of setting up in advance and described second logical address subspace, determine the physical address in the described second physical address subspace that described logical address is corresponding.
Another aspect of the invention is to provide a kind of addressing system, comprising:
Processor, the first memory block mask register BSR, comprise the first physical address space of at least two the first physical address subspaces and comprise the second physical address space of at least one the second physical address subspace;
Described processor comprises device for addressing as above.
Technique effect of the present invention is: by the logical address space comprising the first logical address subspace and the second logical address subspace built in advance, when getting addressing instruction, the the first physical address subspace mapping selected by BSR is to the first logical address subspace, add the mapping relations of the second logical address subspace and the second physical address subspace in the logical address space set up in advance, logic-based address space is according to addressing instruction addressing first physical address subspace or the second physical address subspace, solve in prior art directly address when carrying out data transmission and processing in unified addressing scheme between different B ANK (namely different physical address subspaces) and the problem of BSR need be frequently set, realize directly address without the need to frequently revising the settings of BSR, just can switch between the first physical address subspace and the second physical address subspace by means of only amendment addressing instruction, improve instruction execution efficiency and the data transmission efficiency of microprocessor.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of 16 bit addressing instructions in prior art;
Address maps schematic diagram when Fig. 2 is the data space directly address of alternating expression addressing;
Address maps schematic diagram when Fig. 3 is the data space indirect addressing of alternating expression addressing;
Address maps schematic diagram when Fig. 4 is the data space directly address of unified addressing;
The schematic flow sheet of a kind of addressing method that Fig. 5 provides for the embodiment of the present invention;
Fig. 6 is the address maps schematic diagram in the embodiment of the present invention in a second physical address subspace situation.
The structural representation of a kind of device for addressing that Fig. 7 provides for the embodiment of the present invention;
The structural representation of a kind of addressing system that Fig. 8 provides for the embodiment of the present invention.
Embodiment
In order to clearly and detailedly introduce the embodiment of the present invention, first introduce the directly address in prior art under two kinds of addressing schemes and indirect addressing.
1) alternating expression addressing
Tentation data storage space is 2
10=1024 bytes, address realm 000H ~ 3FFH, wherein the storage space of GPR is 768 bytes, and the storage space of SFR is 256 bytes.The addressing instruction bit wide of microprocessor is 16, comprises 9 bit instruction codes and 7 positional operands, data space is divided into 8 BANK, and each BANK is 128 bytes, and low 32 address assignment in a BANK are to SFR, and high 96 address assignment are to GPR.
Address maps schematic diagram when Fig. 2 is the data space directly address of alternating expression addressing.As shown in Figure 2, during directly address, select mapped BANK by BSR, addressing instruction can this BANK of addressing.Each BANK is 128 bytes, is just in time covered by the addressing space of an addressing instruction.
Address maps schematic diagram when Fig. 3 is the data space indirect addressing of alternating expression addressing.As shown in Figure 3, during indirect addressing, microprocessor, by the mode of directly address, is accessed the indirect index register in SFR and indirect data register, thus is realized the function of indirect addressing.Because the bit wide of indirect addressing indexed registers is not by the restriction of addressing instruction bit wide, therefore indirect addressing can cover whole data space completely.
2) unified addressing
Tentation data storage space is 2
10=1024 bytes, address realm 000H ~ 3FFH, wherein the storage space of GPR is 768 bytes, and the storage space of SFR is 256 bytes.The addressing instruction bit wide supposing microprocessor is 16, and comprise 9 bit instruction codes and 7 positional operands, data space is divided into 8 BANK, each BANK is 128 bytes, and BANK0 ~ BANK5 distributes to GPR, and BANK6 ~ BANK7 distributes to SFR.
Address maps schematic diagram when Fig. 4 is the data space directly address of unified addressing.As shown in Figure 4, during directly address, select mapped BANK by BSR, comprise the BANK distributing to GPR and the BANK distributing to SFR, addressing instruction can this BANK of addressing.Each BANK is 128 bytes, is just in time covered by the addressing space of an addressing instruction.
During indirect addressing, similar in address maps mode and alternating expression encoding scheme.
Can find out, no matter it is all the same for being directly address or indirect addressing, directly address needs to arrange BSR frequently, and indirect addressing then needs the high address value arranging indirect index register frequently.These operate the instruction execution efficiency that all greatly can reduce microprocessor frequently.
The schematic flow sheet of a kind of addressing method that Fig. 5 provides for the embodiment of the present invention.As shown in Figure 5, the method comprises:
501, addressing instruction is obtained;
For example, device for addressing obtains addressing instruction.In the embodiment of the present invention, device for addressing is arranged within a processor.Particularly, device for addressing can obtain addressing instruction from programmed instruction memory block.The bit wide of addressing instruction depends on the instruction memory size of processor.Addressing instruction comprises order code and operand.
502, the first physical address subspace selected is determined according to the settings of a BSR;
Physical address subspace is equivalent to BANK, and the first physical address subspace is that the first physical address space obtains according to certain regular subregion, and the first physical address subspace can be divided at least two the first physical address subspaces.Described first physical address space can be ROM (read-only memory) (Read-OnlyMemory is called for short ROM), random access memory (RandomAccessMemory is called for short RAM) or SFR, particularly, can also be the GPR in RAM.Correspondingly, the first physical address subspace can be ROM memory block, RAM memory block or SFR memory block, can also be specifically the GPR memory block in RAM memory block.For example, GPR memory block refers to the data storage area distributing to GPR, and SFR memory block refers to the data storage area distributing to SFR.The size of each first physical address subspace is the same.Particularly, the settings of a BSR are set according to programmed instruction by processor.
503, the mapping relations of the first logical address subspace in the first physical address subspace setting up described selection and the logical address space built in advance;
Particularly, also comprised before 501:
Build described logical address space according to the addressing range of addressing instruction, described logical address space comprises described first logical address subspace and the second logical address subspace;
By the size subregion of the first physical address space according to described first logical address subspace, form at least two the first physical address subspaces, by the size subregion of the second physical address space according to described second logical address subspace, form at least one second physical address subspace.
Particularly, the addressing range of addressing instruction is determined according to the figure place of operand in addressing instruction, and described logical address space can cover the addressing range of addressing instruction, i.e. addressing space.For example, if the figure place of operand is 8 in addressing instruction, then logical address space is 2
8=256 bytes, i.e. 00H ~ FFH.The size of described first logical address subspace equals the size of the first physical address subspace, and the size of described second logical address subspace equals the size of the second physical address subspace, and the size of each second physical address subspace is the same.Described second physical address space can be ROM, RAM or SFR, particularly, can also be the GPR in RAM.Correspondingly, the second physical address subspace can be ROM memory block, RAM memory block or SFR memory block, particularly, can also be the GPR memory block in RAM memory block.Second logical address subspace is for setting up mapping relations with the second physical address subspace.First physical address space can be identical with the second physical address space, also can be different.For example, when the varying in size of the first physical address space and first logical address subspace identical with the second physical address space and the second logical address subspace, Same Physical address space can form the first physical address subspace and the second physical address subspace of different number.Particularly, first logical address subspace and the second position of logical address subspace in described logical address space also can be pre-set, such as the first logical address subspace is positioned at the low level of described logical address space, and the second logical address subspace is positioned at a high position for described logical address space.More preferably, the first logical address subspace is identical with the size of the second logical address subspace, and correspondingly, the first physical address subspace is also identical with the size of the second physical address subspace.
504, the logical address that described addressing instruction is corresponding is determined;
In the embodiment of the present invention, the logical address that described addressing instruction is corresponding is determined according to operand in described addressing instruction.For example, if operand is 36H in addressing instruction, then determine that corresponding logical address is 36H.
If 505 described logical addresses are positioned at described first logical address subspace, then according to the first physical address subspace of described selection and the mapping relations of the first logical address subspace, determine the physical address in the first physical address subspace of the described selection that described logical address is corresponding; If described logical address is positioned at the second logical address subspace of the described logical address space built in advance, then according to the mapping relations of the second physical address subspace of setting up in advance and described second logical address subspace, determine the physical address in the described second physical address subspace that described logical address is corresponding.
For example, the address realm of logic of propositions address space is 00H ~ FFH, wherein the address realm of the first logical address subspace is 00H ~ 7FH, the address realm of the second logical address subspace is 80H ~ FFH, if described logical address is 36H, then be positioned at the first logical address subspace, if described logical address is 96H, be then positioned at the second logical address subspace.Further, if the address realm of the first physical address subspace selected is 0080H ~ 00FFH, physical address in first physical address subspace of the described selection that then logical address 36H is corresponding is 00C6H, if the address realm having the second physical address subspace of mapping relations with the second logical address subspace is FF80H ~ FFFFH, then the physical address in the second physical address subspace that logical address 96H is corresponding is FF96H.Namely, if described logical address is positioned at the first logical address subspace, using described logical address relative to the skew of the start address of the first logical address subspace as the skew of physical address relative to the start address of the first physical address subspace of described selection; If described logical address is positioned at the second logical address subspace, using described logical address relative to the skew of the start address of the second logical address subspace as the skew of physical address relative to the start address of described second physical address subspace.
After completing address procedures by above-mentioned steps 501 ~ 505, determining physical address, can also carry out the operation such as reading or write of data in the position that this physical address is corresponding according to programmed instruction, the present embodiment does not limit this.
In an optional embodiment of the present invention, if the second physical address subspace only has one, described formation also comprises after at least one second physical address subspace:
Set up the mapping relations of described second logical address subspace and described second physical address subspace.
That is, when only having a second physical address subspace, can set up the mapping relations between this second physical address subspace and the second logical address subspace in advance, and the mapping relations of this second logical address subspace and this second physical address subspace can remain unchanged.Fig. 6 is the address maps schematic diagram in the embodiment of the present invention in a second physical address subspace situation.Wherein, 0000H ~ 07FFH is assigned with and gives the first physical address space, and FF80H ~ FFFFH is assigned with and gives the second physical address space, retains physical address space in addition; First physical address space has been divided into 16 the first physical address subspaces, and the second physical address space only comprises a second physical address subspace; Logical address subspace corresponding with the first physical address space in logical address space is the first logical address subspace, and the logical address subspace corresponding with the second physical address space is the second logical address subspace.
In another alternative embodiment of the present invention, if the second physical address subspace has at least two, then also comprise:
The the second physical address subspace selected is determined according to the settings of the 2nd BSR;
Set up the second physical address subspace of described selection and the mapping relations of described second logical address subspace;
Accordingly, the second physical address subspace that in 505, basis is set up in advance and the mapping relations of described second logical address subspace, determine that the physical address in the described second physical address subspace that described logical address is corresponding specifically comprises:
According to the second physical address subspace of described selection and the mapping relations of described second logical address subspace, determine the physical address in the second physical address subspace of the described selection that described logical address is corresponding.
That is, then the 2nd BSR is set, is used for from multiple second physical address subspace, selecting one, by the second physical address subspace mapping of selection to the second logical address subspace.In this case, the mapping object of the second logical address subspace may change.With a BSR similarly, the settings of the 2nd BSR also can be set according to programmed instruction by processor.
In order to switch BANK operation when reducing further and to carry out data transmission and processing between different memory areas frequently, described logical address space can also be expanded, to comprise more logical address subspace to be mapped to different physical address subspaces.Particularly, described logical address space also comprises the 3rd logical address subspace, also comprises before 501:
By the size subregion of the 3rd physical address space according to described 3rd logical address subspace, form at least two the 3rd physical address subspaces;
Also comprise after 501:
The 3rd physical address subspace selected is determined according to the settings of the 3rd BSR;
Set up the 3rd physical address subspace of described selection and the mapping relations of described 3rd logical address subspace;
Accordingly, also comprise after 504:
If described logical address is positioned at described 3rd logical address subspace, then according to the 3rd physical address subspace of described selection and the mapping relations of the 3rd logical address subspace, determine the physical address in the described 3rd physical address subspace that described logical address is corresponding.
Wherein, the size of the 3rd physical address subspace is identical with the size of the 3rd logical address subspace.Described 3rd physical address space can be ROM, RAM or SFR, can also be the GPR in RAM.Correspondingly, described 3rd physical address subspace also can be SFR memory block, ROM memory block or RAM memory block, can also be the GP memory block R in RAM memory block.3rd physical address space with the first physical address space, the second physical address space can be identical, or different.Described first physical address subspace, the second physical address subspace, the 3rd physical address subspace can be same memory blocks, also can be different memory blocks.In addition, similar with the second physical address subspace, when the 3rd physical address subspace only has one, without the need to arranging the 3rd BSR, before 501, the mapping relations of this 3rd physical address subspace and the 3rd logical address subspace can be set up in advance.
Particularly, when logical address space also comprises the 3rd logical address subspace, addressing instruction can be designed there is larger addressing range, namely increase the figure place of operand.For example, when the figure place of operand is 8, the addressing range of addressing instruction is 2
8=256 bytes, the size of the first/bis-logical address subspace is 2
7=128 bytes, when adding size and being also the 3rd logical address subspace of 128 bytes, can the figure place of design operation number be 9, namely the addressing range of addressing instruction be 2
9=512 bytes, can cover three logical address subspaces, even 4 logical address subspaces.If the addressing range of addressing instruction is constant, also the address realm of each logical address subspace can be reduced, correspondingly reduce the size of BANK.For example, when the figure place of operand is 8, the addressing range of addressing instruction is 2
8=256 bytes, the size of the first/bis-logical address subspace is 2
7=128 bytes, when needs increase the 3rd logical address subspace, all can be designed to 2 by the size of 3 logical address subspaces
6=64 bytes, are correspondingly designed to 64 bytes by the size of each BANK.If the address realm of the addressing range of addressing instruction and each logical address subspace is all constant, also can by the addressing range of software change in logical address space.For example, addressing range in logical address space is initially the first logical address subspace and the second logical address subspace, after completing an addressing by the first logical address subspace, addressing range in logical address space can be set in the second logical address subspace and the 3rd logical address subspace, after completing an addressing by the 3rd logical address subspace, the addressing range in logical address space can be set in the first logical address subspace and the second logical address subspace again.
It should be noted that, when logical address space also comprises the more logical address subspace such as the 4th logical address subspace, the 5th logical address subspace, addressing method is also similar with said process.In addition, also can according to the size of the figure place determination logical address space of the operand of addressing instruction, then according to different physical address spaces, logical address space is divided into and each physical address space multiple logical address subspace one to one, and is physical address subspace according to each physical address space subregion of the large young pathbreaker of the logical address subspace of correspondence.
It should be noted that, the embodiment of the present invention is mainly to the improvement of directly address.During indirect addressing, processor, by the mode of directly address, is accessed the indirect index register in SFR and indirect data register, thus is realized the function of indirect addressing.Because the bit wide of indirect addressing indexed registers is not by the restriction of addressing instruction bit wide, therefore indirect addressing can cover whole data space completely, i.e. all physical address spaces.
The logical address space that comprise first logical address subspace and second logical address subspace of the embodiment of the present invention by building in advance, when getting addressing instruction, the the first physical address subspace mapping selected by BSR is to the first logical address subspace, add the mapping relations of the second logical address subspace and the second physical address subspace in the logical address space set up in advance, logic-based address space is according to addressing instruction addressing first physical address subspace or the second physical address subspace, solve in prior art directly address when carrying out data transmission and processing in unified addressing scheme between different B ANK (namely different physical address subspaces) and the problem of BSR need be frequently set, realize directly address without the need to frequently revising the settings of BSR, just can switch between the first physical address subspace and the second physical address subspace by means of only amendment addressing instruction, improve instruction execution efficiency and the data transmission efficiency of microprocessor.
One of ordinary skill in the art will appreciate that: all or part of step realizing above-mentioned each embodiment of the method can have been come by the hardware that programmed instruction is relevant.Aforesaid program can be stored in a computer read/write memory medium.This program, when performing, performs the step comprising above-mentioned each embodiment of the method; And aforesaid storage medium comprises: ROM, RAM, magnetic disc or CD etc. various can be program code stored medium.
The structural representation of a kind of device for addressing that Fig. 7 provides for the embodiment of the present invention.As shown in Figure 7, this device comprises:
Acquisition module 71, for obtaining addressing instruction;
Select module 72, for determining the first physical address subspace selected according to the settings of a BSR;
Mapping block 73, for the mapping relations of the first logical address subspace in the first physical address subspace of setting up described selection and the logical address space built in advance;
Determination module 74, for determining the logical address that described addressing instruction is corresponding;
Addressed module 75, if be positioned at described first logical address subspace for described logical address, then according to the first physical address subspace of described selection and the mapping relations of the first logical address subspace, determine the physical address in the first physical address subspace of the described selection that described logical address is corresponding; If described logical address is positioned at the second logical address subspace of the described logical address space built in advance, then according to the mapping relations of the second physical address subspace of setting up in advance and described second logical address subspace, determine the physical address in the described second physical address subspace that described logical address is corresponding.
In an optional embodiment of the present invention, this device also comprises:
Build module, before obtaining addressing instruction at acquisition module 71, the addressing range according to addressing instruction builds the logical address space comprising described first logical address subspace and the second logical address subspace; By the size subregion of the first storage space according to described first logical address subspace, form at least two the first physical address subspaces, by the size subregion of the second storage space according to described second logical address subspace, form at least one second physical address subspace.Wherein, the size of described first logical address subspace equals the size of the first physical address subspace, and the size of described second logical address subspace equals the size of the second physical address subspace.
In another alternative embodiment of the present invention, if the second physical address subspace only has one, mapping block 73 also for,
After at least one second physical address subspace of described structure module generation, set up the mapping relations of described second logical address subspace and described second physical address subspace.
In another alternative embodiment of the present invention, if the second physical address subspace has at least two, select module 72 also for, according to the settings of the 2nd BSR determine select the second physical address subspace;
Mapping block 73 also for, set up the second physical address subspace of described selection and the mapping relations of described second logical address subspace;
Addressed module 75 specifically for,
If described logical address is positioned at the second logical address subspace of described logical address space, then according to the second physical address subspace of described selection and the mapping relations of described second logical address subspace, determine the physical address in the second physical address subspace of the described selection that described logical address is corresponding.
In another alternative embodiment of the present invention, described logical address space also comprises the 3rd logical address subspace, the size of described 3rd logical address subspace equals the size of the 3rd physical address subspace, described structure module is also for before obtaining addressing instruction at acquisition module 71, by the size subregion of the 3rd storage space according to described 3rd logical address subspace, form at least two the 3rd physical address subspaces;
Select module 72 also for, according to the settings of the 3rd BSR determine select the 3rd physical address subspace;
Mapping block 73 also for, set up the 3rd physical address subspace of described selection and the mapping relations of described 3rd logical address subspace;
Addressed module 75 also for, if described logical address is positioned at described 3rd logical address subspace, then according to the 3rd physical address subspace of described selection and the mapping relations of the 3rd logical address subspace, determine the physical address in the 3rd physical address subspace of the described selection that described logical address is corresponding.
Described first physical address subspace, the second physical address subspace, the 3rd physical address subspace can be SFR memory block, ROM memory block or RAM memory block respectively.More preferably, the size designing each logical address subspace is identical, and correspondingly, the size of each physical address subspace is also identical.
A kind of addressing method that the specific implementation of the present embodiment provides with reference to the embodiment of the present invention.The logical address space that comprise first logical address subspace and second logical address subspace of the embodiment of the present invention by building in advance, when getting addressing instruction, the the first physical address subspace mapping selected by BSR is to the first logical address subspace, add the mapping relations of the second logical address subspace and the second physical address subspace in the logical address space set up in advance, logic-based address space is according to addressing instruction addressing the 3rd physical address subspace or the second physical address subspace, solve in prior art directly address when carrying out data transmission and processing in unified addressing scheme between different B ANK (namely different physical address subspaces) and the problem of BSR need be frequently set, realize directly address without the need to frequently revising the settings of BSR, just can switch between the first physical address subspace and the second physical address subspace by means of only amendment addressing instruction, improve instruction execution efficiency and the data transmission efficiency of microprocessor.
The structural representation of a kind of addressing system that Fig. 8 provides for the embodiment of the present invention.As shown in Figure 8, this system comprises: processor 81, a BSR82, comprise the first physical address space 83 of at least two the first physical address subspaces 831 and comprise the second physical address space 84 of at least one the second physical address subspace 841;
Processor 81, comprises device for addressing 811, and device for addressing 811 is the device as described in a kind of device for addressing of providing as the embodiment of the present invention.
If the second physical address subspace 841 has multiple, this system can further include the 2nd BSR.
Further, if logical address space is except the first logical address subspace and the second logical address subspace, also comprise the 3rd logical address subspace, then this system correspondingly can also comprise three physical address space corresponding with the 3rd logical address subspace, when the 3rd physical address space obtains at least two the 3rd physical address subspaces according to the size subregion of the 3rd logical address subspace, also comprise the 3rd BSR for selecting from least two the 3rd physical address subspaces.
Above-mentioned first physical address space, the second physical address space, the 3rd physical address space can be SFR, ROM or RAM respectively.
In application, processor 81, a BSR82, logical address space can realize in singlechip chip, and the first physical address space, the second physical address space, the 3rd physical address space can be on-chip memory respectively, or chip external memory.
A kind of addressing method that the specific implementation of the present embodiment provides with reference to the embodiment of the present invention and device for addressing.The logical address space that comprise first logical address subspace and second logical address subspace of the embodiment of the present invention by building in advance, when getting addressing instruction, the the first physical address subspace mapping selected by BSR is to the first logical address subspace, add the mapping relations of the second logical address subspace and the second physical address subspace in the logical address space set up in advance, logic-based address space is according to addressing instruction addressing first physical address subspace or the second physical address subspace, solve in prior art directly address when carrying out data transmission and processing in unified addressing scheme between different B ANK (namely different physical address subspaces) and the problem of BSR need be frequently set, realize directly address without the need to frequently revising the settings of BSR, just can switch between the first physical address subspace and the second physical address subspace by means of only amendment addressing instruction, improve instruction execution efficiency and the data transmission efficiency of microprocessor.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (10)
1. an addressing method, is characterized in that, comprising:
Obtain addressing instruction;
The the first physical address subspace selected is determined according to the settings of the first memory block mask register BSR;
The mapping relations of the first logical address subspace in the first physical address subspace setting up described selection and the logical address space built in advance;
Determine the logical address that described addressing instruction is corresponding;
If described logical address is positioned at described first logical address subspace, then according to the first physical address subspace of described selection and the mapping relations of the first logical address subspace, determine the physical address in the first physical address subspace of the described selection that described logical address is corresponding;
If described logical address is positioned at the second logical address subspace of the described logical address space built in advance, then according to the mapping relations of the second physical address subspace of setting up in advance and described second logical address subspace, determine the physical address in the described second physical address subspace that described logical address is corresponding;
Also comprise before described acquisition addressing instruction:
Addressing range according to addressing instruction builds the described logical address space comprising described first logical address subspace and the second logical address subspace;
By the size subregion of the first physical address space according to described first logical address subspace, form at least two the first physical address subspaces, by the size subregion of the second physical address space according to described second logical address subspace, form at least one second physical address subspace.
2. method according to claim 1, is characterized in that, if the second physical address subspace only has one, described formation also comprises after at least one second physical address subspace:
Set up the mapping relations of described second logical address subspace and described second physical address subspace.
3. method according to claim 1, is characterized in that, if the second physical address subspace has at least two, then described method also comprises:
The the second physical address subspace selected is determined according to the settings of the 2nd BSR;
Set up the second physical address subspace of described selection and the mapping relations of described second logical address subspace;
The mapping relations of the second physical address subspace that described basis is set up in advance and described second logical address subspace, determine that the physical address in the described second physical address subspace that described logical address is corresponding specifically comprises:
According to the second physical address subspace of described selection and the mapping relations of described second logical address subspace, determine the physical address in the second physical address subspace of the described selection that described logical address is corresponding.
4. the method according to any one of claim 1-3, is characterized in that, described logical address space also comprises the 3rd logical address subspace, also comprises before described acquisition addressing instruction:
By the size subregion of the 3rd physical address space according to described 3rd logical address subspace, form at least two the 3rd physical address subspaces;
Also comprise after described acquisition addressing instruction:
The 3rd physical address subspace selected is determined according to the settings of the 3rd BSR;
Set up the 3rd physical address subspace of described selection and the mapping relations of described 3rd logical address subspace;
Described determine the logical address that described addressing instruction is corresponding after also comprise:
If described logical address is positioned at described 3rd logical address subspace, then according to the 3rd physical address subspace of described selection and the mapping relations of the 3rd logical address subspace, determine the physical address in the 3rd physical address subspace of the described selection that described logical address is corresponding.
5. a device for addressing, is characterized in that, comprising:
Acquisition module, for obtaining addressing instruction;
Select module, for determining the first physical address subspace selected according to the settings of the first memory block mask register BSR;
Mapping block, for the mapping relations of the first logical address subspace in the first physical address subspace of setting up described selection and the logical address space built in advance;
Determination module, for determining the logical address in the described logical address space that described addressing instruction is corresponding;
Addressed module, if be positioned at described first logical address subspace for described logical address, then according to the first physical address subspace of described selection and the mapping relations of the first logical address subspace, determine the physical address in the first physical address subspace of the described selection that described logical address is corresponding; If described logical address is positioned at the second logical address subspace of the described logical address space built in advance, then according to the mapping relations of the second physical address subspace of setting up in advance and described second logical address subspace, determine the physical address in the described second physical address subspace that described logical address is corresponding;
Build module, before obtaining addressing instruction at described acquisition module, the addressing range according to addressing instruction builds the logical address space comprising described first logical address subspace and the second logical address subspace; By the size subregion of the first physical address space according to described first logical address subspace, form at least two the first physical address subspaces, by the size subregion of the second physical address space according to described second logical address subspace, form at least one second physical address subspace.
6. device according to claim 5, is characterized in that, if the second physical address subspace only has one, described mapping block also for,
After described structure module construction forms at least one second physical address subspace, set up the mapping relations of described second logical address subspace and described second physical address subspace.
7. device according to claim 5, is characterized in that, if the second physical address subspace has at least two, described selection module also for, according to the settings of the 2nd BSR determine select the second physical address subspace;
Described mapping block also for, set up the second physical address subspace of described selection and the mapping relations of described second logical address subspace;
Described addressed module specifically for,
If described logical address is positioned at the second logical address subspace of described logical address space, then according to the second physical address subspace of described selection and the mapping relations of described second logical address subspace, determine the physical address in the second physical address subspace of the described selection that described logical address is corresponding.
8. the device according to any one of claim 5-7, it is characterized in that, described logical address space also comprises the 3rd logical address subspace, described structure module is also for before described acquisition module acquisition addressing instruction, by the size subregion of the 3rd storage space according to described 3rd logical address subspace, form at least two the 3rd physical address subspaces;
Described selection module also for, according to the settings of the 3rd BSR determine select the 3rd physical address subspace;
Described mapping block also for, set up the 3rd physical address subspace of described selection and the mapping relations of described 3rd logical address subspace;
Described addressed module also for, if described logical address is positioned at described 3rd logical address subspace, then according to the 3rd physical address subspace of described selection and the mapping relations of the 3rd logical address subspace, determine the physical address in the 3rd physical address subspace of the described selection that described logical address is corresponding.
9. an addressing system, it is characterized in that, comprising: processor, the first memory block mask register BSR, comprise the first physical address space of at least two the first physical address subspaces and comprise the second physical address space of at least one the second physical address subspace;
Described processor, comprises the device for addressing according to any one of claim 5-8.
10. system according to claim 9, is characterized in that, described first physical address space, the second physical address space are read only memory ROM, random access memory ram or specified register SFR.
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| CN110136666A (en) * | 2019-05-05 | 2019-08-16 | 深圳市华星光电技术有限公司 | Sequence controller and timing control panel |
| CN112015668B (en) * | 2019-05-31 | 2023-03-31 | 西安诺瓦星云科技股份有限公司 | Physical address acquisition method and device and multimedia playing box |
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